Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\UHS_PSRAM_MEMORY\data\apsram_06_f_2ch_32M\APSRAM_TOP.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\ipcore\UHS_PSRAM_MEMORY\data\apsram_06_f_2ch_32M\apsram_code.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9
Device Version C
Created Time Wed May 28 13:47:34 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module UHS_PSRAM_Memory_Interface_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.41s, Peak memory usage = 85.676MB
Running netlist conversion:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 85.676MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.183s, Peak memory usage = 85.676MB
    Optimizing Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.188s, Peak memory usage = 85.676MB
    Optimizing Phase 2: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 85.676MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 85.676MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 85.676MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 85.676MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 85.676MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.332s, Peak memory usage = 85.676MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 85.676MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 85.676MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 113.691MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.349s, Peak memory usage = 113.691MB
Generate output files:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.223s, Peak memory usage = 113.691MB
Total Time and Memory Usage CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 113.691MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 354
Embedded Port 52
I/O Buf 400
    IBUF 217
    OBUF 139
    TBUF 4
    IOBUF 36
    ELVDS_OBUF 4
Register 1312
    DFF 1
    DFFP 8
    DFFPE 16
    DFFC 757
    DFFCE 530
LUT 2275
    LUT2 543
    LUT3 710
    LUT4 1022
ALU 60
    ALU 60
SSRAM 36
    RAM16S4 36
INV 32
    INV 32
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
BSRAM 4
    SDPB 4
CLOCK 3
    CLKDIV 1
    DHCEN 2

Resource Utilization Summary

Resource Usage Utilization
Logic 2583(2307 LUT, 60 ALU, 36 RAM16) / 8640 30%
Register 1312 / 6900 20%
  --Register as Latch 0 / 6900 0%
  --Register as FF 1312 / 6900 20%
BSRAM 4 / 26 16%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 memory_clk Base 20.000 50.000 0.000 10.000 memory_clk_ibuf/I
2 memory_clk_p Base 20.000 50.000 0.000 10.000 memory_clk_p_ibuf/I
3 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
4 clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 memory_clk_ibuf/I memory_clk clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 114.016(MHz) 6 TOP
2 clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 111.408(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.904
Data Arrival Time 1.589
Data Required Time 10.493
From u_psram_sync/cs_memsync_4_s0
To u_dhcen_clk_x2p
Launch Clk clk[F]
Latch Clk memory_clk_p[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_sync/cs_memsync_4_s0/CLK
0.878 0.340 tC2Q RF 8 u_psram_sync/cs_memsync_4_s0/Q
1.589 0.711 tNET FF 1 u_dhcen_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk_p
10.000 0.000 tCL FF 1 memory_clk_p_ibuf/I
10.000 0.000 tINS FF 1 memory_clk_p_ibuf/O
10.711 0.711 tNET FF 3 u_dhcen_clk_x2p/CLKIN
10.681 -0.030 tUnc u_dhcen_clk_x2p
10.493 -0.188 tSu 1 u_dhcen_clk_x2p
Path Statistics:
Clock Skew: 0.173
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 8.904
Data Arrival Time 1.589
Data Required Time 10.493
From u_psram_sync/cs_memsync_4_s0
To u_dhcen_clk_x2
Launch Clk clk[F]
Latch Clk memory_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_sync/cs_memsync_4_s0/CLK
0.878 0.340 tC2Q RF 8 u_psram_sync/cs_memsync_4_s0/Q
1.589 0.711 tNET FF 1 u_dhcen_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 memory_clk
10.000 0.000 tCL FF 1 memory_clk_ibuf/I
10.000 0.000 tINS FF 1 memory_clk_ibuf/O
10.711 0.711 tNET FF 3 u_dhcen_clk_x2/CLKIN
10.681 -0.030 tUnc u_dhcen_clk_x2
10.493 -0.188 tSu 1 u_dhcen_clk_x2
Path Statistics:
Clock Skew: 0.173
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 11.229
Data Arrival Time 9.012
Data Required Time 20.242
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_13_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_sync/n44_s3/I1
3.929 0.814 tINS FF 5 u_psram_sync/n44_s3/F
4.640 0.711 tNET FF 1 u_psram_sync/n40_s2/I2
5.249 0.609 tINS FF 3 u_psram_sync/n40_s2/F
5.961 0.711 tNET FF 1 u_psram_sync/n39_s2/I1
6.775 0.814 tINS FF 3 u_psram_sync/n39_s2/F
7.487 0.711 tNET FF 1 u_psram_sync/n38_s1/I1
8.301 0.814 tINS FF 1 u_psram_sync/n38_s1/F
9.012 0.711 tNET FF 1 u_psram_sync/lock_cnt_13_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_13_s1/CLK
20.242 -0.296 tSu 1 u_psram_sync/lock_cnt_13_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.867, 45.627%; route: 4.268, 50.365%; tC2Q: 0.340, 4.008%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 11.279
Data Arrival Time 8.963
Data Required Time 20.242
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_14_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_sync/n44_s3/I1
3.929 0.814 tINS FF 5 u_psram_sync/n44_s3/F
4.640 0.711 tNET FF 1 u_psram_sync/n40_s2/I2
5.249 0.609 tINS FF 3 u_psram_sync/n40_s2/F
5.961 0.711 tNET FF 1 u_psram_sync/n39_s2/I1
6.775 0.814 tINS FF 3 u_psram_sync/n39_s2/F
7.487 0.711 tNET FF 1 u_psram_sync/n37_s1/I0
8.251 0.765 tINS FF 1 u_psram_sync/n37_s1/F
8.963 0.711 tNET FF 1 u_psram_sync/lock_cnt_14_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_14_s1/CLK
20.242 -0.296 tSu 1 u_psram_sync/lock_cnt_14_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.817, 45.306%; route: 4.268, 50.663%; tC2Q: 0.340, 4.031%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 11.435
Data Arrival Time 8.807
Data Required Time 20.242
From u_psram_sync/lock_cnt_1_s3
To u_psram_sync/lock_cnt_15_s1
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 31 clk_ibuf/O
0.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_1_s3/CLK
0.878 0.340 tC2Q RF 5 u_psram_sync/lock_cnt_1_s3/Q
1.589 0.711 tNET FF 1 u_psram_sync/n47_s2/I1
2.403 0.814 tINS FF 4 u_psram_sync/n47_s2/F
3.115 0.711 tNET FF 1 u_psram_sync/n44_s3/I1
3.929 0.814 tINS FF 5 u_psram_sync/n44_s3/F
4.640 0.711 tNET FF 1 u_psram_sync/n40_s2/I2
5.249 0.609 tINS FF 3 u_psram_sync/n40_s2/F
5.961 0.711 tNET FF 1 u_psram_sync/n39_s2/I1
6.775 0.814 tINS FF 3 u_psram_sync/n39_s2/F
7.487 0.711 tNET FF 1 u_psram_sync/n36_s1/I2
8.096 0.609 tINS FF 1 u_psram_sync/n36_s1/F
8.807 0.711 tNET FF 1 u_psram_sync/lock_cnt_15_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 31 clk_ibuf/O
20.538 0.538 tNET RR 1 u_psram_sync/lock_cnt_15_s1/CLK
20.242 -0.296 tSu 1 u_psram_sync/lock_cnt_15_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.661, 44.277%; route: 4.268, 51.616%; tC2Q: 0.340, 4.107%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%