Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\a.cst
Timing Constraint File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\fpga_project.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW1NR-LV9MG100PAC7/I6
Device	GW1NR-9
Device Version	C
Created Time	Wed May 28 13:47:58 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C7/I6
Hold Delay Model	Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed	10551
Numbers of Endpoints Analyzed	6577
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	cl_osc	Base	20.000	50.000	0.000	10.000			clk
2	memory_clk	Base	20.000	50.000	0.000	10.000			your_instance_name/rpll_inst/CLKOUT
3	memory_clk_p	Base	20.000	50.000	0.000	10.000			your_instance_name/rpll_inst/CLKOUTP
4	clk_d	Base	80.000	12.500	0.000	40.000			your_instance_name/rpll_inst/CLKOUTD
5	user_clk	Generated	40.000	25.000	0.000	20.000	your_instance_name/rpll_inst/CLKOUT	memory_clk	u_PSRAM_TOP/clkdiv/CLKOUT
6	your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Generated	60.000	16.667	0.000	30.000	clk_ibuf/I	cl_osc	your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	cl_osc	50.000(MHz)	245.026(MHz)	4	TOP
2	clk_d	12.500(MHz)	134.649(MHz)	5	TOP
3	user_clk	25.000(MHz)	97.348(MHz)	6	TOP

No timing paths to get frequency of memory_clk!

No timing paths to get frequency of memory_clk_p!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
cl_osc	Setup	0.000	0
cl_osc	Hold	0.000	0
memory_clk	Setup	0.000	0
memory_clk	Hold	0.000	0
memory_clk_p	Setup	0.000	0
memory_clk_p	Hold	0.000	0
clk_d	Setup	0.000	0
clk_d	Hold	0.000	0
user_clk	Setup	0.000	0
user_clk	Hold	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	15.919	u_reset_key/cnt_1_s0/Q	u_reset_key/key_1_s0/CE	cl_osc:[R]	cl_osc:[R]	20.000	0.000	4.049
2	17.220	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_19_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.484
3	17.262	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_18_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.442
4	17.304	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_17_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.399
5	17.347	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_16_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.357
6	17.389	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_15_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.315
7	17.431	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_14_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.273
8	17.473	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_13_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.230
9	17.515	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_12_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.188
10	17.558	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_11_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.146
11	17.600	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_10_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.104
12	17.642	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_9_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.061
13	17.684	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_8_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.019
14	17.727	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_7_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.977
15	17.732	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_18_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.236
16	17.732	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_19_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.236
17	17.757	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_0_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	2.211
18	17.769	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_6_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.935
19	17.811	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_5_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.892
20	17.853	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_4_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.850
21	17.896	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_3_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.808
22	17.938	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_2_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.766
23	17.998	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_1_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.970
24	17.998	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_2_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.970
25	17.998	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_3_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	0.000	1.970

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.355	u_PSRAM_TOP/u_psram_top0/rd_data_d_50_s0/Q	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[18]	user_clk:[R]	user_clk:[R]	0.000	0.000	0.418
2	0.355	u_PSRAM_TOP/u_psram_top0/rd_data_d_49_s0/Q	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[17]	user_clk:[R]	user_clk:[R]	0.000	0.000	0.418
3	0.380	u_PSRAM_TOP/u_psram_top0/rd_data_d_58_s0/Q	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[26]	user_clk:[R]	user_clk:[R]	0.000	0.000	0.443
4	0.380	u_PSRAM_TOP/u_psram_top0/rd_data_d_38_s0/Q	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[6]	user_clk:[R]	user_clk:[R]	0.000	0.000	0.443
5	0.524	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_0_s0/D	cl_osc:[R]	cl_osc:[R]	0.000	0.000	0.524
6	0.524	u_test1/check_data_39_s1/Q	u_test1/check_data_39_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
7	0.524	u_test1/cyc_cnt_9_s1/Q	u_test1/cyc_cnt_9_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
8	0.524	u_test1/wr_data_add_54_s1/Q	u_test1/wr_data_add_54_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
9	0.524	u_test1/wr_data_add_63_s1/Q	u_test1/wr_data_add_63_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
10	0.524	u_test0/check_data_50_s1/Q	u_test0/check_data_50_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
11	0.524	u_test0/cyc_cnt_5_s1/Q	u_test0/cyc_cnt_5_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
12	0.524	u_test0/cyc_cnt_6_s1/Q	u_test0/cyc_cnt_6_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
13	0.524	u_test0/cyc_cnt_9_s1/Q	u_test0/cyc_cnt_9_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
14	0.524	u_test0/wr_data_add_16_s1/Q	u_test0/wr_data_add_16_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
15	0.524	u_test0/wr_data_add_18_s1/Q	u_test0/wr_data_add_18_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
16	0.524	u_test0/wr_data_add_44_s1/Q	u_test0/wr_data_add_44_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
17	0.524	u_test0/wr_data_add_52_s1/Q	u_test0/wr_data_add_52_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
18	0.524	u_test0/wr_data_add_57_s1/Q	u_test0/wr_data_add_57_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
19	0.524	u_test0/wr_data_add_63_s1/Q	u_test0/wr_data_add_63_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
20	0.524	u_test0/WR_CNT_7_s1/Q	u_test0/WR_CNT_7_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
21	0.524	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/Q	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
22	0.524	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/Q	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
23	0.524	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/Q	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
24	0.524	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/Q	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524
25	0.524	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/Q	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/D	user_clk:[R]	user_clk:[R]	0.000	0.000	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/key_rst_r_s0
2	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_19_s0
3	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_17_s0
4	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_13_s0
5	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_5_s0
6	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_6_s0
7	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_14_s0
8	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_7_s0
9	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_8_s0
10	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_18_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	15.919
Data Arrival Time	8.460
Data Required Time	24.378
From	u_reset_key/cnt_1_s0
To	u_reset_key/key_1_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R24C11[0][B]	u_reset_key/cnt_1_s0/CLK
4.750	0.340	tC2Q	RF	2	R24C11[0][B]	u_reset_key/cnt_1_s0/Q
5.115	0.365	tNET	FF	1	R24C11[3][B]	u_reset_key/n96_s3/I1
5.876	0.760	tINS	FR	1	R24C11[3][B]	u_reset_key/n96_s3/F
6.186	0.310	tNET	RR	1	R24C12[3][A]	u_reset_key/n96_s1/I0
6.972	0.786	tINS	RR	1	R24C12[3][A]	u_reset_key/n96_s1/F
7.283	0.310	tNET	RR	1	R25C12[0][A]	u_reset_key/n96_s0/I0
7.877	0.594	tINS	RR	1	R25C12[0][A]	u_reset_key/n96_s0/F
8.460	0.583	tNET	RR	1	R25C9[0][B]	u_reset_key/key_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R25C9[0][B]	u_reset_key/key_1_s0/CLK
24.378	-0.032	tSu		1	R25C9[0][B]	u_reset_key/key_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.141, 52.870%; route: 1.569, 38.742%; tC2Q: 0.340, 8.388%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	17.220
Data Arrival Time	6.894
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_19_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C13[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C13[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C13[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C13[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C13[2][B]	u_reset_key/n19_s/CIN
6.435	0.042	tINS	FF	1	R24C13[2][B]	u_reset_key/n19_s/COUT
6.435	0.000	tNET	FF	2	R24C14[0][A]	u_reset_key/n18_s/CIN
6.477	0.042	tINS	FF	1	R24C14[0][A]	u_reset_key/n18_s/COUT
6.477	0.000	tNET	FF	2	R24C14[0][B]	u_reset_key/n17_s/CIN
6.894	0.417	tINS	FF	1	R24C14[0][B]	u_reset_key/n17_s/SUM
6.894	0.000	tNET	FF	1	R24C14[0][B]	u_reset_key/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C14[0][B]	u_reset_key/cnt_19_s0/CLK
24.114	-0.296	tSu		1	R24C14[0][B]	u_reset_key/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.543, 62.113%; route: 0.601, 24.213%; tC2Q: 0.340, 13.674%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	17.262
Data Arrival Time	6.852
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_18_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C13[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C13[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C13[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C13[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C13[2][B]	u_reset_key/n19_s/CIN
6.435	0.042	tINS	FF	1	R24C13[2][B]	u_reset_key/n19_s/COUT
6.435	0.000	tNET	FF	2	R24C14[0][A]	u_reset_key/n18_s/CIN
6.852	0.417	tINS	FF	1	R24C14[0][A]	u_reset_key/n18_s/SUM
6.852	0.000	tNET	FF	1	R24C14[0][A]	u_reset_key/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C14[0][A]	u_reset_key/cnt_18_s0/CLK
24.114	-0.296	tSu		1	R24C14[0][A]	u_reset_key/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.501, 61.458%; route: 0.601, 24.632%; tC2Q: 0.340, 13.910%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	17.304
Data Arrival Time	6.810
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_17_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C13[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C13[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C13[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C13[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C13[2][B]	u_reset_key/n19_s/CIN
6.810	0.417	tINS	FF	1	R24C13[2][B]	u_reset_key/n19_s/SUM
6.810	0.000	tNET	FF	1	R24C13[2][B]	u_reset_key/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[2][B]	u_reset_key/cnt_17_s0/CLK
24.114	-0.296	tSu		1	R24C13[2][B]	u_reset_key/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.458, 60.779%; route: 0.601, 25.066%; tC2Q: 0.340, 14.155%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	17.347
Data Arrival Time	6.768
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_16_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C13[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C13[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C13[2][A]	u_reset_key/n20_s/CIN
6.768	0.417	tINS	FF	1	R24C13[2][A]	u_reset_key/n20_s/SUM
6.768	0.000	tNET	FF	1	R24C13[2][A]	u_reset_key/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[2][A]	u_reset_key/cnt_16_s0/CLK
24.114	-0.296	tSu		1	R24C13[2][A]	u_reset_key/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.416, 60.076%; route: 0.601, 25.515%; tC2Q: 0.340, 14.409%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	17.389
Data Arrival Time	6.725
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_15_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C13[1][B]	u_reset_key/n21_s/CIN
6.725	0.417	tINS	FF	1	R24C13[1][B]	u_reset_key/n21_s/SUM
6.725	0.000	tNET	FF	1	R24C13[1][B]	u_reset_key/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[1][B]	u_reset_key/cnt_15_s0/CLK
24.114	-0.296	tSu		1	R24C13[1][B]	u_reset_key/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.374, 59.348%; route: 0.601, 25.981%; tC2Q: 0.340, 14.672%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	17.431
Data Arrival Time	6.683
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_14_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C13[1][A]	u_reset_key/n22_s/CIN
6.683	0.417	tINS	FF	1	R24C13[1][A]	u_reset_key/n22_s/SUM
6.683	0.000	tNET	FF	1	R24C13[1][A]	u_reset_key/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[1][A]	u_reset_key/cnt_14_s0/CLK
24.114	-0.296	tSu		1	R24C13[1][A]	u_reset_key/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.332, 58.592%; route: 0.601, 26.463%; tC2Q: 0.340, 14.944%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	17.473
Data Arrival Time	6.641
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_13_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C13[0][B]	u_reset_key/n23_s/CIN
6.641	0.417	tINS	FF	1	R24C13[0][B]	u_reset_key/n23_s/SUM
6.641	0.000	tNET	FF	1	R24C13[0][B]	u_reset_key/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[0][B]	u_reset_key/cnt_13_s0/CLK
24.114	-0.296	tSu		1	R24C13[0][B]	u_reset_key/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.289, 57.808%; route: 0.601, 26.965%; tC2Q: 0.340, 15.227%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	17.515
Data Arrival Time	6.599
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_12_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C13[0][A]	u_reset_key/n24_s/CIN
6.599	0.417	tINS	FF	1	R24C13[0][A]	u_reset_key/n24_s/SUM
6.599	0.000	tNET	FF	1	R24C13[0][A]	u_reset_key/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[0][A]	u_reset_key/cnt_12_s0/CLK
24.114	-0.296	tSu		1	R24C13[0][A]	u_reset_key/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.247, 56.994%; route: 0.601, 27.485%; tC2Q: 0.340, 15.521%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	17.558
Data Arrival Time	6.557
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_11_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C12[2][B]	u_reset_key/n25_s/CIN
6.557	0.417	tINS	FF	1	R24C12[2][B]	u_reset_key/n25_s/SUM
6.557	0.000	tNET	FF	1	R24C12[2][B]	u_reset_key/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[2][B]	u_reset_key/cnt_11_s0/CLK
24.114	-0.296	tSu		1	R24C12[2][B]	u_reset_key/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.205, 56.147%; route: 0.601, 28.026%; tC2Q: 0.340, 15.827%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	17.600
Data Arrival Time	6.514
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_10_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C12[2][A]	u_reset_key/n26_s/CIN
6.514	0.417	tINS	FF	1	R24C12[2][A]	u_reset_key/n26_s/SUM
6.514	0.000	tNET	FF	1	R24C12[2][A]	u_reset_key/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[2][A]	u_reset_key/cnt_10_s0/CLK
24.114	-0.296	tSu		1	R24C12[2][A]	u_reset_key/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.163, 55.267%; route: 0.601, 28.589%; tC2Q: 0.340, 16.144%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	17.642
Data Arrival Time	6.472
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_9_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C12[1][B]	u_reset_key/n27_s/CIN
6.472	0.417	tINS	FF	1	R24C12[1][B]	u_reset_key/n27_s/SUM
6.472	0.000	tNET	FF	1	R24C12[1][B]	u_reset_key/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[1][B]	u_reset_key/cnt_9_s0/CLK
24.114	-0.296	tSu		1	R24C12[1][B]	u_reset_key/cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.120, 54.350%; route: 0.601, 29.174%; tC2Q: 0.340, 16.475%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	17.684
Data Arrival Time	6.430
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_8_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C12[1][A]	u_reset_key/n28_s/CIN
6.430	0.417	tINS	FF	1	R24C12[1][A]	u_reset_key/n28_s/SUM
6.430	0.000	tNET	FF	1	R24C12[1][A]	u_reset_key/cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[1][A]	u_reset_key/cnt_8_s0/CLK
24.114	-0.296	tSu		1	R24C12[1][A]	u_reset_key/cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.078, 53.395%; route: 0.601, 29.785%; tC2Q: 0.340, 16.820%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	17.727
Data Arrival Time	6.388
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_7_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C12[0][B]	u_reset_key/n29_s/CIN
6.388	0.417	tINS	FF	1	R24C12[0][B]	u_reset_key/n29_s/SUM
6.388	0.000	tNET	FF	1	R24C12[0][B]	u_reset_key/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[0][B]	u_reset_key/cnt_7_s0/CLK
24.114	-0.296	tSu		1	R24C12[0][B]	u_reset_key/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.036, 52.400%; route: 0.601, 30.421%; tC2Q: 0.340, 17.179%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	17.732
Data Arrival Time	6.646
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_18_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.646	0.861	tNET	RR	1	R24C14[0][A]	u_reset_key/cnt_18_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C14[0][A]	u_reset_key/cnt_18_s0/CLK
24.378	-0.032	tSu		1	R24C14[0][A]	u_reset_key/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.167%; route: 1.110, 49.642%; tC2Q: 0.340, 15.191%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	17.732
Data Arrival Time	6.646
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_19_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.646	0.861	tNET	RR	1	R24C14[0][B]	u_reset_key/cnt_19_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C14[0][B]	u_reset_key/cnt_19_s0/CLK
24.378	-0.032	tSu		1	R24C14[0][B]	u_reset_key/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.167%; route: 1.110, 49.642%; tC2Q: 0.340, 15.191%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	17.757
Data Arrival Time	6.622
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_0_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.622	0.836	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
24.378	-0.032	tSu		1	R25C10[0][A]	u_reset_key/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.559%; route: 1.085, 49.081%; tC2Q: 0.340, 15.361%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	17.769
Data Arrival Time	6.345
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_6_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C12[0][A]	u_reset_key/n30_s/CIN
6.345	0.417	tINS	FF	1	R24C12[0][A]	u_reset_key/n30_s/SUM
6.345	0.000	tNET	FF	1	R24C12[0][A]	u_reset_key/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C12[0][A]	u_reset_key/cnt_6_s0/CLK
24.114	-0.296	tSu		1	R24C12[0][A]	u_reset_key/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.994, 51.361%; route: 0.601, 31.085%; tC2Q: 0.340, 17.554%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	17.811
Data Arrival Time	6.303
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_5_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C11[2][B]	u_reset_key/n31_s/CIN
6.303	0.417	tINS	FF	1	R24C11[2][B]	u_reset_key/n31_s/SUM
6.303	0.000	tNET	FF	1	R24C11[2][B]	u_reset_key/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[2][B]	u_reset_key/cnt_5_s0/CLK
24.114	-0.296	tSu		1	R24C11[2][B]	u_reset_key/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.951, 50.275%; route: 0.601, 31.779%; tC2Q: 0.340, 17.946%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	17.853
Data Arrival Time	6.261
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_4_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C11[2][A]	u_reset_key/n32_s/CIN
6.261	0.417	tINS	FF	1	R24C11[2][A]	u_reset_key/n32_s/SUM
6.261	0.000	tNET	FF	1	R24C11[2][A]	u_reset_key/cnt_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[2][A]	u_reset_key/cnt_4_s0/CLK
24.114	-0.296	tSu		1	R24C11[2][A]	u_reset_key/cnt_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.909, 49.140%; route: 0.601, 32.504%; tC2Q: 0.340, 18.356%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	17.896
Data Arrival Time	6.219
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_3_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C11[1][B]	u_reset_key/n33_s/CIN
6.219	0.417	tINS	FF	1	R24C11[1][B]	u_reset_key/n33_s/SUM
6.219	0.000	tNET	FF	1	R24C11[1][B]	u_reset_key/cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[1][B]	u_reset_key/cnt_3_s0/CLK
24.114	-0.296	tSu		1	R24C11[1][B]	u_reset_key/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.867, 47.952%; route: 0.601, 33.264%; tC2Q: 0.340, 18.785%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	17.938
Data Arrival Time	6.176
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_2_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C11[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C11[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C11[1][A]	u_reset_key/n34_s/CIN
6.176	0.417	tINS	RF	1	R24C11[1][A]	u_reset_key/n34_s/SUM
6.176	0.000	tNET	FF	1	R24C11[1][A]	u_reset_key/cnt_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[1][A]	u_reset_key/cnt_2_s0/CLK
24.114	-0.296	tSu		1	R24C11[1][A]	u_reset_key/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.825, 46.707%; route: 0.601, 34.059%; tC2Q: 0.340, 19.234%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	17.998
Data Arrival Time	6.381
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_1_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.381	0.595	tNET	RR	1	R24C11[0][B]	u_reset_key/cnt_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[0][B]	u_reset_key/cnt_1_s0/CLK
24.378	-0.032	tSu		1	R24C11[0][B]	u_reset_key/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 39.908%; route: 0.844, 42.853%; tC2Q: 0.340, 17.239%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	17.998
Data Arrival Time	6.381
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_2_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.381	0.595	tNET	RR	1	R24C11[1][A]	u_reset_key/cnt_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[1][A]	u_reset_key/cnt_2_s0/CLK
24.378	-0.032	tSu		1	R24C11[1][A]	u_reset_key/cnt_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 39.908%; route: 0.844, 42.853%; tC2Q: 0.340, 17.239%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	17.998
Data Arrival Time	6.381
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_3_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C11[0][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C11[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C11[0][B]	u_reset_key/key_an_s0/F
6.381	0.595	tNET	RR	1	R24C11[1][B]	u_reset_key/cnt_3_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C11[1][B]	u_reset_key/cnt_3_s0/CLK
24.378	-0.032	tSu		1	R24C11[1][B]	u_reset_key/cnt_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 39.908%; route: 0.844, 42.853%; tC2Q: 0.340, 17.239%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.355
Data Arrival Time	0.555
Data Required Time	0.201
From	u_PSRAM_TOP/u_psram_top0/rd_data_d_50_s0
To	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C21[1][B]	u_PSRAM_TOP/u_psram_top0/rd_data_d_50_s0/CLK
0.384	0.247	tC2Q	RF	1	R11C21[1][B]	u_PSRAM_TOP/u_psram_top0/rd_data_d_50_s0/Q
0.555	0.171	tNET	FF	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[18]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	0.355
Data Arrival Time	0.555
Data Required Time	0.201
From	u_PSRAM_TOP/u_psram_top0/rd_data_d_49_s0
To	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C21[1][A]	u_PSRAM_TOP/u_psram_top0/rd_data_d_49_s0/CLK
0.384	0.247	tC2Q	RF	1	R11C21[1][A]	u_PSRAM_TOP/u_psram_top0/rd_data_d_49_s0/Q
0.555	0.171	tNET	FF	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.171, 40.960%; tC2Q: 0.247, 59.040%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.380
Data Arrival Time	0.580
Data Required Time	0.201
From	u_PSRAM_TOP/u_psram_top0/rd_data_d_58_s0
To	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C22[0][B]	u_PSRAM_TOP/u_psram_top0/rd_data_d_58_s0/CLK
0.384	0.247	tC2Q	RR	1	R12C22[0][B]	u_PSRAM_TOP/u_psram_top0/rd_data_d_58_s0/Q
0.580	0.196	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 44.283%; tC2Q: 0.247, 55.717%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.380
Data Arrival Time	0.580
Data Required Time	0.201
From	u_PSRAM_TOP/u_psram_top0/rd_data_d_38_s0
To	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C20[2][A]	u_PSRAM_TOP/u_psram_top0/rd_data_d_38_s0/CLK
0.384	0.247	tC2Q	RR	1	R12C20[2][A]	u_PSRAM_TOP/u_psram_top0/rd_data_d_38_s0/Q
0.580	0.196	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s/CLKA
0.201	0.064	tHld		1	BSRAM_R10[5]	u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/data_mem_data_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.196, 44.283%; tC2Q: 0.247, 55.717%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_0_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
3.126	3.126	tINS	RR	24	IOT29[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R25C10[0][A]	u_reset_key/cnt_0_s0/Q
3.512	0.002	tNET	RR	1	R25C10[0][A]	u_reset_key/n36_s2/I0
3.788	0.276	tINS	RF	1	R25C10[0][A]	u_reset_key/n36_s2/F
3.788	0.000	tNET	FF	1	R25C10[0][A]	u_reset_key/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
3.126	3.126	tINS	RR	24	IOT29[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R25C10[0][A]	u_reset_key/cnt_0_s0/CLK
3.263	0.000	tHld		1	R25C10[0][A]	u_reset_key/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test1/check_data_39_s1
To	u_test1/check_data_39_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R25C43[0][A]	u_test1/check_data_39_s1/CLK
0.384	0.247	tC2Q	RR	4	R25C43[0][A]	u_test1/check_data_39_s1/Q
0.386	0.002	tNET	RR	1	R25C43[0][A]	u_test1/n1603_s2/I3
0.661	0.276	tINS	RF	1	R25C43[0][A]	u_test1/n1603_s2/F
0.661	0.000	tNET	FF	1	R25C43[0][A]	u_test1/check_data_39_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R25C43[0][A]	u_test1/check_data_39_s1/CLK
0.137	0.000	tHld		1	R25C43[0][A]	u_test1/check_data_39_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test1/cyc_cnt_9_s1
To	u_test1/cyc_cnt_9_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C43[0][A]	u_test1/cyc_cnt_9_s1/CLK
0.384	0.247	tC2Q	RR	2	R18C43[0][A]	u_test1/cyc_cnt_9_s1/Q
0.386	0.002	tNET	RR	1	R18C43[0][A]	u_test1/n1446_s2/I3
0.661	0.276	tINS	RF	1	R18C43[0][A]	u_test1/n1446_s2/F
0.661	0.000	tNET	FF	1	R18C43[0][A]	u_test1/cyc_cnt_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C43[0][A]	u_test1/cyc_cnt_9_s1/CLK
0.137	0.000	tHld		1	R18C43[0][A]	u_test1/cyc_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test1/wr_data_add_54_s1
To	u_test1/wr_data_add_54_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C39[1][A]	u_test1/wr_data_add_54_s1/CLK
0.384	0.247	tC2Q	RR	5	R17C39[1][A]	u_test1/wr_data_add_54_s1/Q
0.386	0.002	tNET	RR	1	R17C39[1][A]	u_test1/n682_s1/I2
0.661	0.276	tINS	RF	1	R17C39[1][A]	u_test1/n682_s1/F
0.661	0.000	tNET	FF	1	R17C39[1][A]	u_test1/wr_data_add_54_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C39[1][A]	u_test1/wr_data_add_54_s1/CLK
0.137	0.000	tHld		1	R17C39[1][A]	u_test1/wr_data_add_54_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test1/wr_data_add_63_s1
To	u_test1/wr_data_add_63_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C43[0][A]	u_test1/wr_data_add_63_s1/CLK
0.384	0.247	tC2Q	RR	2	R16C43[0][A]	u_test1/wr_data_add_63_s1/Q
0.386	0.002	tNET	RR	1	R16C43[0][A]	u_test1/n673_s1/I2
0.661	0.276	tINS	RF	1	R16C43[0][A]	u_test1/n673_s1/F
0.661	0.000	tNET	FF	1	R16C43[0][A]	u_test1/wr_data_add_63_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C43[0][A]	u_test1/wr_data_add_63_s1/CLK
0.137	0.000	tHld		1	R16C43[0][A]	u_test1/wr_data_add_63_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/check_data_50_s1
To	u_test0/check_data_50_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C6[0][A]	u_test0/check_data_50_s1/CLK
0.384	0.247	tC2Q	RR	4	R17C6[0][A]	u_test0/check_data_50_s1/Q
0.386	0.002	tNET	RR	1	R17C6[0][A]	u_test0/n1592_s2/I3
0.661	0.276	tINS	RF	1	R17C6[0][A]	u_test0/n1592_s2/F
0.661	0.000	tNET	FF	1	R17C6[0][A]	u_test0/check_data_50_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C6[0][A]	u_test0/check_data_50_s1/CLK
0.137	0.000	tHld		1	R17C6[0][A]	u_test0/check_data_50_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/cyc_cnt_5_s1
To	u_test0/cyc_cnt_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C3[0][A]	u_test0/cyc_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	3	R21C3[0][A]	u_test0/cyc_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R21C3[0][A]	u_test0/n1450_s2/I3
0.661	0.276	tINS	RF	1	R21C3[0][A]	u_test0/n1450_s2/F
0.661	0.000	tNET	FF	1	R21C3[0][A]	u_test0/cyc_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C3[0][A]	u_test0/cyc_cnt_5_s1/CLK
0.137	0.000	tHld		1	R21C3[0][A]	u_test0/cyc_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/cyc_cnt_6_s1
To	u_test0/cyc_cnt_6_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C2[0][A]	u_test0/cyc_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	4	R18C2[0][A]	u_test0/cyc_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R18C2[0][A]	u_test0/n1449_s2/I1
0.661	0.276	tINS	RF	1	R18C2[0][A]	u_test0/n1449_s2/F
0.661	0.000	tNET	FF	1	R18C2[0][A]	u_test0/cyc_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C2[0][A]	u_test0/cyc_cnt_6_s1/CLK
0.137	0.000	tHld		1	R18C2[0][A]	u_test0/cyc_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/cyc_cnt_9_s1
To	u_test0/cyc_cnt_9_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C3[1][A]	u_test0/cyc_cnt_9_s1/CLK
0.384	0.247	tC2Q	RR	2	R18C3[1][A]	u_test0/cyc_cnt_9_s1/Q
0.386	0.002	tNET	RR	1	R18C3[1][A]	u_test0/n1446_s2/I3
0.661	0.276	tINS	RF	1	R18C3[1][A]	u_test0/n1446_s2/F
0.661	0.000	tNET	FF	1	R18C3[1][A]	u_test0/cyc_cnt_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C3[1][A]	u_test0/cyc_cnt_9_s1/CLK
0.137	0.000	tHld		1	R18C3[1][A]	u_test0/cyc_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_16_s1
To	u_test0/wr_data_add_16_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C9[1][A]	u_test0/wr_data_add_16_s1/CLK
0.384	0.247	tC2Q	RR	4	R9C9[1][A]	u_test0/wr_data_add_16_s1/Q
0.386	0.002	tNET	RR	1	R9C9[1][A]	u_test0/n720_s1/I2
0.661	0.276	tINS	RF	1	R9C9[1][A]	u_test0/n720_s1/F
0.661	0.000	tNET	FF	1	R9C9[1][A]	u_test0/wr_data_add_16_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C9[1][A]	u_test0/wr_data_add_16_s1/CLK
0.137	0.000	tHld		1	R9C9[1][A]	u_test0/wr_data_add_16_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_18_s1
To	u_test0/wr_data_add_18_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C9[0][A]	u_test0/wr_data_add_18_s1/CLK
0.384	0.247	tC2Q	RR	6	R11C9[0][A]	u_test0/wr_data_add_18_s1/Q
0.386	0.002	tNET	RR	1	R11C9[0][A]	u_test0/n718_s1/I0
0.661	0.276	tINS	RF	1	R11C9[0][A]	u_test0/n718_s1/F
0.661	0.000	tNET	FF	1	R11C9[0][A]	u_test0/wr_data_add_18_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C9[0][A]	u_test0/wr_data_add_18_s1/CLK
0.137	0.000	tHld		1	R11C9[0][A]	u_test0/wr_data_add_18_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_44_s1
To	u_test0/wr_data_add_44_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C4[0][A]	u_test0/wr_data_add_44_s1/CLK
0.384	0.247	tC2Q	RR	5	R16C4[0][A]	u_test0/wr_data_add_44_s1/Q
0.386	0.002	tNET	RR	1	R16C4[0][A]	u_test0/n692_s1/I2
0.661	0.276	tINS	RF	1	R16C4[0][A]	u_test0/n692_s1/F
0.661	0.000	tNET	FF	1	R16C4[0][A]	u_test0/wr_data_add_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C4[0][A]	u_test0/wr_data_add_44_s1/CLK
0.137	0.000	tHld		1	R16C4[0][A]	u_test0/wr_data_add_44_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_52_s1
To	u_test0/wr_data_add_52_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C7[1][A]	u_test0/wr_data_add_52_s1/CLK
0.384	0.247	tC2Q	RR	4	R16C7[1][A]	u_test0/wr_data_add_52_s1/Q
0.386	0.002	tNET	RR	1	R16C7[1][A]	u_test0/n684_s1/I2
0.661	0.276	tINS	RF	1	R16C7[1][A]	u_test0/n684_s1/F
0.661	0.000	tNET	FF	1	R16C7[1][A]	u_test0/wr_data_add_52_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C7[1][A]	u_test0/wr_data_add_52_s1/CLK
0.137	0.000	tHld		1	R16C7[1][A]	u_test0/wr_data_add_52_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_57_s1
To	u_test0/wr_data_add_57_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C7[0][A]	u_test0/wr_data_add_57_s1/CLK
0.384	0.247	tC2Q	RR	3	R16C7[0][A]	u_test0/wr_data_add_57_s1/Q
0.386	0.002	tNET	RR	1	R16C7[0][A]	u_test0/n679_s1/I2
0.661	0.276	tINS	RF	1	R16C7[0][A]	u_test0/n679_s1/F
0.661	0.000	tNET	FF	1	R16C7[0][A]	u_test0/wr_data_add_57_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C7[0][A]	u_test0/wr_data_add_57_s1/CLK
0.137	0.000	tHld		1	R16C7[0][A]	u_test0/wr_data_add_57_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/wr_data_add_63_s1
To	u_test0/wr_data_add_63_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C5[1][A]	u_test0/wr_data_add_63_s1/CLK
0.384	0.247	tC2Q	RR	2	R16C5[1][A]	u_test0/wr_data_add_63_s1/Q
0.386	0.002	tNET	RR	1	R16C5[1][A]	u_test0/n673_s1/I2
0.661	0.276	tINS	RF	1	R16C5[1][A]	u_test0/n673_s1/F
0.661	0.000	tNET	FF	1	R16C5[1][A]	u_test0/wr_data_add_63_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C5[1][A]	u_test0/wr_data_add_63_s1/CLK
0.137	0.000	tHld		1	R16C5[1][A]	u_test0/wr_data_add_63_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test0/WR_CNT_7_s1
To	u_test0/WR_CNT_7_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R5C5[1][A]	u_test0/WR_CNT_7_s1/CLK
0.384	0.247	tC2Q	RR	4	R5C5[1][A]	u_test0/WR_CNT_7_s1/Q
0.386	0.002	tNET	RR	1	R5C5[1][A]	u_test0/n165_s2/I3
0.661	0.276	tINS	RF	1	R5C5[1][A]	u_test0/n165_s2/F
0.661	0.000	tNET	FF	1	R5C5[1][A]	u_test0/WR_CNT_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R5C5[1][A]	u_test0/WR_CNT_7_s1/CLK
0.137	0.000	tHld		1	R5C5[1][A]	u_test0/WR_CNT_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1
To	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/CLK
0.384	0.247	tC2Q	RR	3	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/Q
0.386	0.002	tNET	RR	1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n989_s3/I3
0.661	0.276	tINS	RF	1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n989_s3/F
0.661	0.000	tNET	FF	1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1/CLK
0.137	0.000	tHld		1	R18C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].times_reg_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1
To	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/CLK
0.384	0.247	tC2Q	RR	2	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/Q
0.386	0.002	tNET	RR	1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n2812_s2/I3
0.661	0.276	tINS	RF	1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n2812_s2/F
0.661	0.000	tNET	FF	1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1/CLK
0.137	0.000	tHld		1	R26C33[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1
To	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/CLK
0.384	0.247	tC2Q	RR	5	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/Q
0.386	0.002	tNET	RR	1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1750_s3/I3
0.661	0.276	tINS	RF	1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1750_s3/F
0.661	0.000	tNET	FF	1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1/CLK
0.137	0.000	tHld		1	R22C27[0][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1
To	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	3	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1748_s3/I3
0.661	0.276	tINS	RF	1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1748_s3/F
0.661	0.000	tNET	FF	1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1/CLK
0.137	0.000	tHld		1	R22C28[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/tRST_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1
To	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/CLK
0.384	0.247	tC2Q	RR	6	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/Q
0.386	0.002	tNET	RR	1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1713_s4/I1
0.661	0.276	tINS	RF	1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/n1713_s4/F
0.661	0.000	tNET	FF	1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2299	RIGHTSIDE[0]	u_PSRAM_TOP/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1/CLK
0.137	0.000	tHld		1	R18C32[1][A]	u_PSRAM_TOP/u_psram_top1/u_psram_init/waite_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/key_rst_r_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/key_rst_r_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/key_rst_r_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_19_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_17_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_13_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_5_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_6_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_14_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_7_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_8_s0/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_18_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2299	clk_x1	29.728	0.195
255	init_calib0	31.703	2.109
255	init_calib1	30.927	2.483
171	u_test1/burst_num1_9_4	31.250	1.990
171	u_test0/burst_num0_9_4	32.116	2.975
87	u_test1/wr_data_63_5	30.058	2.213
87	u_test0/wr_data_63_5	31.155	2.327
76	u_PSRAM_TOP/u_psram_top0/config_done_Z	35.647	2.309
76	u_PSRAM_TOP/u_psram_top1/config_done_Z	33.969	3.273
74	u_PSRAM_TOP/wr_data_d0_0_5	37.635	1.993

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C16	100.00%
R2C18	100.00%
R2C19	100.00%
R3C4	100.00%
R12C28	100.00%
R23C29	100.00%
R12C24	100.00%
R23C20	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name cl_osc -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name memory_clk -period 20 -waveform {0 10} [get_pins {your_instance_name/rpll_inst/CLKOUT}]
TC_CLOCK	Actived	create_clock -name memory_clk_p -period 20 -waveform {0 10} [get_pins {your_instance_name/rpll_inst/CLKOUTP}]
TC_CLOCK	Actived	create_clock -name clk_d -period 80 -waveform {0 40} [get_pins {your_instance_name/rpll_inst/CLKOUTD}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name user_clk -source [get_pins {your_instance_name/rpll_inst/CLKOUT}] -master_clock memory_clk -divide_by 2 [get_pins {u_PSRAM_TOP/clkdiv/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {cl_osc}] -group [get_clocks {memory_clk}] -group [get_clocks {user_clk}] -group [get_clocks {memory_clk_p}] -group [get_clocks {clk_d}]