Power Messages
| Report Title | Power Analysis Report |
| Design File | E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File | E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\a.cst |
| Timing Constraints File | E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\fpga_project.sdc |
| Tool Version | V1.9.11.02 (64-bit) |
| Part Number | GW1NR-LV9MG100PAC7/I6 |
| Device | GW1NR-9 |
| Device Version | C |
| Created Time | Wed May 28 13:47:58 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Configure Information:
| Grade | Commercial |
| Process | Typical |
| Ambient Temperature | 25.000 |
| Use Custom Theta JA | false |
| Heat Sink | None |
| Air Flow | LFM_0 |
| Use Custom Theta SA | false |
| Board Thermal Model | None |
| Use Custom Theta JB | false |
| Related Vcd File | |
| Related Saif File | |
| Filter Glitches | false |
| Default IO Toggle Rate | 0.125 |
| Default Remain Toggle Rate | 0.125 |
Power Summary
Power Information:
| Total Power (mW) | 22.478 |
| Quiescent Power (mW) | 14.436 |
| Dynamic Power (mW) | 8.042 |
| Psram Power (mW) | 172.000 |
Thermal Information:
| Junction Temperature | 26.082 |
| Theta JA | 49.205 |
| Max Allowed Ambient Temperature | 83.918 |
Supply Information:
| Voltage Source | Voltage | Dynamic Current(mA) | Quiescent Current(mA) | Power(mW) |
|---|---|---|---|---|
| VCC | 1.200 | 5.264 | 2.613 | 9.452 |
| VCCX | 3.300 | 0.339 | 3.200 | 11.678 |
| VCCIO18 | 1.800 | 0.337 | 0.411 | 1.348 |
Power Details
Power By Block Type:
| Block Type | Total Power(mW) | Static Power(mW) | Average Toggle Rate(millions of transitions/sec) |
|---|---|---|---|
| Logic | 0.438 | NA | 3.135 |
| IO | 4.793 | 2.610 | 6.676 |
| BSRAM | 4.248 | NA | NA |
| PLL | 1.163 | NA | NA |
Power By Hierarchy:
| Hierarchy Entity | Total Power(mW) | Block Dynamic Power(mW) |
|---|---|---|
| syn_top | 5.849 | 5.849(5.849) |
| syn_top/u_PSRAM_TOP/ | 4.481 | 4.481(4.481) |
| syn_top/u_PSRAM_TOP/u_psram_sync/ | 0.003 | 0.003(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top0/ | 2.239 | 2.239(2.214) |
| syn_top/u_PSRAM_TOP/u_psram_top0/matched_rvld[0].u_matched_rvld_fifo/ | 1.063 | 1.063(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top0/matched_rvld[1].u_matched_rvld_fifo/ | 1.063 | 1.063(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_init/ | 0.054 | 0.054(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/ | 0.035 | 0.035(0.035) |
| syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/ | 0.021 | 0.021(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/ | 0.014 | 0.014(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top1/ | 2.239 | 2.239(2.215) |
| syn_top/u_PSRAM_TOP/u_psram_top1/matched_rvld[0].u_matched_rvld_fifo/ | 1.063 | 1.063(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top1/matched_rvld[1].u_matched_rvld_fifo/ | 1.063 | 1.063(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_init/ | 0.054 | 0.054(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/ | 0.035 | 0.035(0.035) |
| syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/ | 0.021 | 0.021(0.000) |
| syn_top/u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/ | 0.014 | 0.014(0.000) |
| syn_top/u_reset_key/ | 0.022 | 0.022(0.000) |
| syn_top/u_test0/ | 0.091 | 0.091(0.000) |
| syn_top/u_test1/ | 0.092 | 0.092(0.000) |
| syn_top/your_instance_name/ | 1.163 | 1.163(0.000) |
Power By Clock Domain:
| Clock Domain | Clock Frequency(Mhz) | Total Dynamic Power(mW) |
|---|---|---|
| cl_osc | 50.000 | 1.186 |
| clk_d | 12.500 | 0.003 |
| user_clk | 25.000 | 4.663 |
| memory_clk | 50.000 | 0.004 |
| memory_clk_p | 50.000 | 0.004 |