Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\apsram_syn_top.v
E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\apsram_test.v
E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\gowin_rpll\gowin_rpll.v
E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\key_debounce.v
E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_2_channel\project\fpga_project\src\uhs_psram_memory_interface\uhs_psram_memory_interface.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9
Device Version C
Created Time Wed May 28 13:47:46 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module syn_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.642s, Peak memory usage = 231.480MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 231.480MB
    Optimizing Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.112s, Peak memory usage = 231.480MB
    Optimizing Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.151s, Peak memory usage = 231.480MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 231.480MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 231.480MB
    Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 231.480MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 231.480MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 231.480MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.063s, Peak memory usage = 231.480MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 231.480MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 253.266MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.355s, Peak memory usage = 253.266MB
Generate output files:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.316s, Peak memory usage = 260.816MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 5s, Peak memory usage = 260.816MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 4
Embedded Port 52
I/O Buf 52
    IBUF 2
    OBUF 6
    TBUF 4
    IOBUF 36
    ELVDS_OBUF 4
Register 2229
    DFF 3
    DFFE 1
    DFFR 20
    DFFP 12
    DFFPE 16
    DFFC 1105
    DFFCE 1072
LUT 3311
    LUT2 769
    LUT3 901
    LUT4 1641
ALU 323
    ALU 323
SSRAM 36
    RAM16S4 36
INV 33
    INV 33
IOLOGIC 112
    IDES4 32
    OSER4 48
    IODELAY 32
BSRAM 4
    SDPB 4
CLOCK 4
    CLKDIV 1
    DHCEN 2
    rPLL 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3883(3344 LUT, 323 ALU, 36 RAM16) / 8640 45%
Register 2229 / 6900 33%
  --Register as Latch 0 / 6900 0%
  --Register as FF 2229 / 6900 33%
BSRAM 4 / 26 16%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 your_instance_name/rpll_inst/CLKOUT.default_gen_clk Generated 20.000 50.000 0.000 10.000 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUT
3 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 20.000 50.000 5.000 15.000 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
4 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk Generated 80.000 12.500 0.000 40.000 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD
5 your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 60.000 16.667 0.000 30.000 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3
6 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk Generated 40.000 25.000 0.000 20.000 your_instance_name/rpll_inst/CLKOUT your_instance_name/rpll_inst/CLKOUT.default_gen_clk u_PSRAM_TOP/clkdiv/CLKOUT

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 184.068(MHz) 4 TOP
2 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk 12.500(MHz) 114.016(MHz) 6 TOP
3 u_PSRAM_TOP/clkdiv/CLKOUT.default_gen_clk 25.000(MHz) 111.408(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 8.948
Data Arrival Time 2.403
Data Required Time 11.350
From u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0
To u_PSRAM_TOP/u_dhcen_clk_x2
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
0.814 0.814 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.352 0.538 tNET RR 1 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK
1.691 0.340 tC2Q RF 8 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q
2.403 0.711 tNET FF 1 u_PSRAM_TOP/u_dhcen_clk_x2/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 your_instance_name/rpll_inst/CLKOUT.default_gen_clk
10.857 0.857 tCL FF 1 your_instance_name/rpll_inst/CLKOUT
11.568 0.711 tNET FF 3 u_PSRAM_TOP/u_dhcen_clk_x2/CLKIN
11.538 -0.030 tUnc u_PSRAM_TOP/u_dhcen_clk_x2
11.350 -0.188 tSu 1 u_PSRAM_TOP/u_dhcen_clk_x2
Path Statistics:
Clock Skew: 0.216
Setup Relationship: 10.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 13.920
Data Arrival Time 2.403
Data Required Time 16.322
From u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0
To u_PSRAM_TOP/u_dhcen_clk_x2p
Launch Clk your_instance_name/rpll_inst/CLKOUTD.default_gen_clk[F]
Latch Clk your_instance_name/rpll_inst/CLKOUTP.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 your_instance_name/rpll_inst/CLKOUTD.default_gen_clk
0.814 0.814 tCL RR 31 your_instance_name/rpll_inst/CLKOUTD
1.352 0.538 tNET RR 1 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK
1.691 0.340 tC2Q RF 8 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q
2.403 0.711 tNET FF 1 u_PSRAM_TOP/u_dhcen_clk_x2p/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
15.000 0.000 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk
15.829 0.829 tCL FF 1 your_instance_name/rpll_inst/CLKOUTP
16.540 0.711 tNET FF 3 u_PSRAM_TOP/u_dhcen_clk_x2p/CLKIN
16.510 -0.030 tUnc u_PSRAM_TOP/u_dhcen_clk_x2p
16.322 -0.188 tSu 1 u_PSRAM_TOP/u_dhcen_clk_x2p
Path Statistics:
Clock Skew: 0.189
Setup Relationship: 15.000
Logic Level: 1
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 0.000, 0.000%; route: 0.711, 67.685%; tC2Q: 0.340, 32.315%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 14.567
Data Arrival Time 5.939
Data Required Time 20.506
From u_reset_key/cnt_13_s0
To u_reset_key/key_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 24 clk_ibuf/O
0.538 0.538 tNET RR 1 u_reset_key/cnt_13_s0/CLK
0.878 0.340 tC2Q RF 2 u_reset_key/cnt_13_s0/Q
1.589 0.711 tNET FF 1 u_reset_key/n96_s4/I1
2.403 0.814 tINS FF 1 u_reset_key/n96_s4/F
3.115 0.711 tNET FF 1 u_reset_key/n96_s1/I1
3.929 0.814 tINS FF 1 u_reset_key/n96_s1/F
4.640 0.711 tNET FF 1 u_reset_key/n96_s0/I0
5.401 0.760 tINS FR 1 u_reset_key/n96_s0/F
5.939 0.538 tNET RR 1 u_reset_key/key_1_s0/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 24 clk_ibuf/O
20.538 0.538 tNET RR 1 u_reset_key/key_1_s0/CLK
20.506 -0.032 tSu 1 u_reset_key/key_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 2.389, 44.235%; route: 2.672, 49.476%; tC2Q: 0.340, 6.289%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 16.032
Data Arrival Time 4.210
Data Required Time 20.242
From u_reset_key/cnt_0_s0
To u_reset_key/cnt_19_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 24 clk_ibuf/O
0.538 0.538 tNET RR 1 u_reset_key/cnt_0_s0/CLK
0.878 0.340 tC2Q RF 3 u_reset_key/cnt_0_s0/Q
1.589 0.711 tNET FF 2 u_reset_key/n35_s/I1
2.363 0.774 tINS FF 1 u_reset_key/n35_s/COUT
2.363 0.000 tNET FF 2 u_reset_key/n34_s/CIN
2.406 0.042 tINS FF 1 u_reset_key/n34_s/COUT
2.406 0.000 tNET FF 2 u_reset_key/n33_s/CIN
2.448 0.042 tINS FF 1 u_reset_key/n33_s/COUT
2.448 0.000 tNET FF 2 u_reset_key/n32_s/CIN
2.490 0.042 tINS FF 1 u_reset_key/n32_s/COUT
2.490 0.000 tNET FF 2 u_reset_key/n31_s/CIN
2.532 0.042 tINS FF 1 u_reset_key/n31_s/COUT
2.532 0.000 tNET FF 2 u_reset_key/n30_s/CIN
2.574 0.042 tINS FF 1 u_reset_key/n30_s/COUT
2.574 0.000 tNET FF 2 u_reset_key/n29_s/CIN
2.617 0.042 tINS FF 1 u_reset_key/n29_s/COUT
2.617 0.000 tNET FF 2 u_reset_key/n28_s/CIN
2.659 0.042 tINS FF 1 u_reset_key/n28_s/COUT
2.659 0.000 tNET FF 2 u_reset_key/n27_s/CIN
2.701 0.042 tINS FF 1 u_reset_key/n27_s/COUT
2.701 0.000 tNET FF 2 u_reset_key/n26_s/CIN
2.743 0.042 tINS FF 1 u_reset_key/n26_s/COUT
2.743 0.000 tNET FF 2 u_reset_key/n25_s/CIN
2.786 0.042 tINS FF 1 u_reset_key/n25_s/COUT
2.786 0.000 tNET FF 2 u_reset_key/n24_s/CIN
2.828 0.042 tINS FF 1 u_reset_key/n24_s/COUT
2.828 0.000 tNET FF 2 u_reset_key/n23_s/CIN
2.870 0.042 tINS FF 1 u_reset_key/n23_s/COUT
2.870 0.000 tNET FF 2 u_reset_key/n22_s/CIN
2.912 0.042 tINS FF 1 u_reset_key/n22_s/COUT
2.912 0.000 tNET FF 2 u_reset_key/n21_s/CIN
2.955 0.042 tINS FF 1 u_reset_key/n21_s/COUT
2.955 0.000 tNET FF 2 u_reset_key/n20_s/CIN
2.997 0.042 tINS FF 1 u_reset_key/n20_s/COUT
2.997 0.000 tNET FF 2 u_reset_key/n19_s/CIN
3.039 0.042 tINS FF 1 u_reset_key/n19_s/COUT
3.039 0.000 tNET FF 2 u_reset_key/n18_s/CIN
3.081 0.042 tINS FF 1 u_reset_key/n18_s/COUT
3.081 0.000 tNET FF 2 u_reset_key/n17_s/CIN
3.499 0.417 tINS FF 1 u_reset_key/n17_s/SUM
4.210 0.711 tNET FF 1 u_reset_key/cnt_19_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 24 clk_ibuf/O
20.538 0.538 tNET RR 1 u_reset_key/cnt_19_s0/CLK
20.242 -0.296 tSu 1 u_reset_key/cnt_19_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 1.910, 52.005%; route: 1.423, 38.746%; tC2Q: 0.340, 9.249%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 16.074
Data Arrival Time 4.168
Data Required Time 20.242
From u_reset_key/cnt_0_s0
To u_reset_key/cnt_18_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 24 clk_ibuf/O
0.538 0.538 tNET RR 1 u_reset_key/cnt_0_s0/CLK
0.878 0.340 tC2Q RF 3 u_reset_key/cnt_0_s0/Q
1.589 0.711 tNET FF 2 u_reset_key/n35_s/I1
2.363 0.774 tINS FF 1 u_reset_key/n35_s/COUT
2.363 0.000 tNET FF 2 u_reset_key/n34_s/CIN
2.406 0.042 tINS FF 1 u_reset_key/n34_s/COUT
2.406 0.000 tNET FF 2 u_reset_key/n33_s/CIN
2.448 0.042 tINS FF 1 u_reset_key/n33_s/COUT
2.448 0.000 tNET FF 2 u_reset_key/n32_s/CIN
2.490 0.042 tINS FF 1 u_reset_key/n32_s/COUT
2.490 0.000 tNET FF 2 u_reset_key/n31_s/CIN
2.532 0.042 tINS FF 1 u_reset_key/n31_s/COUT
2.532 0.000 tNET FF 2 u_reset_key/n30_s/CIN
2.574 0.042 tINS FF 1 u_reset_key/n30_s/COUT
2.574 0.000 tNET FF 2 u_reset_key/n29_s/CIN
2.617 0.042 tINS FF 1 u_reset_key/n29_s/COUT
2.617 0.000 tNET FF 2 u_reset_key/n28_s/CIN
2.659 0.042 tINS FF 1 u_reset_key/n28_s/COUT
2.659 0.000 tNET FF 2 u_reset_key/n27_s/CIN
2.701 0.042 tINS FF 1 u_reset_key/n27_s/COUT
2.701 0.000 tNET FF 2 u_reset_key/n26_s/CIN
2.743 0.042 tINS FF 1 u_reset_key/n26_s/COUT
2.743 0.000 tNET FF 2 u_reset_key/n25_s/CIN
2.786 0.042 tINS FF 1 u_reset_key/n25_s/COUT
2.786 0.000 tNET FF 2 u_reset_key/n24_s/CIN
2.828 0.042 tINS FF 1 u_reset_key/n24_s/COUT
2.828 0.000 tNET FF 2 u_reset_key/n23_s/CIN
2.870 0.042 tINS FF 1 u_reset_key/n23_s/COUT
2.870 0.000 tNET FF 2 u_reset_key/n22_s/CIN
2.912 0.042 tINS FF 1 u_reset_key/n22_s/COUT
2.912 0.000 tNET FF 2 u_reset_key/n21_s/CIN
2.955 0.042 tINS FF 1 u_reset_key/n21_s/COUT
2.955 0.000 tNET FF 2 u_reset_key/n20_s/CIN
2.997 0.042 tINS FF 1 u_reset_key/n20_s/COUT
2.997 0.000 tNET FF 2 u_reset_key/n19_s/CIN
3.039 0.042 tINS FF 1 u_reset_key/n19_s/COUT
3.039 0.000 tNET FF 2 u_reset_key/n18_s/CIN
3.456 0.417 tINS FF 1 u_reset_key/n18_s/SUM
4.168 0.711 tNET FF 1 u_reset_key/cnt_18_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 24 clk_ibuf/O
20.538 0.538 tNET RR 1 u_reset_key/cnt_18_s0/CLK
20.242 -0.296 tSu 1 u_reset_key/cnt_18_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 1.867, 51.446%; route: 1.423, 39.197%; tC2Q: 0.340, 9.357%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%