#--  Synopsys, Inc.
#--  Version Q-2020.03G-Beta1
#--  Project file D:\GOWIN_refdesign\apsram32M_refdesign\project\fpga_project\impl\synthesize\rev_1\run_options.txt
#--  Written on Mon Feb  8 10:16:19 2021


#project files
add_file -verilog "D:/GOWIN_refdesign/apsram32M_refdesign/project/fpga_project/src/APSRAM_TOP.v"
add_file -verilog "D:/GOWIN_refdesign/apsram32M_refdesign/project/fpga_project/src/apsram_core.v"


#implementation: "rev_1"
impl -add rev_1 -type fpga
set_option -library_path {E:/gwide/47874/Gowin/Gowin_V1.9.7.02Beta1/IDE/data/hardware_core/gw2a/prim_syn.v}

#device options
set_option -technology GOWIN-GW2A
set_option -part GW2A_18
set_option -package PBGA484
set_option -speed_grade -7
set_option -part_companion ""

#compilation/mapping options

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# GOWIN-GW2A
set_option -maxfan 10000
set_option -rw_check_on_ram 1
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -run_prop_extract 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/fpga_project.vm"
impl -active "rev_1"
