Timing Messages

Report Title	Timing Analysis Report
Design File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_1_channel\project\fpga_project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_1_channel\project\fpga_project\src\a.cst
Timing Constraint File	E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_1_channel\project\fpga_project\src\fpga_project.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW1NR-LV9MG100PAC7/I6
Device	GW1NR-9
Device Version	C
Created Time	Wed May 28 13:46:44 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 1.14V 85C C7/I6
Hold Delay Model	Fast 1.26V 0C C7/I6
Numbers of Paths Analyzed	10268
Numbers of Endpoints Analyzed	5951
Numbers of Falling Endpoints	0
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	cl_osc	Base	20.000	50.000	0.000	10.000			clk
2	memory_clk	Base	20.000	50.000	0.000	10.000			u_pll/rpll_inst/CLKOUT
3	memory_clk_p	Base	20.000	50.000	1.563	10.000			u_pll/rpll_inst/CLKOUTP
4	clk_d	Base	80.000	12.500	0.000	40.000			u_pll/rpll_inst/CLKOUTD
5	user_clk	Generated	40.000	25.000	0.000	20.000	u_pll/rpll_inst/CLKOUT	memory_clk	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
6	u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Generated	60.000	16.667	0.000	30.000	clk_ibuf/I	cl_osc	u_pll/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	cl_osc	50.000(MHz)	256.490(MHz)	4	TOP
2	clk_d	12.500(MHz)	130.470(MHz)	6	TOP
3	user_clk	25.000(MHz)	82.476(MHz)	8	TOP

No timing paths to get frequency of memory_clk!

No timing paths to get frequency of memory_clk_p!

No timing paths to get frequency of u_pll/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
cl_osc	Setup	0.000	0
cl_osc	Hold	0.000	0
memory_clk	Setup	0.000	0
memory_clk	Hold	0.000	0
memory_clk_p	Setup	0.000	0
memory_clk_p	Hold	0.000	0
clk_d	Setup	0.000	0
clk_d	Hold	0.000	0
user_clk	Setup	0.000	0
user_clk	Hold	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
u_pll/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	16.101	u_reset_key/cnt_0_s0/Q	u_reset_key/key_1_s0/CE	cl_osc:[R]	cl_osc:[R]	20.000	3.867
2	17.220	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_19_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.484
3	17.262	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_18_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.442
4	17.304	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_17_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.399
5	17.347	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_16_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.357
6	17.389	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_15_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.315
7	17.431	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_14_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.273
8	17.473	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_13_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.230
9	17.515	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_12_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.188
10	17.558	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_11_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.146
11	17.600	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_10_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.104
12	17.642	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_9_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.061
13	17.684	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_8_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	2.019
14	17.727	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_7_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	1.977
15	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_12_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
16	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_13_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
17	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_14_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
18	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_15_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
19	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_16_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
20	17.728	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_17_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.240
21	17.735	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_18_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.233
22	17.735	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_19_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.233
23	17.761	u_reset_key/key_rst_r_s0/Q	u_reset_key/cnt_0_s0/RESET	cl_osc:[R]	cl_osc:[R]	20.000	2.207
24	17.769	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_6_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	1.935
25	17.811	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_5_s0/D	cl_osc:[R]	cl_osc:[R]	20.000	1.892

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.524	u_reset_key/cnt_0_s0/Q	u_reset_key/cnt_0_s0/D	cl_osc:[R]	cl_osc:[R]	0.524
2	0.524	u_test/check_data_27_s1/Q	u_test/check_data_27_s1/D	user_clk:[R]	user_clk:[R]	0.524
3	0.524	u_test/check_data_34_s1/Q	u_test/check_data_34_s1/D	user_clk:[R]	user_clk:[R]	0.524
4	0.524	u_test/check_data_105_s1/Q	u_test/check_data_105_s1/D	user_clk:[R]	user_clk:[R]	0.524
5	0.524	u_test/cyc_cnt_5_s1/Q	u_test/cyc_cnt_5_s1/D	user_clk:[R]	user_clk:[R]	0.524
6	0.524	u_test/cyc_cnt_9_s1/Q	u_test/cyc_cnt_9_s1/D	user_clk:[R]	user_clk:[R]	0.524
7	0.524	u_test/wr_data_add_44_s1/Q	u_test/wr_data_add_44_s1/D	user_clk:[R]	user_clk:[R]	0.524
8	0.524	u_test/wr_data_add_71_s1/Q	u_test/wr_data_add_71_s1/D	user_clk:[R]	user_clk:[R]	0.524
9	0.524	u_test/wr_data_add_121_s1/Q	u_test/wr_data_add_121_s1/D	user_clk:[R]	user_clk:[R]	0.524
10	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/D	clk_d:[R]	clk_d:[R]	0.524
11	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/D	clk_d:[R]	clk_d:[R]	0.524
12	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/D	user_clk:[R]	user_clk:[R]	0.524
13	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/D	user_clk:[R]	user_clk:[R]	0.524
14	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D	user_clk:[R]	user_clk:[R]	0.524
15	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/D	user_clk:[R]	user_clk:[R]	0.524
16	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/D	user_clk:[R]	user_clk:[R]	0.524
17	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/D	user_clk:[R]	user_clk:[R]	0.524
18	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/D	user_clk:[R]	user_clk:[R]	0.524
19	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/D	user_clk:[R]	user_clk:[R]	0.524
20	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/D	user_clk:[R]	user_clk:[R]	0.524
21	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/D	user_clk:[R]	user_clk:[R]	0.524
22	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/D	user_clk:[R]	user_clk:[R]	0.524
23	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/D	user_clk:[R]	user_clk:[R]	0.524
24	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/D	user_clk:[R]	user_clk:[R]	0.524
25	0.524	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/Q	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/D	user_clk:[R]	user_clk:[R]	0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
2	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/d_clr_flag_s6/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
3	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/cyc_cnt_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
4	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/burst_rnum_0_s3/PRESET	user_clk:[R]	user_clk:[R]	40.000	2.411
5	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
6	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_1_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
7	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_4_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
8	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_7_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
9	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_8_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
10	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
11	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_1_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
12	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_4_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
13	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_7_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
14	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_8_s3/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
15	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_1_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
16	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_2_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
17	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_3_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
18	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_4_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
19	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_5_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
20	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_6_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
21	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_7_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
22	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_8_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
23	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_9_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
24	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_10_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411
25	37.557	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_11_s1/CLEAR	user_clk:[R]	user_clk:[R]	40.000	2.411

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
2	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/d_clr_flag_s6/CLEAR	user_clk:[R]	user_clk:[R]	1.389
3	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/cyc_cnt_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
4	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/burst_rnum_0_s3/PRESET	user_clk:[R]	user_clk:[R]	1.389
5	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
6	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_1_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
7	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_4_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
8	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_7_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
9	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/RD_CNT_8_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
10	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_0_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
11	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_1_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
12	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_4_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
13	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_7_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
14	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/WR_CNT_8_s3/CLEAR	user_clk:[R]	user_clk:[R]	1.389
15	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_1_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
16	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_2_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
17	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_3_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
18	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_4_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
19	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_5_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
20	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_6_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
21	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_7_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
22	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_8_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
23	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_9_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
24	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_10_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389
25	1.379	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q	u_test/check_data_11_s1/CLEAR	user_clk:[R]	user_clk:[R]	1.389

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/key_rst_r_s0
2	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_19_s0
3	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_17_s0
4	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_13_s0
5	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_5_s0
6	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_6_s0
7	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_14_s0
8	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_7_s0
9	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_8_s0
10	6.948	7.874	0.926	High Pulse Width	cl_osc	u_reset_key/cnt_18_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	16.101
Data Arrival Time	8.277
Data Required Time	24.378
From	u_reset_key/cnt_0_s0
To	u_reset_key/key_1_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	1	R24C14[3][B]	u_reset_key/n96_s3/I0
5.946	0.594	tINS	FR	1	R24C14[3][B]	u_reset_key/n96_s3/F
6.256	0.310	tNET	RR	1	R24C15[3][A]	u_reset_key/n96_s1/I0
7.071	0.814	tINS	RF	1	R24C15[3][A]	u_reset_key/n96_s1/F
7.434	0.363	tNET	FF	1	R24C13[0][A]	u_reset_key/n96_s0/I0
8.028	0.594	tINS	FR	1	R24C13[0][A]	u_reset_key/n96_s0/F
8.277	0.249	tNET	RR	1	R24C13[0][B]	u_reset_key/key_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C13[0][B]	u_reset_key/key_1_s0/CLK
24.378	-0.032	tSu		1	R24C13[0][B]	u_reset_key/key_1_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 2.003, 51.800%; route: 1.524, 39.417%; tC2Q: 0.340, 8.783%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path2

Path Summary:

Slack	17.220
Data Arrival Time	6.894
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_19_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C16[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C16[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C16[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C16[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C16[2][B]	u_reset_key/n19_s/CIN
6.435	0.042	tINS	FF	1	R24C16[2][B]	u_reset_key/n19_s/COUT
6.435	0.000	tNET	FF	2	R24C17[0][A]	u_reset_key/n18_s/CIN
6.477	0.042	tINS	FF	1	R24C17[0][A]	u_reset_key/n18_s/COUT
6.477	0.000	tNET	FF	2	R24C17[0][B]	u_reset_key/n17_s/CIN
6.894	0.417	tINS	FF	1	R24C17[0][B]	u_reset_key/n17_s/SUM
6.894	0.000	tNET	FF	1	R24C17[0][B]	u_reset_key/cnt_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C17[0][B]	u_reset_key/cnt_19_s0/CLK
24.114	-0.296	tSu		1	R24C17[0][B]	u_reset_key/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.543, 62.113%; route: 0.601, 24.213%; tC2Q: 0.340, 13.674%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path3

Path Summary:

Slack	17.262
Data Arrival Time	6.852
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_18_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C16[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C16[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C16[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C16[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C16[2][B]	u_reset_key/n19_s/CIN
6.435	0.042	tINS	FF	1	R24C16[2][B]	u_reset_key/n19_s/COUT
6.435	0.000	tNET	FF	2	R24C17[0][A]	u_reset_key/n18_s/CIN
6.852	0.417	tINS	FF	1	R24C17[0][A]	u_reset_key/n18_s/SUM
6.852	0.000	tNET	FF	1	R24C17[0][A]	u_reset_key/cnt_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C17[0][A]	u_reset_key/cnt_18_s0/CLK
24.114	-0.296	tSu		1	R24C17[0][A]	u_reset_key/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	5
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.501, 61.458%; route: 0.601, 24.632%; tC2Q: 0.340, 13.910%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path4

Path Summary:

Slack	17.304
Data Arrival Time	6.810
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_17_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C16[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C16[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C16[2][A]	u_reset_key/n20_s/CIN
6.393	0.042	tINS	FF	1	R24C16[2][A]	u_reset_key/n20_s/COUT
6.393	0.000	tNET	FF	2	R24C16[2][B]	u_reset_key/n19_s/CIN
6.810	0.417	tINS	FF	1	R24C16[2][B]	u_reset_key/n19_s/SUM
6.810	0.000	tNET	FF	1	R24C16[2][B]	u_reset_key/cnt_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[2][B]	u_reset_key/cnt_17_s0/CLK
24.114	-0.296	tSu		1	R24C16[2][B]	u_reset_key/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.458, 60.779%; route: 0.601, 25.066%; tC2Q: 0.340, 14.155%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path5

Path Summary:

Slack	17.347
Data Arrival Time	6.768
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_16_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C16[1][B]	u_reset_key/n21_s/CIN
6.351	0.042	tINS	FF	1	R24C16[1][B]	u_reset_key/n21_s/COUT
6.351	0.000	tNET	FF	2	R24C16[2][A]	u_reset_key/n20_s/CIN
6.768	0.417	tINS	FF	1	R24C16[2][A]	u_reset_key/n20_s/SUM
6.768	0.000	tNET	FF	1	R24C16[2][A]	u_reset_key/cnt_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[2][A]	u_reset_key/cnt_16_s0/CLK
24.114	-0.296	tSu		1	R24C16[2][A]	u_reset_key/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.416, 60.076%; route: 0.601, 25.515%; tC2Q: 0.340, 14.409%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path6

Path Summary:

Slack	17.389
Data Arrival Time	6.725
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_15_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.308	0.042	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/COUT
6.308	0.000	tNET	FF	2	R24C16[1][B]	u_reset_key/n21_s/CIN
6.725	0.417	tINS	FF	1	R24C16[1][B]	u_reset_key/n21_s/SUM
6.725	0.000	tNET	FF	1	R24C16[1][B]	u_reset_key/cnt_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[1][B]	u_reset_key/cnt_15_s0/CLK
24.114	-0.296	tSu		1	R24C16[1][B]	u_reset_key/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.374, 59.348%; route: 0.601, 25.981%; tC2Q: 0.340, 14.672%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path7

Path Summary:

Slack	17.431
Data Arrival Time	6.683
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_14_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.266	0.042	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/COUT
6.266	0.000	tNET	FF	2	R24C16[1][A]	u_reset_key/n22_s/CIN
6.683	0.417	tINS	FF	1	R24C16[1][A]	u_reset_key/n22_s/SUM
6.683	0.000	tNET	FF	1	R24C16[1][A]	u_reset_key/cnt_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[1][A]	u_reset_key/cnt_14_s0/CLK
24.114	-0.296	tSu		1	R24C16[1][A]	u_reset_key/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.332, 58.592%; route: 0.601, 26.463%; tC2Q: 0.340, 14.944%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path8

Path Summary:

Slack	17.473
Data Arrival Time	6.641
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_13_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.224	0.042	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/COUT
6.224	0.000	tNET	FF	2	R24C16[0][B]	u_reset_key/n23_s/CIN
6.641	0.417	tINS	FF	1	R24C16[0][B]	u_reset_key/n23_s/SUM
6.641	0.000	tNET	FF	1	R24C16[0][B]	u_reset_key/cnt_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[0][B]	u_reset_key/cnt_13_s0/CLK
24.114	-0.296	tSu		1	R24C16[0][B]	u_reset_key/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.289, 57.808%; route: 0.601, 26.965%; tC2Q: 0.340, 15.227%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path9

Path Summary:

Slack	17.515
Data Arrival Time	6.599
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_12_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.182	0.042	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/COUT
6.182	0.000	tNET	FF	2	R24C16[0][A]	u_reset_key/n24_s/CIN
6.599	0.417	tINS	FF	1	R24C16[0][A]	u_reset_key/n24_s/SUM
6.599	0.000	tNET	FF	1	R24C16[0][A]	u_reset_key/cnt_12_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[0][A]	u_reset_key/cnt_12_s0/CLK
24.114	-0.296	tSu		1	R24C16[0][A]	u_reset_key/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.247, 56.994%; route: 0.601, 27.485%; tC2Q: 0.340, 15.521%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path10

Path Summary:

Slack	17.558
Data Arrival Time	6.557
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_11_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.139	0.042	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/COUT
6.139	0.000	tNET	FF	2	R24C15[2][B]	u_reset_key/n25_s/CIN
6.557	0.417	tINS	FF	1	R24C15[2][B]	u_reset_key/n25_s/SUM
6.557	0.000	tNET	FF	1	R24C15[2][B]	u_reset_key/cnt_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[2][B]	u_reset_key/cnt_11_s0/CLK
24.114	-0.296	tSu		1	R24C15[2][B]	u_reset_key/cnt_11_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.205, 56.147%; route: 0.601, 28.026%; tC2Q: 0.340, 15.827%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path11

Path Summary:

Slack	17.600
Data Arrival Time	6.514
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_10_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.097	0.042	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/COUT
6.097	0.000	tNET	FF	2	R24C15[2][A]	u_reset_key/n26_s/CIN
6.514	0.417	tINS	FF	1	R24C15[2][A]	u_reset_key/n26_s/SUM
6.514	0.000	tNET	FF	1	R24C15[2][A]	u_reset_key/cnt_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[2][A]	u_reset_key/cnt_10_s0/CLK
24.114	-0.296	tSu		1	R24C15[2][A]	u_reset_key/cnt_10_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.163, 55.267%; route: 0.601, 28.589%; tC2Q: 0.340, 16.144%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path12

Path Summary:

Slack	17.642
Data Arrival Time	6.472
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_9_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.055	0.042	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/COUT
6.055	0.000	tNET	FF	2	R24C15[1][B]	u_reset_key/n27_s/CIN
6.472	0.417	tINS	FF	1	R24C15[1][B]	u_reset_key/n27_s/SUM
6.472	0.000	tNET	FF	1	R24C15[1][B]	u_reset_key/cnt_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[1][B]	u_reset_key/cnt_9_s0/CLK
24.114	-0.296	tSu		1	R24C15[1][B]	u_reset_key/cnt_9_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.120, 54.350%; route: 0.601, 29.174%; tC2Q: 0.340, 16.475%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path13

Path Summary:

Slack	17.684
Data Arrival Time	6.430
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_8_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.013	0.042	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/COUT
6.013	0.000	tNET	FF	2	R24C15[1][A]	u_reset_key/n28_s/CIN
6.430	0.417	tINS	FF	1	R24C15[1][A]	u_reset_key/n28_s/SUM
6.430	0.000	tNET	FF	1	R24C15[1][A]	u_reset_key/cnt_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[1][A]	u_reset_key/cnt_8_s0/CLK
24.114	-0.296	tSu		1	R24C15[1][A]	u_reset_key/cnt_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	4
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.078, 53.395%; route: 0.601, 29.785%; tC2Q: 0.340, 16.820%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path14

Path Summary:

Slack	17.727
Data Arrival Time	6.388
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_7_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
5.970	0.042	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/COUT
5.970	0.000	tNET	FF	2	R24C15[0][B]	u_reset_key/n29_s/CIN
6.388	0.417	tINS	FF	1	R24C15[0][B]	u_reset_key/n29_s/SUM
6.388	0.000	tNET	FF	1	R24C15[0][B]	u_reset_key/cnt_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[0][B]	u_reset_key/cnt_7_s0/CLK
24.114	-0.296	tSu		1	R24C15[0][B]	u_reset_key/cnt_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 1.036, 52.400%; route: 0.601, 30.421%; tC2Q: 0.340, 17.179%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path15

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_12_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[0][A]	u_reset_key/cnt_12_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[0][A]	u_reset_key/cnt_12_s0/CLK
24.378	-0.032	tSu		1	R24C16[0][A]	u_reset_key/cnt_12_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path16

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_13_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[0][B]	u_reset_key/cnt_13_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[0][B]	u_reset_key/cnt_13_s0/CLK
24.378	-0.032	tSu		1	R24C16[0][B]	u_reset_key/cnt_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path17

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_14_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[1][A]	u_reset_key/cnt_14_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[1][A]	u_reset_key/cnt_14_s0/CLK
24.378	-0.032	tSu		1	R24C16[1][A]	u_reset_key/cnt_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path18

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_15_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[1][B]	u_reset_key/cnt_15_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[1][B]	u_reset_key/cnt_15_s0/CLK
24.378	-0.032	tSu		1	R24C16[1][B]	u_reset_key/cnt_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path19

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_16_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[2][A]	u_reset_key/cnt_16_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[2][A]	u_reset_key/cnt_16_s0/CLK
24.378	-0.032	tSu		1	R24C16[2][A]	u_reset_key/cnt_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path20

Path Summary:

Slack	17.728
Data Arrival Time	6.650
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_17_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.650	0.865	tNET	RR	1	R24C16[2][B]	u_reset_key/cnt_17_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C16[2][B]	u_reset_key/cnt_17_s0/CLK
24.378	-0.032	tSu		1	R24C16[2][B]	u_reset_key/cnt_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.105%; route: 1.114, 49.730%; tC2Q: 0.340, 15.165%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path21

Path Summary:

Slack	17.735
Data Arrival Time	6.643
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_18_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.643	0.858	tNET	RR	1	R24C17[0][A]	u_reset_key/cnt_18_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C17[0][A]	u_reset_key/cnt_18_s0/CLK
24.378	-0.032	tSu		1	R24C17[0][A]	u_reset_key/cnt_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.212%; route: 1.107, 49.577%; tC2Q: 0.340, 15.211%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path22

Path Summary:

Slack	17.735
Data Arrival Time	6.643
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_19_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.643	0.858	tNET	RR	1	R24C17[0][B]	u_reset_key/cnt_19_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C17[0][B]	u_reset_key/cnt_19_s0/CLK
24.378	-0.032	tSu		1	R24C17[0][B]	u_reset_key/cnt_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.212%; route: 1.107, 49.577%; tC2Q: 0.340, 15.211%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path23

Path Summary:

Slack	17.761
Data Arrival Time	6.618
Data Required Time	24.378
From	u_reset_key/key_rst_r_s0
To	u_reset_key/cnt_0_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/CLK
4.750	0.340	tC2Q	RR	1	R25C13[1][A]	u_reset_key/key_rst_r_s0/Q
4.999	0.249	tNET	RR	1	R25C13[0][B]	u_reset_key/key_an_s0/I0
5.785	0.786	tINS	RR	20	R25C13[0][B]	u_reset_key/key_an_s0/F
6.618	0.832	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
24.378	-0.032	tSu		1	R25C13[0][A]	u_reset_key/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.786, 35.623%; route: 1.081, 48.988%; tC2Q: 0.340, 15.389%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path24

Path Summary:

Slack	17.769
Data Arrival Time	6.345
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_6_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
5.928	0.042	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/COUT
5.928	0.000	tNET	FF	2	R24C15[0][A]	u_reset_key/n30_s/CIN
6.345	0.417	tINS	FF	1	R24C15[0][A]	u_reset_key/n30_s/SUM
6.345	0.000	tNET	FF	1	R24C15[0][A]	u_reset_key/cnt_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C15[0][A]	u_reset_key/cnt_6_s0/CLK
24.114	-0.296	tSu		1	R24C15[0][A]	u_reset_key/cnt_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.994, 51.361%; route: 0.601, 31.085%; tC2Q: 0.340, 17.554%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Path25

Path Summary:

Slack	17.811
Data Arrival Time	6.303
Data Required Time	24.114
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_5_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
4.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
4.411	0.181	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
4.750	0.340	tC2Q	RF	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
5.352	0.601	tNET	FF	2	R24C14[0][B]	u_reset_key/n35_s/I1
5.759	0.408	tINS	FR	1	R24C14[0][B]	u_reset_key/n35_s/COUT
5.759	0.000	tNET	RR	2	R24C14[1][A]	u_reset_key/n34_s/CIN
5.801	0.042	tINS	RF	1	R24C14[1][A]	u_reset_key/n34_s/COUT
5.801	0.000	tNET	FF	2	R24C14[1][B]	u_reset_key/n33_s/CIN
5.844	0.042	tINS	FF	1	R24C14[1][B]	u_reset_key/n33_s/COUT
5.844	0.000	tNET	FF	2	R24C14[2][A]	u_reset_key/n32_s/CIN
5.886	0.042	tINS	FF	1	R24C14[2][A]	u_reset_key/n32_s/COUT
5.886	0.000	tNET	FF	2	R24C14[2][B]	u_reset_key/n31_s/CIN
6.303	0.417	tINS	FF	1	R24C14[2][B]	u_reset_key/n31_s/SUM
6.303	0.000	tNET	FF	1	R24C14[2][B]	u_reset_key/cnt_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					cl_osc
20.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
24.230	4.230	tINS	RR	24	IOT29[A]	clk_ibuf/O
24.411	0.181	tNET	RR	1	R24C14[2][B]	u_reset_key/cnt_5_s0/CLK
24.114	-0.296	tSu		1	R24C14[2][B]	u_reset_key/cnt_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	20.000
Logic Level	3
Arrival Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%
Arrival Data Path Delay	cell: 0.951, 50.275%; route: 0.601, 31.779%; tC2Q: 0.340, 17.946%
Required Clock Path Delay	cell: 4.230, 95.902%; route: 0.181, 4.098%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.524
Data Arrival Time	3.788
Data Required Time	3.263
From	u_reset_key/cnt_0_s0
To	u_reset_key/cnt_0_s0
Launch Clk	cl_osc:[R]
Latch Clk	cl_osc:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
3.126	3.126	tINS	RR	24	IOT29[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
3.510	0.247	tC2Q	RR	3	R25C13[0][A]	u_reset_key/cnt_0_s0/Q
3.512	0.002	tNET	RR	1	R25C13[0][A]	u_reset_key/n36_s2/I0
3.788	0.276	tINS	RF	1	R25C13[0][A]	u_reset_key/n36_s2/F
3.788	0.000	tNET	FF	1	R25C13[0][A]	u_reset_key/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					cl_osc
0.000	0.000	tCL	RR	1	IOT29[A]	clk_ibuf/I
3.126	3.126	tINS	RR	24	IOT29[A]	clk_ibuf/O
3.263	0.137	tNET	RR	1	R25C13[0][A]	u_reset_key/cnt_0_s0/CLK
3.263	0.000	tHld		1	R25C13[0][A]	u_reset_key/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 3.126, 95.808%; route: 0.137, 4.192%

Path2

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/check_data_27_s1
To	u_test/check_data_27_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C9[1][A]	u_test/check_data_27_s1/CLK
0.384	0.247	tC2Q	RR	3	R9C9[1][A]	u_test/check_data_27_s1/Q
0.386	0.002	tNET	RR	1	R9C9[1][A]	u_test/n2455_s2/I3
0.661	0.276	tINS	RF	1	R9C9[1][A]	u_test/n2455_s2/F
0.661	0.000	tNET	FF	1	R9C9[1][A]	u_test/check_data_27_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C9[1][A]	u_test/check_data_27_s1/CLK
0.137	0.000	tHld		1	R9C9[1][A]	u_test/check_data_27_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/check_data_34_s1
To	u_test/check_data_34_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R5C10[0][A]	u_test/check_data_34_s1/CLK
0.384	0.247	tC2Q	RR	4	R5C10[0][A]	u_test/check_data_34_s1/Q
0.386	0.002	tNET	RR	1	R5C10[0][A]	u_test/n2448_s2/I3
0.661	0.276	tINS	RF	1	R5C10[0][A]	u_test/n2448_s2/F
0.661	0.000	tNET	FF	1	R5C10[0][A]	u_test/check_data_34_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R5C10[0][A]	u_test/check_data_34_s1/CLK
0.137	0.000	tHld		1	R5C10[0][A]	u_test/check_data_34_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/check_data_105_s1
To	u_test/check_data_105_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C11[0][A]	u_test/check_data_105_s1/CLK
0.384	0.247	tC2Q	RR	4	R11C11[0][A]	u_test/check_data_105_s1/Q
0.386	0.002	tNET	RR	1	R11C11[0][A]	u_test/n2377_s2/I3
0.661	0.276	tINS	RF	1	R11C11[0][A]	u_test/n2377_s2/F
0.661	0.000	tNET	FF	1	R11C11[0][A]	u_test/check_data_105_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C11[0][A]	u_test/check_data_105_s1/CLK
0.137	0.000	tHld		1	R11C11[0][A]	u_test/check_data_105_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/cyc_cnt_5_s1
To	u_test/cyc_cnt_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C6[0][A]	u_test/cyc_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	4	R15C6[0][A]	u_test/cyc_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R15C6[0][A]	u_test/n2162_s2/I3
0.661	0.276	tINS	RF	1	R15C6[0][A]	u_test/n2162_s2/F
0.661	0.000	tNET	FF	1	R15C6[0][A]	u_test/cyc_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C6[0][A]	u_test/cyc_cnt_5_s1/CLK
0.137	0.000	tHld		1	R15C6[0][A]	u_test/cyc_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/cyc_cnt_9_s1
To	u_test/cyc_cnt_9_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C5[0][A]	u_test/cyc_cnt_9_s1/CLK
0.384	0.247	tC2Q	RR	2	R15C5[0][A]	u_test/cyc_cnt_9_s1/Q
0.386	0.002	tNET	RR	1	R15C5[0][A]	u_test/n2158_s2/I3
0.661	0.276	tINS	RF	1	R15C5[0][A]	u_test/n2158_s2/F
0.661	0.000	tNET	FF	1	R15C5[0][A]	u_test/cyc_cnt_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C5[0][A]	u_test/cyc_cnt_9_s1/CLK
0.137	0.000	tHld		1	R15C5[0][A]	u_test/cyc_cnt_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_44_s1
To	u_test/wr_data_add_44_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C7[1][A]	u_test/wr_data_add_44_s1/CLK
0.384	0.247	tC2Q	RR	5	R20C7[1][A]	u_test/wr_data_add_44_s1/Q
0.386	0.002	tNET	RR	1	R20C7[1][A]	u_test/n1012_s1/I2
0.661	0.276	tINS	RF	1	R20C7[1][A]	u_test/n1012_s1/F
0.661	0.000	tNET	FF	1	R20C7[1][A]	u_test/wr_data_add_44_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C7[1][A]	u_test/wr_data_add_44_s1/CLK
0.137	0.000	tHld		1	R20C7[1][A]	u_test/wr_data_add_44_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_71_s1
To	u_test/wr_data_add_71_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C10[1][A]	u_test/wr_data_add_71_s1/CLK
0.384	0.247	tC2Q	RR	3	R18C10[1][A]	u_test/wr_data_add_71_s1/Q
0.386	0.002	tNET	RR	1	R18C10[1][A]	u_test/n985_s1/I2
0.661	0.276	tINS	RF	1	R18C10[1][A]	u_test/n985_s1/F
0.661	0.000	tNET	FF	1	R18C10[1][A]	u_test/wr_data_add_71_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C10[1][A]	u_test/wr_data_add_71_s1/CLK
0.137	0.000	tHld		1	R18C10[1][A]	u_test/wr_data_add_71_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_test/wr_data_add_121_s1
To	u_test/wr_data_add_121_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R24C4[1][A]	u_test/wr_data_add_121_s1/CLK
0.384	0.247	tC2Q	RR	3	R24C4[1][A]	u_test/wr_data_add_121_s1/Q
0.386	0.002	tNET	RR	1	R24C4[1][A]	u_test/n935_s1/I2
0.661	0.276	tINS	RF	1	R24C4[1][A]	u_test/n935_s1/F
0.661	0.000	tNET	FF	1	R24C4[1][A]	u_test/wr_data_add_121_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R24C4[1][A]	u_test/wr_data_add_121_s1/CLK
0.137	0.000	tHld		1	R24C4[1][A]	u_test/wr_data_add_121_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/CLK
0.384	0.247	tC2Q	RR	5	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/Q
0.386	0.002	tNET	RR	1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n43_s3/I0
0.661	0.276	tINS	RF	1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n43_s3/F
0.661	0.000	tNET	FF	1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1/CLK
0.137	0.000	tHld		1	R6C35[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1
Launch Clk	clk_d:[R]
Latch Clk	clk_d:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK
0.384	0.247	tC2Q	RR	3	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/Q
0.386	0.002	tNET	RR	1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n38_s1/I2
0.661	0.276	tINS	RF	1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/n38_s1/F
0.661	0.000	tNET	FF	1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk_d
0.000	0.000	tCL	RR	31	PLL_R	u_pll/rpll_inst/CLKOUTD
0.137	0.137	tNET	RR	1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1/CLK
0.137	0.000	tHld		1	R5C36[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_sync/lock_cnt_13_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/CLK
0.384	0.247	tC2Q	RR	4	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/Q
0.386	0.002	tNET	RR	1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4524_s4/I3
0.661	0.276	tINS	RF	1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4524_s4/F
0.661	0.000	tNET	FF	1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3/CLK
0.137	0.000	tHld		1	R21C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/CLK
0.384	0.247	tC2Q	RR	2	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/Q
0.386	0.002	tNET	RR	1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4522_s2/I3
0.661	0.276	tINS	RF	1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4522_s2/F
0.661	0.000	tNET	FF	1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1/CLK
0.137	0.000	tHld		1	R20C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.384	0.247	tC2Q	RR	3	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/Q
0.386	0.002	tNET	RR	1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4520_s2/I3
0.661	0.276	tINS	RF	1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n4520_s2/F
0.661	0.000	tNET	FF	1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1/CLK
0.137	0.000	tHld		1	R21C19[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/timer_cnt1_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/CLK
0.384	0.247	tC2Q	RR	3	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/Q
0.386	0.002	tNET	RR	1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2880_s1/I3
0.661	0.276	tINS	RF	1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2880_s1/F
0.661	0.000	tNET	FF	1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1/CLK
0.137	0.000	tHld		1	R13C20[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tRST_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/CLK
0.384	0.247	tC2Q	RR	3	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/Q
0.386	0.002	tNET	RR	1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2802_s3/I1
0.661	0.276	tINS	RF	1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2802_s3/F
0.661	0.000	tNET	FF	1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1/CLK
0.137	0.000	tHld		1	R17C22[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/GRST_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/CLK
0.384	0.247	tC2Q	RR	3	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/Q
0.386	0.002	tNET	RR	1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2737_s2/I3
0.661	0.276	tINS	RF	1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2737_s2/F
0.661	0.000	tNET	FF	1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1/CLK
0.137	0.000	tHld		1	R18C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/CLK
0.384	0.247	tC2Q	RR	3	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/Q
0.386	0.002	tNET	RR	1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2734_s2/I3
0.661	0.276	tINS	RF	1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2734_s2/F
0.661	0.000	tNET	FF	1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1/CLK
0.137	0.000	tHld		1	R12C23[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/CLK
0.384	0.247	tC2Q	RR	3	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/Q
0.386	0.002	tNET	RR	1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2729_s2/I3
0.661	0.276	tINS	RF	1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2729_s2/F
0.661	0.000	tNET	FF	1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1/CLK
0.137	0.000	tHld		1	R11C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/CLK
0.384	0.247	tC2Q	RR	2	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/Q
0.386	0.002	tNET	RR	1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2725_s1/I3
0.661	0.276	tINS	RF	1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2725_s1/F
0.661	0.000	tNET	FF	1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1/CLK
0.137	0.000	tHld		1	R12C23[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/tvcs_cnt_15_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	2	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2008_s2/I3
0.661	0.276	tINS	RF	1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n2008_s2/F
0.661	0.000	tNET	FF	1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1/CLK
0.137	0.000	tHld		1	R12C25[1][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[3].check_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/CLK
0.384	0.247	tC2Q	RR	2	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/Q
0.386	0.002	tNET	RR	1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n1202_s2/I3
0.661	0.276	tINS	RF	1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n1202_s2/F
0.661	0.000	tNET	FF	1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1/CLK
0.137	0.000	tHld		1	R23C27[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/CLK
0.384	0.247	tC2Q	RR	4	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/Q
0.386	0.002	tNET	RR	1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n1201_s2/I1
0.661	0.276	tINS	RF	1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n1201_s2/F
0.661	0.000	tNET	FF	1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1/CLK
0.137	0.000	tHld		1	R24C28[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[2].read_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/CLK
0.384	0.247	tC2Q	RR	3	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/Q
0.386	0.002	tNET	RR	1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n877_s2/I1
0.661	0.276	tINS	RF	1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n877_s2/F
0.661	0.000	tNET	FF	1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1/CLK
0.137	0.000	tHld		1	R16C24[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[1].check_cnt_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	0.524
Data Arrival Time	0.661
Data Required Time	0.137
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1
To	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/CLK
0.384	0.247	tC2Q	RR	2	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/Q
0.386	0.002	tNET	RR	1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n310_s2/I3
0.661	0.276	tINS	RF	1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/n310_s2/F
0.661	0.000	tNET	FF	1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1/CLK
0.137	0.000	tHld		1	R7C21[0][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/read_calibration[0].check_cnt_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C7[2][A]	u_test/check_data_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C7[2][A]	u_test/check_data_0_s3/CLK
40.149	-0.032	tSu		1	R9C7[2][A]	u_test/check_data_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path2

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/d_clr_flag_s6
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C6[0][A]	u_test/d_clr_flag_s6/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C6[0][A]	u_test/d_clr_flag_s6/CLK
40.149	-0.032	tSu		1	R9C6[0][A]	u_test/d_clr_flag_s6

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/cyc_cnt_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R16C4[0][A]	u_test/cyc_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R16C4[0][A]	u_test/cyc_cnt_0_s3/CLK
40.149	-0.032	tSu		1	R16C4[0][A]	u_test/cyc_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/burst_rnum_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R16C4[0][B]	u_test/burst_rnum_0_s3/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R16C4[0][B]	u_test/burst_rnum_0_s3/CLK
40.149	-0.032	tSu		1	R16C4[0][B]	u_test/burst_rnum_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path5

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R13C4[0][A]	u_test/RD_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R13C4[0][A]	u_test/RD_CNT_0_s3/CLK
40.149	-0.032	tSu		1	R13C4[0][A]	u_test/RD_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path6

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_1_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R14C5[2][A]	u_test/RD_CNT_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R14C5[2][A]	u_test/RD_CNT_1_s3/CLK
40.149	-0.032	tSu		1	R14C5[2][A]	u_test/RD_CNT_1_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_4_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R13C4[0][B]	u_test/RD_CNT_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R13C4[0][B]	u_test/RD_CNT_4_s3/CLK
40.149	-0.032	tSu		1	R13C4[0][B]	u_test/RD_CNT_4_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_7_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R12C4[2][A]	u_test/RD_CNT_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R12C4[2][A]	u_test/RD_CNT_7_s3/CLK
40.149	-0.032	tSu		1	R12C4[2][A]	u_test/RD_CNT_7_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path9

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_8_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R13C4[2][A]	u_test/RD_CNT_8_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R13C4[2][A]	u_test/RD_CNT_8_s3/CLK
40.149	-0.032	tSu		1	R13C4[2][A]	u_test/RD_CNT_8_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R17C8[0][A]	u_test/WR_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R17C8[0][A]	u_test/WR_CNT_0_s3/CLK
40.149	-0.032	tSu		1	R17C8[0][A]	u_test/WR_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_1_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R16C8[0][B]	u_test/WR_CNT_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R16C8[0][B]	u_test/WR_CNT_1_s3/CLK
40.149	-0.032	tSu		1	R16C8[0][B]	u_test/WR_CNT_1_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_4_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R16C8[2][A]	u_test/WR_CNT_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R16C8[2][A]	u_test/WR_CNT_4_s3/CLK
40.149	-0.032	tSu		1	R16C8[2][A]	u_test/WR_CNT_4_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_7_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R14C7[0][A]	u_test/WR_CNT_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R14C7[0][A]	u_test/WR_CNT_7_s3/CLK
40.149	-0.032	tSu		1	R14C7[0][A]	u_test/WR_CNT_7_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_8_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R16C8[0][A]	u_test/WR_CNT_8_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R16C8[0][A]	u_test/WR_CNT_8_s3/CLK
40.149	-0.032	tSu		1	R16C8[0][A]	u_test/WR_CNT_8_s3

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_1_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C7[0][B]	u_test/check_data_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C7[0][B]	u_test/check_data_1_s1/CLK
40.149	-0.032	tSu		1	R9C7[0][B]	u_test/check_data_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path16

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_2_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C6[2][A]	u_test/check_data_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C6[2][A]	u_test/check_data_2_s1/CLK
40.149	-0.032	tSu		1	R9C6[2][A]	u_test/check_data_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path17

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C6[1][A]	u_test/check_data_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C6[1][A]	u_test/check_data_3_s1/CLK
40.149	-0.032	tSu		1	R9C6[1][A]	u_test/check_data_3_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path18

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_4_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C7[1][A]	u_test/check_data_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C7[1][A]	u_test/check_data_4_s1/CLK
40.149	-0.032	tSu		1	R9C7[1][A]	u_test/check_data_4_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path19

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C7[1][B]	u_test/check_data_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C7[1][B]	u_test/check_data_5_s1/CLK
40.149	-0.032	tSu		1	R9C7[1][B]	u_test/check_data_5_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_6_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C6[2][B]	u_test/check_data_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C6[2][B]	u_test/check_data_6_s1/CLK
40.149	-0.032	tSu		1	R9C6[2][B]	u_test/check_data_6_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path21

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_7_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C6[1][B]	u_test/check_data_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C6[1][B]	u_test/check_data_7_s1/CLK
40.149	-0.032	tSu		1	R9C6[1][B]	u_test/check_data_7_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_8_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C5[2][A]	u_test/check_data_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C5[2][A]	u_test/check_data_8_s1/CLK
40.149	-0.032	tSu		1	R9C5[2][A]	u_test/check_data_8_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_9_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R9C5[2][B]	u_test/check_data_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R9C5[2][B]	u_test/check_data_9_s1/CLK
40.149	-0.032	tSu		1	R9C5[2][B]	u_test/check_data_9_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path24

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_10_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R8C4[2][A]	u_test/check_data_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R8C4[2][A]	u_test/check_data_10_s1/CLK
40.149	-0.032	tSu		1	R8C4[2][A]	u_test/check_data_10_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack	37.557
Data Arrival Time	2.592
Data Required Time	40.149
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_11_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.181	0.181	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.520	0.340	tC2Q	RF	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
2.592	2.072	tNET	FF	1	R6C6[0][A]	u_test/check_data_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
40.000	40.000					active clock edge time
40.000	0.000					user_clk
40.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
40.181	0.181	tNET	RR	1	R6C6[0][A]	u_test/check_data_11_s1/CLK
40.149	-0.032	tSu		1	R6C6[0][A]	u_test/check_data_11_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	40.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.072, 85.916%; tC2Q: 0.340, 14.084%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.181, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C7[2][A]	u_test/check_data_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C7[2][A]	u_test/check_data_0_s3/CLK
0.146	0.009	tHld		1	R9C7[2][A]	u_test/check_data_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/d_clr_flag_s6
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C6[0][A]	u_test/d_clr_flag_s6/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C6[0][A]	u_test/d_clr_flag_s6/CLK
0.146	0.009	tHld		1	R9C6[0][A]	u_test/d_clr_flag_s6

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/cyc_cnt_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R16C4[0][A]	u_test/cyc_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C4[0][A]	u_test/cyc_cnt_0_s3/CLK
0.146	0.009	tHld		1	R16C4[0][A]	u_test/cyc_cnt_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/burst_rnum_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R16C4[0][B]	u_test/burst_rnum_0_s3/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C4[0][B]	u_test/burst_rnum_0_s3/CLK
0.146	0.009	tHld		1	R16C4[0][B]	u_test/burst_rnum_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R13C4[0][A]	u_test/RD_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C4[0][A]	u_test/RD_CNT_0_s3/CLK
0.146	0.009	tHld		1	R13C4[0][A]	u_test/RD_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_1_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R14C5[2][A]	u_test/RD_CNT_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C5[2][A]	u_test/RD_CNT_1_s3/CLK
0.146	0.009	tHld		1	R14C5[2][A]	u_test/RD_CNT_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_4_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R13C4[0][B]	u_test/RD_CNT_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C4[0][B]	u_test/RD_CNT_4_s3/CLK
0.146	0.009	tHld		1	R13C4[0][B]	u_test/RD_CNT_4_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_7_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R12C4[2][A]	u_test/RD_CNT_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R12C4[2][A]	u_test/RD_CNT_7_s3/CLK
0.146	0.009	tHld		1	R12C4[2][A]	u_test/RD_CNT_7_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/RD_CNT_8_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R13C4[2][A]	u_test/RD_CNT_8_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R13C4[2][A]	u_test/RD_CNT_8_s3/CLK
0.146	0.009	tHld		1	R13C4[2][A]	u_test/RD_CNT_8_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_0_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R17C8[0][A]	u_test/WR_CNT_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R17C8[0][A]	u_test/WR_CNT_0_s3/CLK
0.146	0.009	tHld		1	R17C8[0][A]	u_test/WR_CNT_0_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_1_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R16C8[0][B]	u_test/WR_CNT_1_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C8[0][B]	u_test/WR_CNT_1_s3/CLK
0.146	0.009	tHld		1	R16C8[0][B]	u_test/WR_CNT_1_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_4_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R16C8[2][A]	u_test/WR_CNT_4_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C8[2][A]	u_test/WR_CNT_4_s3/CLK
0.146	0.009	tHld		1	R16C8[2][A]	u_test/WR_CNT_4_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_7_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R14C7[0][A]	u_test/WR_CNT_7_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R14C7[0][A]	u_test/WR_CNT_7_s3/CLK
0.146	0.009	tHld		1	R14C7[0][A]	u_test/WR_CNT_7_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/WR_CNT_8_s3
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R16C8[0][A]	u_test/WR_CNT_8_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R16C8[0][A]	u_test/WR_CNT_8_s3/CLK
0.146	0.009	tHld		1	R16C8[0][A]	u_test/WR_CNT_8_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_1_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C7[0][B]	u_test/check_data_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C7[0][B]	u_test/check_data_1_s1/CLK
0.146	0.009	tHld		1	R9C7[0][B]	u_test/check_data_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_2_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C6[2][A]	u_test/check_data_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C6[2][A]	u_test/check_data_2_s1/CLK
0.146	0.009	tHld		1	R9C6[2][A]	u_test/check_data_2_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_3_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C6[1][A]	u_test/check_data_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C6[1][A]	u_test/check_data_3_s1/CLK
0.146	0.009	tHld		1	R9C6[1][A]	u_test/check_data_3_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_4_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C7[1][A]	u_test/check_data_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C7[1][A]	u_test/check_data_4_s1/CLK
0.146	0.009	tHld		1	R9C7[1][A]	u_test/check_data_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_5_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C7[1][B]	u_test/check_data_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C7[1][B]	u_test/check_data_5_s1/CLK
0.146	0.009	tHld		1	R9C7[1][B]	u_test/check_data_5_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_6_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C6[2][B]	u_test/check_data_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C6[2][B]	u_test/check_data_6_s1/CLK
0.146	0.009	tHld		1	R9C6[2][B]	u_test/check_data_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_7_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C6[1][B]	u_test/check_data_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C6[1][B]	u_test/check_data_7_s1/CLK
0.146	0.009	tHld		1	R9C6[1][B]	u_test/check_data_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_8_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C5[2][A]	u_test/check_data_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C5[2][A]	u_test/check_data_8_s1/CLK
0.146	0.009	tHld		1	R9C5[2][A]	u_test/check_data_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_9_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R9C5[2][B]	u_test/check_data_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R9C5[2][B]	u_test/check_data_9_s1/CLK
0.146	0.009	tHld		1	R9C5[2][B]	u_test/check_data_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_10_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R8C4[2][A]	u_test/check_data_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R8C4[2][A]	u_test/check_data_10_s1/CLK
0.146	0.009	tHld		1	R8C4[2][A]	u_test/check_data_10_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack	1.379
Data Arrival Time	1.525
Data Required Time	0.146
From	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0
To	u_test/check_data_11_s1
Launch Clk	user_clk:[R]
Latch Clk	user_clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/CLK
0.384	0.247	tC2Q	RR	1245	R15C18[2][A]	u_psram_memory_interface_top/u_apsram_top/u_psram_init/init_calib_s0/Q
1.525	1.142	tNET	RR	1	R6C6[0][A]	u_test/check_data_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					user_clk
0.000	0.000	tCL	RR	2060	RIGHTSIDE[0]	u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT
0.137	0.137	tNET	RR	1	R6C6[0][A]	u_test/check_data_11_s1/CLK
0.146	0.009	tHld		1	R6C6[0][A]	u_test/check_data_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.142, 82.212%; tC2Q: 0.247, 17.788%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.137, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/key_rst_r_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/key_rst_r_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/key_rst_r_s0/CLK

MPW2

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_19_s0/CLK

MPW3

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_17_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_17_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_17_s0/CLK

MPW4

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_13_s0/CLK

MPW5

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_5_s0/CLK

MPW6

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_6_s0/CLK

MPW7

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_14_s0/CLK

MPW8

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_7_s0/CLK

MPW9

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_8_s0/CLK

MPW10

MPW Summary:

Slack:	6.948
Actual Width:	7.874
Required Width:	0.926
Type:	High Pulse Width
Clock:	cl_osc
Objects:	u_reset_key/cnt_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			cl_osc
0.000	0.000	tCL	RR	clk_ibuf/I
4.230	4.230	tINS	RR	clk_ibuf/O
4.411	0.181	tNET	RR	u_reset_key/cnt_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			cl_osc
10.000	0.000	tCL	FF	clk_ibuf/I
12.140	2.140	tINS	FF	clk_ibuf/O
12.285	0.145	tNET	FF	u_reset_key/cnt_18_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2060	clk_x1	27.875	0.195
1245	init_calib_d	29.916	2.693
299	u_test/burst_num_Z_9_4	30.779	4.181
152	u_psram_memory_interface_top/u_apsram_top/config_done_Z	33.356	2.703
150	u_test/wr_data_127_5	31.865	1.968
128	u_test/wr_data_add_127_10	33.201	1.825
127	u_test/check_data_127_12	32.482	2.787
127	u_test/d_clr_flag_9	30.496	3.166
74	u_psram_memory_interface_top/u_apsram_top/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_d0_0_5	37.642	1.986
65	u_psram_memory_interface_top/u_apsram_top/rd_data_valid_d0_Z_1[2]	35.277	2.309

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C5	100.00%
R2C6	100.00%
R2C22	100.00%
R3C7	100.00%
R12C31	100.00%
R12C33	100.00%
R12C34	100.00%
R12C32	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name cl_osc -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name memory_clk -period 20 -waveform {0 10} [get_pins {u_pll/rpll_inst/CLKOUT}]
TC_CLOCK	Actived	create_clock -name memory_clk_p -period 20 -waveform {1.563 10} [get_pins {u_pll/rpll_inst/CLKOUTP}]
TC_CLOCK	Actived	create_clock -name clk_d -period 80 -waveform {0 40} [get_pins {u_pll/rpll_inst/CLKOUTD}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name user_clk -source [get_pins {u_pll/rpll_inst/CLKOUT}] -master_clock memory_clk -divide_by 2 [get_pins {u_psram_memory_interface_top/u_apsram_top/clkdiv/CLKOUT}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {cl_osc}] -group [get_clocks {memory_clk}] -group [get_clocks {user_clk}] -group [get_clocks {memory_clk_p}] -group [get_clocks {clk_d}]