Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
D:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
E:\IP\PSRAM\UHS_PSRAM_Memory_Interface\RefDesign\Gowin_UHS_PSRAM_Memory_Interface_RefDesign\uhs_psram_memory_interface_1_channel\project\fpga_project\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1NR-LV9MG100PAC7/I6
Device GW1NR-9
Device Version C
Created Time Thu May 22 10:45:21 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.359s, Elapsed time = 0h 0m 0.366s, Peak memory usage = 71.535MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 71.535MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 71.535MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 71.535MB
    Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 71.535MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 71.535MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 71.535MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 71.535MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 71.535MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 71.535MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 71.535MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 71.535MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 100.117MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.107s, Peak memory usage = 100.117MB
Generate output files:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.056s, Peak memory usage = 100.117MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 100.117MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 139
I/O Buf 139
    IBUF 138
    OBUF 1
Register 776
    DFF 275
    DFFR 1
    DFFP 3
    DFFPE 33
    DFFC 26
    DFFCE 438
LUT 524
    LUT2 60
    LUT3 122
    LUT4 342
MUX 1
    MUX16 1
ALU 13
    ALU 13
INV 4
    INV 4
BSRAM 8
    SDPX9B 8
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 549(536 LUT, 13 ALU) / 8640 7%
Register 776 / 6744 12%
  --Register as Latch 0 / 6744 0%
  --Register as FF 776 / 6744 12%
BSRAM 8 / 26 31%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk_x1 Base 20.000 50.000 0.000 10.000 clk_x1_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_x1 50.000(MHz) 115.985(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 11.378
Data Arrival Time 8.863
Data Required Time 20.242
From u_la0_top/capture_window_sel_0_s3
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 337 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/capture_window_sel_0_s3/CLK
0.878 0.340 tC2Q RF 14 u_la0_top/capture_window_sel_0_s3/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s18/I1
2.403 0.814 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s18/F
3.115 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/I0
3.879 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s17/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/I0
5.355 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s15/F
6.067 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/I0
6.832 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s12/F
7.543 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/I2
8.152 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_9_s10/F
8.863 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 337 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_start_reg_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.718, 44.654%; route: 4.268, 51.267%; tC2Q: 0.340, 4.079%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 337 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.878 0.340 tC2Q RF 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s6/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n875_s6/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s4/I1
5.405 0.814 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n875_s4/F
6.116 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n883_s1/I2
6.726 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n883_s1/F
7.437 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 337 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 337 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.878 0.340 tC2Q RF 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s6/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n875_s6/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s4/I1
5.405 0.814 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n875_s4/F
6.116 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n881_s1/I2
6.726 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n881_s1/F
7.437 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 337 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 337 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.878 0.340 tC2Q RF 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s6/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n875_s6/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s4/I1
5.405 0.814 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n875_s4/F
6.116 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n878_s1/I2
6.726 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n878_s1/F
7.437 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 337 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.805
Data Arrival Time 7.437
Data Required Time 20.242
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk clk_x1[R]
Latch Clk clk_x1[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1 clk_x1_ibuf/I
0.000 0.000 tINS RR 337 clk_x1_ibuf/O
0.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.878 0.340 tC2Q RF 13 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.589 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/I0
2.354 0.765 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n875_s10/F
3.065 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s6/I1
3.879 0.814 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n875_s6/F
4.591 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n875_s4/I1
5.405 0.814 tINS FF 10 u_la0_top/u_ao_mem_ctrl/n875_s4/F
6.116 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n876_s1/I2
6.726 0.609 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n876_s1/F
7.437 0.711 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1 clk_x1_ibuf/I
20.000 0.000 tINS RR 337 clk_x1_ibuf/O
20.538 0.538 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
20.242 -0.296 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.003, 43.522%; route: 3.557, 51.555%; tC2Q: 0.340, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%