Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\ipcore\SERDES_IP\IPlib\25GSERETH\data\ge_pcs.v
D:\Gowin\Gowin_V1.9.12.01_x64_internal\IDE\ipcore\SERDES_IP\IPlib\25GSERETH\data\ge_pcs_wrap.v
GowinSynthesis Constraints File ---
Tool Version V1.9.12.01 (64-bit)
Part Number GW5AST-LV138FPG676AES
Device GW5AST-138
Device Version B
Created Time Tue Dec 30 15:08:45 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Two_Giga_Serial_Ethernet_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 1s, Peak memory usage = 96.199MB
Running netlist conversion:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.099s, Peak memory usage = 96.199MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.362s, Peak memory usage = 96.199MB
    Optimizing Phase 1: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 96.199MB
    Optimizing Phase 2: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.397s, Peak memory usage = 96.199MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.204s, Peak memory usage = 96.199MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 96.199MB
    Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 96.199MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 96.199MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.342s, Peak memory usage = 96.199MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 96.199MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 96.199MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 8s, Peak memory usage = 118.910MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.3s, Peak memory usage = 118.910MB
Generate output files:
    CPU time = 0h 0m 0.296s, Elapsed time = 0h 0m 0.44s, Peak memory usage = 118.910MB
Total Time and Memory Usage CPU time = 0h 0m 9s, Elapsed time = 0h 0m 11s, Peak memory usage = 118.910MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 458
I/O Buf 456
    IBUF 195
    OBUF 261
Register 2371
    DFFSE 6
    DFFRE 88
    DFFPE 86
    DFFCE 2191
LUT 2634
    LUT2 517
    LUT3 554
    LUT4 1563
ALU 86
    ALU 86
INV 14
    INV 14

Resource Utilization Summary

Resource Usage Utilization
Logic 2734(2648 LUT, 86 ALU) / 138240 2%
Register 2371 / 139140 2%
  --Register as Latch 0 / 139140 0%
  --Register as FF 2371 / 139140 2%
BSRAM 0 / 340 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 serdes_pcs_rx_clk_i Base 10.000 100.000 0.000 5.000 serdes_pcs_rx_clk_i_ibuf/I
2 serdes_pcs_tx_clk_i Base 10.000 100.000 0.000 5.000 serdes_pcs_tx_clk_i_ibuf/I
3 clk_in_i Base 10.000 100.000 0.000 5.000 clk_in_i_ibuf/I
4 miim_hs_clk_i Base 10.000 100.000 0.000 5.000 miim_hs_clk_i_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 serdes_pcs_rx_clk_i 100.000(MHz) 169.241(MHz) 6 TOP
2 serdes_pcs_tx_clk_i 100.000(MHz) 148.727(MHz) 7 TOP
3 clk_in_i 100.000(MHz) 856.531(MHz) 1 TOP
4 miim_hs_clk_i 100.000(MHz) 200.451(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.276
Data Arrival Time 7.073
Data Required Time 10.349
From u_ge_pcs/u_ge_tx/encode_txd_0_s1
To u_ge_pcs/u_ge_tx/encode_txd_8_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
0.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_0_s1/CLK
0.795 0.382 tC2Q RR 4 u_ge_pcs/u_ge_tx/encode_txd_0_s1/Q
1.207 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/I0
1.786 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/F
2.199 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I0
2.778 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
3.190 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I1
3.758 0.567 tINS RR 2 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
4.170 0.413 tNET RR 1 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/I2
4.678 0.507 tINS RR 5 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/F
5.090 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n394_s2/I0
5.669 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n394_s2/F
6.081 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n394_s1/I0
6.660 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n394_s1/F
7.073 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_8_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
10.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_8_s1/CLK
10.349 -0.064 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_8_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.390, 50.901%; route: 2.887, 43.356%; tC2Q: 0.382, 5.743%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 2

Path Summary:
Slack 3.276
Data Arrival Time 7.073
Data Required Time 10.349
From u_ge_pcs/u_ge_tx/encode_txd_0_s1
To u_ge_pcs/u_ge_tx/encode_txd_12_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
0.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_0_s1/CLK
0.795 0.382 tC2Q RR 4 u_ge_pcs/u_ge_tx/encode_txd_0_s1/Q
1.207 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/I0
1.786 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/F
2.199 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I0
2.778 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
3.190 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I1
3.758 0.567 tINS RR 2 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
4.170 0.413 tNET RR 1 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/I2
4.678 0.507 tINS RR 5 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/F
5.090 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n390_s2/I0
5.669 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n390_s2/F
6.081 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n390_s4/I0
6.660 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n390_s4/F
7.073 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_12_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
10.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_12_s1/CLK
10.349 -0.064 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_12_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.390, 50.901%; route: 2.887, 43.356%; tC2Q: 0.382, 5.743%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 3

Path Summary:
Slack 3.276
Data Arrival Time 7.073
Data Required Time 10.349
From u_ge_pcs/u_ge_tx/encode_txd_0_s1
To u_ge_pcs/u_ge_tx/encode_txd_15_s2
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
0.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_0_s1/CLK
0.795 0.382 tC2Q RR 4 u_ge_pcs/u_ge_tx/encode_txd_0_s1/Q
1.207 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/I0
1.786 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/F
2.199 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I0
2.778 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
3.190 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I1
3.758 0.567 tINS RR 2 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
4.170 0.413 tNET RR 1 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/I2
4.678 0.507 tINS RR 5 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/F
5.090 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n387_s2/I0
5.669 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n387_s2/F
6.081 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n387_s4/I0
6.660 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n387_s4/F
7.073 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_15_s2/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
10.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_15_s2/CLK
10.349 -0.064 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_15_s2
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.390, 50.901%; route: 2.887, 43.356%; tC2Q: 0.382, 5.743%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 4

Path Summary:
Slack 3.287
Data Arrival Time 7.061
Data Required Time 10.349
From u_ge_pcs/u_ge_tx/encode_txd_0_s1
To u_ge_pcs/u_ge_tx/encode_txd_10_s1
Launch Clk serdes_pcs_tx_clk_i[R]
Latch Clk serdes_pcs_tx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_tx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
0.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
0.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_0_s1/CLK
0.795 0.382 tC2Q RR 4 u_ge_pcs/u_ge_tx/encode_txd_0_s1/Q
1.207 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/I0
1.786 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s3/F
2.199 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/I0
2.778 0.579 tINS RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s0/F
3.190 0.413 tNET RR 1 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/I1
3.758 0.567 tINS RR 2 u_ge_pcs/u1_encoder_8b10b_disparity/serdes_txdata_o_d_19_s/F
4.170 0.413 tNET RR 1 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/I2
4.678 0.507 tINS RR 5 u_ge_pcs/u2_encoder_8b10b_disparity/encode_disparity_comb_1_s/F
5.090 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n392_s2/I1
5.658 0.567 tINS RR 1 u_ge_pcs/u_ge_tx/n392_s2/F
6.070 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/n392_s1/I0
6.649 0.579 tINS RR 1 u_ge_pcs/u_ge_tx/n392_s1/F
7.061 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_10_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_tx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_tx_clk_i_ibuf/I
10.000 0.000 tINS RR 1063 serdes_pcs_tx_clk_i_ibuf/O
10.413 0.413 tNET RR 1 u_ge_pcs/u_ge_tx/encode_txd_10_s1/CLK
10.349 -0.064 tSu 1 u_ge_pcs/u_ge_tx/encode_txd_10_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 7
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 3.379, 50.818%; route: 2.887, 43.429%; tC2Q: 0.382, 5.753%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%

Path 5

Path Summary:
Slack 4.091
Data Arrival Time 6.010
Data Required Time 10.101
From u_ge_pcs/u_ge_rx/c_state_3_s0
To u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1
Launch Clk serdes_pcs_rx_clk_i[R]
Latch Clk serdes_pcs_rx_clk_i[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 serdes_pcs_rx_clk_i
0.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
0.000 0.000 tINS RR 1229 serdes_pcs_rx_clk_i_ibuf/O
0.413 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/c_state_3_s0/CLK
0.795 0.382 tC2Q RR 17 u_ge_pcs/u_ge_rx/c_state_3_s0/Q
1.207 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/receiving_m_set_h_s4/I0
1.786 0.579 tINS RR 11 u_ge_pcs/u_ge_rx/receiving_m_set_h_s4/F
2.199 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/idle_cnt_1_s10/I0
2.778 0.579 tINS RR 9 u_ge_pcs/u_ge_rx/idle_cnt_1_s10/F
3.190 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/idle_cnt_1_s4/I2
3.697 0.507 tINS RR 2 u_ge_pcs/u_ge_rx/idle_cnt_1_s4/F
4.110 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/I2
4.618 0.507 tINS RR 2 u_ge_pcs/u_ge_rx/rx_config_cnt_2_s4/F
5.030 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/I1
5.598 0.567 tINS RR 2 u_ge_pcs/u_ge_rx/rx_config_cnt_2_s15/F
6.010 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 serdes_pcs_rx_clk_i
10.000 0.000 tCL RR 1 serdes_pcs_rx_clk_i_ibuf/I
10.000 0.000 tINS RR 1229 serdes_pcs_rx_clk_i_ibuf/O
10.413 0.413 tNET RR 1 u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1/CLK
10.101 -0.311 tSu 1 u_ge_pcs/u_ge_rx/rx_config_cnt_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%
Arrival Data Path Delay: cell: 2.740, 48.951%; route: 2.475, 44.216%; tC2Q: 0.382, 6.833%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.413, 100.000%