Power Messages

Report Title	Power Analysis Report
Design File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.cst
Timing Constraints File	E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\fpga_project.sdc
Tool Version	V1.9.12.01 (64-bit)
Part Number	GW5AST-LV138FPG676AES
Device	GW5AST-138
Device Version	B
Created Time	Tue Dec 30 15:11:06 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade	Commercial
Process	Typical
Ambient Temperature	25.000
Use Custom Theta JA	false
Heat Sink	None
Air Flow	LFM_0
Use Custom Theta SA	false
Board Thermal Model	None
Use Custom Theta JB	false
Related Vcd File
Related Saif File
Filter Glitches	false
Default IO Toggle Rate	0.125
Default Remain Toggle Rate	0.125

Power Summary

Power Information:

Total Power (mW)	114.838
Quiescent Power (mW)	100.731
Dynamic Power (mW)	14.107

Thermal Information:

Junction Temperature	26.404
Theta JA	12.222
Max Allowed Ambient Temperature	83.596

Supply Information:

Voltage Source	Voltage	Dynamic Current(mA)	Quiescent Current(mA)	Power(mW)
VCC	0.900	13.738	80.007	84.371
VCCX	1.800	0.340	7.200	13.572
VCCIO33	3.300	0.342	3.032	11.134
VCCLDO	1.200	0.000	4.800	5.760

Power Details

Power By Block Type:

Block Type	Total Power(mW)	Static Power(mW)	Average Toggle Rate(millions of transitions/sec)
Logic	4.199	NA	13.356
IO	12.808	10.759	17.148
PLL	7.839	NA	NA

Power By Hierarchy:

Hierarchy Entity	Total Power(mW)	Block Dynamic Power(mW)
top	12.039	12.039(12.011)
top/sw1/	0.002	0.002(0.000)
top/u_SerDes_Top/	2.155	2.155(2.155)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/	2.155	2.155(2.155)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/	2.155	2.155(2.132)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u1_encoder_8b10b_disparity/	0.003	0.003(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u2_encoder_8b10b_disparity/	0.004	0.004(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_an/	0.171	0.171(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_rx/	0.358	0.358(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_sync/	0.077	0.077(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_ge_tx/	0.171	0.171(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/	0.610	0.610(0.143)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_rx_ctrl/u_crc_chk/	0.143	0.143(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/	0.730	0.730(0.174)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_crc_gen/	0.146	0.146(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_mac_tx_ctrl/u_lfsr/	0.028	0.028(0.000)
top/u_SerDes_Top/Two_Giga_Serial_Ethernet_Top_inst/u_ge_pcs/u_serdes_control/	0.007	0.007(0.000)
top/u_Uart_to_Bus_Top/	0.070	0.070(0.070)
top/u_Uart_to_Bus_Top/uart_bus_core/	0.070	0.070(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/	0.065	0.065(0.065)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_bus_inf_md/	0.002	0.002(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/	0.031	0.031(0.031)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/	0.028	0.028(0.022)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_parser_rx_md/u_uart_rx_async_fifo/	0.022	0.022(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_rx_md/u_uart_serial_rx_md/	0.002	0.002(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/	0.032	0.032(0.032)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/	0.029	0.029(0.023)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_parser_tx_md/u_uart_tx_async_fifo/	0.023	0.023(0.000)
top/u_Uart_to_Bus_Top/uart_bus_core/u_uart_md/u_uart_tx_md/u_uart_serial_tx_md/	0.003	0.003(0.000)
top/u_mac_rx_model_word/	1.143	1.143(0.000)
top/u_mac_tx_model_word/	0.716	0.716(0.000)
top/u_pll_uart/	7.874	7.874(7.874)
top/u_pll_uart/u_pll/	7.839	7.839(0.000)
top/u_pll_uart/u_pll_init/	0.035	0.035(0.000)
top/u_sysreg/	0.050	0.050(0.000)
top/uart1/	0.002	0.002(0.000)

Power By Clock Domain:

Clock Domain	Clock Frequency(Mhz)	Total Dynamic Power(mW)
clk_in	52.499	0.007
clk_uart	10.000	0.105
rx_mac_clk	156.250	2.409
tx_mac_clk	156.250	1.662
board_clk	50.000	7.875