Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\button.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\mac_rx_model_word.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\mac_tx_model_word.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\pll_init.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\pll_uart\pll_uart.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\pll_uart\pll_uart_mod.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\serdes\serdes.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\serdes\two_giga_serial_ethernet\two_giga_serial_ethernet.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\sysreg.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\top.v E:\IP_Release\2.5G_Serial_Ethernet_Over_Serdes\1.5\Gowin_2.5G_Serial_Ethernet_RefDesign\project\src\uart_to_bus\uart_to_bus.v |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.12.01 (64-bit) |
| Part Number | GW5AST-LV138FPG676AES |
| Device | GW5AST-138 |
| Device Version | B |
| Created Time | Tue Dec 30 15:10:03 2025 |
| Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1818.762MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.617s, Peak memory usage = 1818.762MB Optimizing Phase 1: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.467s, Peak memory usage = 1818.762MB Optimizing Phase 2: CPU time = 0h 0m 0.875s, Elapsed time = 0h 0m 0.87s, Peak memory usage = 1818.762MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.422s, Peak memory usage = 1818.762MB Inferring Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 1818.762MB Inferring Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 1818.762MB Inferring Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.091s, Peak memory usage = 1818.762MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 1818.762MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.276s, Peak memory usage = 1818.762MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 1818.762MB Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 1818.762MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.588s, Peak memory usage = 1818.762MB Generate output files: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.643s, Peak memory usage = 1818.762MB |
| Total Time and Memory Usage | CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s, Peak memory usage = 1818.762MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 8 |
| I/O Buf | 8 |
| IBUF | 3 |
| OBUF | 5 |
| Register | 5391 |
| DFFSE | 6 |
| DFFRE | 988 |
| DFFPE | 159 |
| DFFCE | 4238 |
| LUT | 5218 |
| LUT2 | 652 |
| LUT3 | 1665 |
| LUT4 | 2901 |
| ALU | 408 |
| ALU | 408 |
| INV | 35 |
| INV | 35 |
| CLOCK | 2 |
| PLL | 1 |
| OSC | 1 |
| GTR12_QUAD | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5661(5253 LUT, 408 ALU) / 138240 | 5% |
| Register | 5391 / 139140 | 4% |
| --Register as Latch | 0 / 139140 | 0% |
| --Register as FF | 5391 / 139140 | 4% |
| BSRAM | 0 / 340 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | u_osc/OSCOUT.default_clk | Base | 19.048 | 52.500 | 0.000 | 9.524 | u_osc/OSCOUT | ||
| 2 | board_clk | Base | 20.000 | 50.000 | 0.000 | 10.000 | board_clk_ibuf/I | ||
| 3 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | Generated | 100.000 | 10.000 | 0.000 | 50.000 | board_clk_ibuf/I | board_clk | u_pll_uart/u_pll/PLL_inst/CLKOUT0 |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_osc/OSCOUT.default_clk | 52.500(MHz) | 361.011(MHz) | 3 | TOP |
| 2 | board_clk | 50.000(MHz) | 207.308(MHz) | 5 | TOP |
| 3 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | 10.000(MHz) | 128.432(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 1.206 |
| Data Arrival Time | 99.408 |
| Data Required Time | 100.614 |
| From | sw1/bout_s0 |
| To | u_sysreg/uart_rdata_5_s0 |
| Launch Clk | u_osc/OSCOUT.default_clk[R] |
| Latch Clk | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 95.238 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 95.238 | 0.000 | tCL | RR | 29 | u_osc/OSCOUT |
| 95.651 | 0.413 | tNET | RR | 1 | sw1/bout_s0/CLK |
| 96.033 | 0.382 | tC2Q | RR | 2 | sw1/bout_s0/Q |
| 96.446 | 0.413 | tNET | RR | 1 | rstn_ip_s0/I0 |
| 97.024 | 0.579 | tINS | RR | 4 | rstn_ip_s0/F |
| 97.437 | 0.413 | tNET | RR | 1 | u_sysreg/n1787_s37/I0 |
| 98.016 | 0.579 | tINS | RR | 1 | u_sysreg/n1787_s37/F |
| 98.428 | 0.413 | tNET | RR | 1 | u_sysreg/n1787_s35/I1 |
| 98.996 | 0.567 | tINS | RR | 1 | u_sysreg/n1787_s35/F |
| 99.408 | 0.413 | tNET | RR | 1 | u_sysreg/uart_rdata_5_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 2005 | u_pll_uart/u_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_sysreg/uart_rdata_5_s0/CLK |
| 100.678 | -0.035 | tUnc | u_sysreg/uart_rdata_5_s0 | ||
| 100.614 | -0.064 | tSu | 1 | u_sysreg/uart_rdata_5_s0 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 4.762 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 1.725, 45.908%; route: 1.650, 43.912%; tC2Q: 0.382, 10.180% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 2
Path Summary:| Slack | 3.568 |
| Data Arrival Time | 301.508 |
| Data Required Time | 305.076 |
| From | u_sysreg/reg0x0030_0_s0 |
| To | uart1/temp_0_s0 |
| Launch Clk | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| Latch Clk | u_osc/OSCOUT.default_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 300.000 | 0.000 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 300.300 | 0.300 | tCL | RR | 2005 | u_pll_uart/u_pll/PLL_inst/CLKOUT0 |
| 300.713 | 0.413 | tNET | RR | 1 | u_sysreg/reg0x0030_0_s0/CLK |
| 301.095 | 0.382 | tC2Q | RR | 2 | u_sysreg/reg0x0030_0_s0/Q |
| 301.508 | 0.413 | tNET | RR | 1 | uart1/temp_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 304.762 | 0.000 | u_osc/OSCOUT.default_clk | |||
| 304.762 | 0.000 | tCL | RR | 29 | u_osc/OSCOUT |
| 305.174 | 0.413 | tNET | RR | 1 | uart1/temp_0_s0/CLK |
| 305.139 | -0.035 | tUnc | uart1/temp_0_s0 | ||
| 305.076 | -0.064 | tSu | 1 | uart1/temp_0_s0 |
| Clock Skew: | -0.300 |
| Setup Relationship: | 4.762 |
| Logic Level: | 1 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 0.000, 0.000%; route: 0.413, 51.887%; tC2Q: 0.382, 48.113% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 3
Path Summary:| Slack | 15.176 |
| Data Arrival Time | 5.173 |
| Data Required Time | 20.349 |
| From | u_pll_uart/u_pll_init/locksig_0_s0 |
| To | u_pll_uart/u_pll_init/RomAddr_2_s1 |
| Launch Clk | board_clk[R] |
| Latch Clk | board_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | board_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/locksig_0_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_pll_uart/u_pll_init/locksig_0_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s17/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s17/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s15/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s15/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s13/I0 |
| 3.769 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s13/F |
| 4.181 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n523_s12/I0 |
| 4.760 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n523_s12/F |
| 5.173 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | board_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | board_clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1/CLK |
| 20.349 | -0.064 | tSu | 1 | u_pll_uart/u_pll_init/RomAddr_2_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.315, 48.634%; route: 2.062, 43.330%; tC2Q: 0.382, 8.036% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 4
Path Summary:| Slack | 15.248 |
| Data Arrival Time | 5.101 |
| Data Required Time | 20.349 |
| From | u_pll_uart/u_pll_init/locksig_5_s0 |
| To | u_pll_uart/u_pll_init/RomAddr_1_s1 |
| Launch Clk | board_clk[R] |
| Latch Clk | board_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | board_clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 40 | board_clk_ibuf/O |
| 0.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/locksig_5_s0/CLK |
| 0.795 | 0.382 | tC2Q | RR | 6 | u_pll_uart/u_pll_init/locksig_5_s0/Q |
| 1.207 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n525_s16/I0 |
| 1.786 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n525_s16/F |
| 2.199 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n525_s15/I0 |
| 2.778 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n525_s15/F |
| 3.190 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n525_s13/I2 |
| 3.697 | 0.507 | tINS | RR | 1 | u_pll_uart/u_pll_init/n525_s13/F |
| 4.110 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/n525_s12/I0 |
| 4.689 | 0.579 | tINS | RR | 1 | u_pll_uart/u_pll_init/n525_s12/F |
| 5.101 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | board_clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | board_clk_ibuf/O |
| 20.413 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/RomAddr_1_s1/CLK |
| 20.349 | -0.064 | tSu | 1 | u_pll_uart/u_pll_init/RomAddr_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.244, 47.854%; route: 2.062, 43.988%; tC2Q: 0.382, 8.158% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
Path 5
Path Summary:| Slack | 15.524 |
| Data Arrival Time | 85.090 |
| Data Required Time | 100.614 |
| From | u_pll_uart/u_pll_init/state_0_s0 |
| To | u_sysreg/uart_rdata_0_s0 |
| Launch Clk | board_clk[R] |
| Latch Clk | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 80.000 | 0.000 | board_clk | |||
| 80.000 | 0.000 | tCL | RR | 1 | board_clk_ibuf/I |
| 80.000 | 0.000 | tINS | RR | 40 | board_clk_ibuf/O |
| 80.412 | 0.413 | tNET | RR | 1 | u_pll_uart/u_pll_init/state_0_s0/CLK |
| 80.795 | 0.382 | tC2Q | RR | 9 | u_pll_uart/u_pll_init/state_0_s0/Q |
| 81.207 | 0.413 | tNET | RR | 1 | n64_s1/I0 |
| 81.786 | 0.579 | tINS | RR | 17 | n64_s1/F |
| 82.199 | 0.413 | tNET | RR | 1 | u_sysreg/n1792_s45/I1 |
| 82.766 | 0.567 | tINS | RR | 1 | u_sysreg/n1792_s45/F |
| 83.179 | 0.413 | tNET | RR | 1 | u_sysreg/n1792_s38/I0 |
| 83.757 | 0.579 | tINS | RR | 1 | u_sysreg/n1792_s38/F |
| 84.170 | 0.413 | tNET | RR | 1 | u_sysreg/n1792_s35/I2 |
| 84.677 | 0.507 | tINS | RR | 1 | u_sysreg/n1792_s35/F |
| 85.090 | 0.413 | tNET | RR | 1 | u_sysreg/uart_rdata_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 100.000 | 0.000 | u_pll_uart/u_pll/PLL_inst/CLKOUT0.default_gen_clk | |||
| 100.300 | 0.300 | tCL | RR | 2005 | u_pll_uart/u_pll/PLL_inst/CLKOUT0 |
| 100.713 | 0.413 | tNET | RR | 1 | u_sysreg/uart_rdata_0_s0/CLK |
| 100.678 | -0.035 | tUnc | u_sysreg/uart_rdata_0_s0 | ||
| 100.614 | -0.064 | tSu | 1 | u_sysreg/uart_rdata_0_s0 |
| Clock Skew: | 0.300 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |
| Arrival Data Path Delay: | cell: 2.233, 47.729%; route: 2.062, 44.094%; tC2Q: 0.382, 8.177% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.413, 100.000% |