Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPADDSUB\data\FP_Add_Sub.v
C:\Gowin\Gowin_V1.9.9Beta-1\IDE\ipcore\FPADDSUB\data\FP_Add_Sub_wrap.v
GowinSynthesis Constraints File ---
Version V1.9.9 Beta-1
Part Number GW2A-LV55PG484C8/I7
Device GW2A-55
Device Version C
Created Time Tue May 16 17:46:43 2023
Legal Announcement Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module FP_Add_Sub_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 29.902MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 29.902MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 29.902MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 29.902MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 29.902MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 29.902MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 29.902MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 29.902MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 29.902MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.049s, Peak memory usage = 29.902MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 29.902MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 29.902MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 46.324MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 46.324MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.085s, Peak memory usage = 46.324MB
Total Time and Memory Usage CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 46.324MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 103
I/O Buf 103
    IBUF 67
    OBUF 36
Register 182
    DFFCE 182
LUT 1176
    LUT2 68
    LUT3 426
    LUT4 682
ALU 95
    ALU 95
INV 1
    INV 1
DSP 1
    ALU54D 1

Resource Utilization Summary

Resource Usage Utilization
Logic 1272(1177 LUTs, 95 ALUs) / 54720 3%
Register 182 / 41997 <1%
  --Register as Latch 0 / 41997 0%
  --Register as FF 182 / 41997 <1%
BSRAM 0 / 140 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 85.6(MHz) 17 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -1.680
Data Arrival Time 12.508
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_6_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.535 0.035 tINS FF 1 FP_Add_Sub_inst/n788_s/COUT
2.535 0.000 tNET FF 2 FP_Add_Sub_inst/n787_s/CIN
2.570 0.035 tINS FF 1 FP_Add_Sub_inst/n787_s/COUT
2.570 0.000 tNET FF 2 FP_Add_Sub_inst/n786_s/CIN
2.606 0.035 tINS FF 1 FP_Add_Sub_inst/n786_s/COUT
2.606 0.000 tNET FF 2 FP_Add_Sub_inst/n785_s/CIN
2.641 0.035 tINS FF 1 FP_Add_Sub_inst/n785_s/COUT
2.641 0.000 tNET FF 2 FP_Add_Sub_inst/n784_s/CIN
3.111 0.470 tINS FF 4 FP_Add_Sub_inst/n784_s/SUM
3.348 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s19/I1
3.903 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_4_s19/F
4.140 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s23/I1
4.695 0.555 tINS FF 7 FP_Add_Sub_inst/shift_num_4_s23/F
4.932 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_3_s6/I1
5.487 0.555 tINS FF 3 FP_Add_Sub_inst/shift_num_3_s6/F
5.724 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s7/I2
6.177 0.453 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s7/F
6.414 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s8/I1
6.969 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s8/F
7.206 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I0
7.723 0.517 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s5/F
7.960 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s2/I2
8.413 0.453 tINS FF 72 FP_Add_Sub_inst/shift_num_0_s2/F
8.650 0.237 tNET FF 1 FP_Add_Sub_inst/n1212_s6/I2
9.103 0.453 tINS FF 5 FP_Add_Sub_inst/n1212_s6/F
9.340 0.237 tNET FF 1 FP_Add_Sub_inst/n1216_s6/I1
9.895 0.555 tINS FF 1 FP_Add_Sub_inst/n1216_s6/F
10.132 0.237 tNET FF 1 FP_Add_Sub_inst/n1216_s4/I1
10.687 0.555 tINS FF 3 FP_Add_Sub_inst/n1216_s4/F
10.924 0.237 tNET FF 1 FP_Add_Sub_inst/n1232_s2/I1
11.479 0.555 tINS FF 1 FP_Add_Sub_inst/n1232_s2/F
11.716 0.237 tNET FF 1 FP_Add_Sub_inst/n1232_s0/I1
12.271 0.555 tINS FF 1 FP_Add_Sub_inst/n1232_s0/F
12.508 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_6_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.095, 69.516%; route: 3.318, 28.492%; tC2Q: 0.232, 1.992%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack -1.680
Data Arrival Time 12.508
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_7_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.535 0.035 tINS FF 1 FP_Add_Sub_inst/n788_s/COUT
2.535 0.000 tNET FF 2 FP_Add_Sub_inst/n787_s/CIN
2.570 0.035 tINS FF 1 FP_Add_Sub_inst/n787_s/COUT
2.570 0.000 tNET FF 2 FP_Add_Sub_inst/n786_s/CIN
2.606 0.035 tINS FF 1 FP_Add_Sub_inst/n786_s/COUT
2.606 0.000 tNET FF 2 FP_Add_Sub_inst/n785_s/CIN
2.641 0.035 tINS FF 1 FP_Add_Sub_inst/n785_s/COUT
2.641 0.000 tNET FF 2 FP_Add_Sub_inst/n784_s/CIN
3.111 0.470 tINS FF 4 FP_Add_Sub_inst/n784_s/SUM
3.348 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s19/I1
3.903 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_4_s19/F
4.140 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s23/I1
4.695 0.555 tINS FF 7 FP_Add_Sub_inst/shift_num_4_s23/F
4.932 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_3_s6/I1
5.487 0.555 tINS FF 3 FP_Add_Sub_inst/shift_num_3_s6/F
5.724 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s7/I2
6.177 0.453 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s7/F
6.414 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s8/I1
6.969 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s8/F
7.206 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I0
7.723 0.517 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s5/F
7.960 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s2/I2
8.413 0.453 tINS FF 72 FP_Add_Sub_inst/shift_num_0_s2/F
8.650 0.237 tNET FF 1 FP_Add_Sub_inst/n1215_s7/I2
9.103 0.453 tINS FF 2 FP_Add_Sub_inst/n1215_s7/F
9.340 0.237 tNET FF 1 FP_Add_Sub_inst/n1215_s6/I1
9.895 0.555 tINS FF 2 FP_Add_Sub_inst/n1215_s6/F
10.132 0.237 tNET FF 1 FP_Add_Sub_inst/n1215_s4/I1
10.687 0.555 tINS FF 3 FP_Add_Sub_inst/n1215_s4/F
10.924 0.237 tNET FF 1 FP_Add_Sub_inst/n1231_s2/I1
11.479 0.555 tINS FF 1 FP_Add_Sub_inst/n1231_s2/F
11.716 0.237 tNET FF 1 FP_Add_Sub_inst/n1231_s0/I1
12.271 0.555 tINS FF 1 FP_Add_Sub_inst/n1231_s0/F
12.508 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_7_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.095, 69.516%; route: 3.318, 28.492%; tC2Q: 0.232, 1.992%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack -1.680
Data Arrival Time 12.508
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_14_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.535 0.035 tINS FF 1 FP_Add_Sub_inst/n788_s/COUT
2.535 0.000 tNET FF 2 FP_Add_Sub_inst/n787_s/CIN
2.570 0.035 tINS FF 1 FP_Add_Sub_inst/n787_s/COUT
2.570 0.000 tNET FF 2 FP_Add_Sub_inst/n786_s/CIN
2.606 0.035 tINS FF 1 FP_Add_Sub_inst/n786_s/COUT
2.606 0.000 tNET FF 2 FP_Add_Sub_inst/n785_s/CIN
2.641 0.035 tINS FF 1 FP_Add_Sub_inst/n785_s/COUT
2.641 0.000 tNET FF 2 FP_Add_Sub_inst/n784_s/CIN
3.111 0.470 tINS FF 4 FP_Add_Sub_inst/n784_s/SUM
3.348 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s19/I1
3.903 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_4_s19/F
4.140 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s23/I1
4.695 0.555 tINS FF 7 FP_Add_Sub_inst/shift_num_4_s23/F
4.932 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_3_s6/I1
5.487 0.555 tINS FF 3 FP_Add_Sub_inst/shift_num_3_s6/F
5.724 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s7/I2
6.177 0.453 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s7/F
6.414 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s8/I1
6.969 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s8/F
7.206 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I0
7.723 0.517 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s5/F
7.960 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s2/I2
8.413 0.453 tINS FF 72 FP_Add_Sub_inst/shift_num_0_s2/F
8.650 0.237 tNET FF 1 FP_Add_Sub_inst/n1212_s6/I2
9.103 0.453 tINS FF 5 FP_Add_Sub_inst/n1212_s6/F
9.340 0.237 tNET FF 1 FP_Add_Sub_inst/n1216_s6/I1
9.895 0.555 tINS FF 1 FP_Add_Sub_inst/n1216_s6/F
10.132 0.237 tNET FF 1 FP_Add_Sub_inst/n1216_s4/I1
10.687 0.555 tINS FF 3 FP_Add_Sub_inst/n1216_s4/F
10.924 0.237 tNET FF 1 FP_Add_Sub_inst/n1224_s2/I1
11.479 0.555 tINS FF 1 FP_Add_Sub_inst/n1224_s2/F
11.716 0.237 tNET FF 1 FP_Add_Sub_inst/n1224_s0/I1
12.271 0.555 tINS FF 1 FP_Add_Sub_inst/n1224_s0/F
12.508 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_14_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.095, 69.516%; route: 3.318, 28.492%; tC2Q: 0.232, 1.992%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack -1.680
Data Arrival Time 12.508
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_43_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.535 0.035 tINS FF 1 FP_Add_Sub_inst/n788_s/COUT
2.535 0.000 tNET FF 2 FP_Add_Sub_inst/n787_s/CIN
2.570 0.035 tINS FF 1 FP_Add_Sub_inst/n787_s/COUT
2.570 0.000 tNET FF 2 FP_Add_Sub_inst/n786_s/CIN
2.606 0.035 tINS FF 1 FP_Add_Sub_inst/n786_s/COUT
2.606 0.000 tNET FF 2 FP_Add_Sub_inst/n785_s/CIN
2.641 0.035 tINS FF 1 FP_Add_Sub_inst/n785_s/COUT
2.641 0.000 tNET FF 2 FP_Add_Sub_inst/n784_s/CIN
3.111 0.470 tINS FF 4 FP_Add_Sub_inst/n784_s/SUM
3.348 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s19/I1
3.903 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_4_s19/F
4.140 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s23/I1
4.695 0.555 tINS FF 7 FP_Add_Sub_inst/shift_num_4_s23/F
4.932 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_3_s6/I1
5.487 0.555 tINS FF 3 FP_Add_Sub_inst/shift_num_3_s6/F
5.724 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s7/I2
6.177 0.453 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s7/F
6.414 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s8/I1
6.969 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s8/F
7.206 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I0
7.723 0.517 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s5/F
7.960 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s2/I2
8.413 0.453 tINS FF 72 FP_Add_Sub_inst/shift_num_0_s2/F
8.650 0.237 tNET FF 1 FP_Add_Sub_inst/n1193_s10/I2
9.103 0.453 tINS FF 3 FP_Add_Sub_inst/n1193_s10/F
9.340 0.237 tNET FF 1 FP_Add_Sub_inst/n1195_s11/I1
9.895 0.555 tINS FF 2 FP_Add_Sub_inst/n1195_s11/F
10.132 0.237 tNET FF 1 FP_Add_Sub_inst/n1195_s6/I1
10.687 0.555 tINS FF 1 FP_Add_Sub_inst/n1195_s6/F
10.924 0.237 tNET FF 1 FP_Add_Sub_inst/n1195_s2/I1
11.479 0.555 tINS FF 1 FP_Add_Sub_inst/n1195_s2/F
11.716 0.237 tNET FF 1 FP_Add_Sub_inst/n1195_s0/I1
12.271 0.555 tINS FF 1 FP_Add_Sub_inst/n1195_s0/F
12.508 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_43_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_43_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_43_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.095, 69.516%; route: 3.318, 28.492%; tC2Q: 0.232, 1.992%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack -1.680
Data Arrival Time 12.508
Data Required Time 10.828
From FP_Add_Sub_inst/mant_shift_b_24_s0
To FP_Add_Sub_inst/norm0_mant_r_47_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 183 clk_ibuf/O
0.863 0.180 tNET RR 1 FP_Add_Sub_inst/mant_shift_b_24_s0/CLK
1.095 0.232 tC2Q RF 1 FP_Add_Sub_inst/mant_shift_b_24_s0/Q
1.332 0.237 tNET FF 2 FP_Add_Sub_inst/n806_s/I1
1.901 0.570 tINS FR 1 FP_Add_Sub_inst/n806_s/COUT
1.901 0.000 tNET RR 2 FP_Add_Sub_inst/n805_s/CIN
1.937 0.035 tINS RF 1 FP_Add_Sub_inst/n805_s/COUT
1.937 0.000 tNET FF 2 FP_Add_Sub_inst/n804_s/CIN
1.972 0.035 tINS FF 1 FP_Add_Sub_inst/n804_s/COUT
1.972 0.000 tNET FF 2 FP_Add_Sub_inst/n803_s/CIN
2.007 0.035 tINS FF 1 FP_Add_Sub_inst/n803_s/COUT
2.007 0.000 tNET FF 2 FP_Add_Sub_inst/n802_s/CIN
2.042 0.035 tINS FF 1 FP_Add_Sub_inst/n802_s/COUT
2.042 0.000 tNET FF 2 FP_Add_Sub_inst/n801_s/CIN
2.078 0.035 tINS FF 1 FP_Add_Sub_inst/n801_s/COUT
2.078 0.000 tNET FF 2 FP_Add_Sub_inst/n800_s/CIN
2.113 0.035 tINS FF 1 FP_Add_Sub_inst/n800_s/COUT
2.113 0.000 tNET FF 2 FP_Add_Sub_inst/n799_s/CIN
2.148 0.035 tINS FF 1 FP_Add_Sub_inst/n799_s/COUT
2.148 0.000 tNET FF 2 FP_Add_Sub_inst/n798_s/CIN
2.183 0.035 tINS FF 1 FP_Add_Sub_inst/n798_s/COUT
2.183 0.000 tNET FF 2 FP_Add_Sub_inst/n797_s/CIN
2.218 0.035 tINS FF 1 FP_Add_Sub_inst/n797_s/COUT
2.218 0.000 tNET FF 2 FP_Add_Sub_inst/n796_s/CIN
2.254 0.035 tINS FF 1 FP_Add_Sub_inst/n796_s/COUT
2.254 0.000 tNET FF 2 FP_Add_Sub_inst/n795_s/CIN
2.289 0.035 tINS FF 1 FP_Add_Sub_inst/n795_s/COUT
2.289 0.000 tNET FF 2 FP_Add_Sub_inst/n794_s/CIN
2.324 0.035 tINS FF 1 FP_Add_Sub_inst/n794_s/COUT
2.324 0.000 tNET FF 2 FP_Add_Sub_inst/n793_s/CIN
2.359 0.035 tINS FF 1 FP_Add_Sub_inst/n793_s/COUT
2.359 0.000 tNET FF 2 FP_Add_Sub_inst/n792_s/CIN
2.394 0.035 tINS FF 1 FP_Add_Sub_inst/n792_s/COUT
2.394 0.000 tNET FF 2 FP_Add_Sub_inst/n791_s/CIN
2.430 0.035 tINS FF 1 FP_Add_Sub_inst/n791_s/COUT
2.430 0.000 tNET FF 2 FP_Add_Sub_inst/n790_s/CIN
2.465 0.035 tINS FF 1 FP_Add_Sub_inst/n790_s/COUT
2.465 0.000 tNET FF 2 FP_Add_Sub_inst/n789_s/CIN
2.500 0.035 tINS FF 1 FP_Add_Sub_inst/n789_s/COUT
2.500 0.000 tNET FF 2 FP_Add_Sub_inst/n788_s/CIN
2.535 0.035 tINS FF 1 FP_Add_Sub_inst/n788_s/COUT
2.535 0.000 tNET FF 2 FP_Add_Sub_inst/n787_s/CIN
2.570 0.035 tINS FF 1 FP_Add_Sub_inst/n787_s/COUT
2.570 0.000 tNET FF 2 FP_Add_Sub_inst/n786_s/CIN
2.606 0.035 tINS FF 1 FP_Add_Sub_inst/n786_s/COUT
2.606 0.000 tNET FF 2 FP_Add_Sub_inst/n785_s/CIN
2.641 0.035 tINS FF 1 FP_Add_Sub_inst/n785_s/COUT
2.641 0.000 tNET FF 2 FP_Add_Sub_inst/n784_s/CIN
3.111 0.470 tINS FF 4 FP_Add_Sub_inst/n784_s/SUM
3.348 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s19/I1
3.903 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_4_s19/F
4.140 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_4_s23/I1
4.695 0.555 tINS FF 7 FP_Add_Sub_inst/shift_num_4_s23/F
4.932 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_3_s6/I1
5.487 0.555 tINS FF 3 FP_Add_Sub_inst/shift_num_3_s6/F
5.724 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s7/I2
6.177 0.453 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s7/F
6.414 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s8/I1
6.969 0.555 tINS FF 1 FP_Add_Sub_inst/shift_num_0_s8/F
7.206 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s5/I0
7.723 0.517 tINS FF 2 FP_Add_Sub_inst/shift_num_0_s5/F
7.960 0.237 tNET FF 1 FP_Add_Sub_inst/shift_num_0_s2/I2
8.413 0.453 tINS FF 72 FP_Add_Sub_inst/shift_num_0_s2/F
8.650 0.237 tNET FF 1 FP_Add_Sub_inst/n1193_s8/I2
9.103 0.453 tINS FF 3 FP_Add_Sub_inst/n1193_s8/F
9.340 0.237 tNET FF 1 FP_Add_Sub_inst/n1195_s9/I1
9.895 0.555 tINS FF 3 FP_Add_Sub_inst/n1195_s9/F
10.132 0.237 tNET FF 1 FP_Add_Sub_inst/n1199_s4/I1
10.687 0.555 tINS FF 2 FP_Add_Sub_inst/n1199_s4/F
10.924 0.237 tNET FF 1 FP_Add_Sub_inst/n1191_s3/I1
11.479 0.555 tINS FF 1 FP_Add_Sub_inst/n1191_s3/F
11.716 0.237 tNET FF 1 FP_Add_Sub_inst/n1191_s1/I1
12.271 0.555 tINS FF 1 FP_Add_Sub_inst/n1191_s1/F
12.508 0.237 tNET FF 1 FP_Add_Sub_inst/norm0_mant_r_47_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 183 clk_ibuf/O
10.863 0.180 tNET RR 1 FP_Add_Sub_inst/norm0_mant_r_47_s0/CLK
10.828 -0.035 tSu 1 FP_Add_Sub_inst/norm0_mant_r_47_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 17
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 8.095, 69.516%; route: 3.318, 28.492%; tC2Q: 0.232, 1.992%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%