Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ahb_regs.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\flash_controller_qspi.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_comp.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_conv.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_conv_addr_gen.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_conv_compute.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_pool.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\ml_pool_addr_gen.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\npu_integration.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\psram_interface.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\psram_controller.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\psram_io4x.v D:\Gowin\Gowin_V1.9.8.07_Education\IDE\ipcore\NPU\data\npu_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 Education |
| Part Number | GW2AR-LV18QN88PC8/I7 |
| Device | GW2AR-18C |
| Created Time | Wed Aug 03 10:46:12 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | NPU_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.671s, Elapsed time = 0h 0m 0.695s, Peak memory usage = 56.469MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.052s, Peak memory usage = 56.469MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.396s, Peak memory usage = 56.469MB Optimizing Phase 1: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.147s, Peak memory usage = 56.469MB Optimizing Phase 2: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.424s, Peak memory usage = 56.469MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.05s, Peak memory usage = 56.469MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 56.469MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 56.469MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 56.469MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 56.469MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.103s, Peak memory usage = 56.469MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 56.469MB Tech-Mapping Phase 3: CPU time = 0h 0m 17s, Elapsed time = 0h 0m 18s, Peak memory usage = 67.762MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.453s, Elapsed time = 0h 0m 0.453s, Peak memory usage = 67.762MB Generate output files: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.43s, Peak memory usage = 67.762MB |
| Total Time and Memory Usage | CPU time = 0h 0m 20s, Elapsed time = 0h 0m 21s, Peak memory usage = 67.762MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 96 |
| Embedded Port | 26 |
| I/O Buf | 109 |
| IBUF | 52 |
| OBUF | 44 |
| IOBUF | 13 |
| Register | 2092 |
| DFFE | 40 |
| DFFS | 2 |
| DFFR | 1 |
| DFFP | 8 |
| DFFPE | 29 |
| DFFC | 184 |
| DFFCE | 1784 |
| DFFNS | 1 |
| DFFNRE | 32 |
| DFFNC | 6 |
| DLNCE | 5 |
| LUT | 2620 |
| LUT2 | 247 |
| LUT3 | 698 |
| LUT4 | 1675 |
| ALU | 823 |
| ALU | 823 |
| INV | 15 |
| INV | 15 |
| IOLOGIC | 20 |
| IDES4 | 9 |
| OSER4 | 11 |
| DSP | 4 |
| MULT18X18 | 2 |
| MULT36X36 | 2 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3458(2635 LUTs, 823 ALUs) / 20736 | 17% |
| Register | 2092 / 15828 | 13% |
| --Register as Latch | 5 / 15828 | 1% |
| --Register as FF | 2087 / 15828 | 13% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I | ||
| pri_fclk90 | Base | 10.000 | 100.0 | 0.000 | 5.000 | pri_fclk90_ibuf/I | ||
| pri_fclk | Base | 10.000 | 100.0 | 0.000 | 5.000 | pri_fclk_ibuf/I | ||
| O_psram_reset_n_d[0] | Base | 10.000 | 100.0 | 0.000 | 5.000 | HRESETn_ibuf/O |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | HCLK | 100.0(MHz) | 87.2(MHz) | 17 | TOP |
| 2 | O_psram_reset_n_d[0] | 100.0(MHz) | 591.0(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -1.470 |
| Data Arrival Time | 12.298 |
| Data Required Time | 10.828 |
| From | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1 |
| To | u_npu_integration/prc/pri/c_state_1_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s0/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s0/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_2_s0/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_2_s0/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_3_s0/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_3_s0/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_4_s0/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_4_s0/COUT |
| 2.042 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_5_s0/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_5_s0/COUT |
| 2.078 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_6_s0/CIN |
| 2.113 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_6_s0/COUT |
| 2.113 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_7_s0/CIN |
| 2.148 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_7_s0/COUT |
| 2.148 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_8_s0/CIN |
| 2.183 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_8_s0/COUT |
| 2.183 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_9_s0/CIN |
| 2.218 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_9_s0/COUT |
| 2.218 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_10_s0/CIN |
| 2.254 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_10_s0/COUT |
| 2.254 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_11_s0/CIN |
| 2.289 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_11_s0/COUT |
| 2.289 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_12_s0/CIN |
| 2.324 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_12_s0/COUT |
| 2.324 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_13_s0/CIN |
| 2.794 | 0.470 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_13_s0/SUM |
| 3.031 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_13_s1/I1 |
| 3.601 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_13_s1/COUT |
| 3.601 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_14_s1/CIN |
| 4.071 | 0.470 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_14_s1/SUM |
| 4.308 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_14_s2/I0 |
| 4.857 | 0.549 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_14_s2/COUT |
| 4.857 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_15_s2/CIN |
| 5.327 | 0.470 | tINS | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_15_s2/SUM |
| 5.564 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s1/I0 |
| 6.081 | 0.517 | tINS | FF | 1 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s1/F |
| 6.318 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s0/I1 |
| 6.873 | 0.555 | tINS | FF | 2 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s0/F |
| 7.110 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s2/I0 |
| 7.627 | 0.517 | tINS | FF | 2 | u_npu_integration/ml_comp/layer_in_addr_Z_15_s2/F |
| 7.864 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/n45_s5/I2 |
| 8.317 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/n45_s5/F |
| 8.554 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/n45_s1/I1 |
| 9.109 | 0.555 | tINS | FF | 1 | u_npu_integration/prc/n45_s1/F |
| 9.346 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/n45_s0/I0 |
| 9.863 | 0.517 | tINS | FF | 67 | u_npu_integration/prc/n45_s0/F |
| 10.100 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/pri/n_state_1_s27/I0 |
| 10.617 | 0.517 | tINS | FF | 1 | u_npu_integration/prc/pri/n_state_1_s27/F |
| 10.854 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/pri/n_state_1_s23/I2 |
| 11.307 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/pri/n_state_1_s23/F |
| 11.544 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/pri/n_state_1_s22/I0 |
| 12.061 | 0.517 | tINS | FF | 1 | u_npu_integration/prc/pri/n_state_1_s22/F |
| 12.298 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/pri/c_state_1_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_npu_integration/prc/pri/c_state_1_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | u_npu_integration/prc/pri/c_state_1_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 17 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 8.122, 71.028%; route: 3.081, 26.943%; tC2Q: 0.232, 2.029% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 0.442 |
| Data Arrival Time | 10.165 |
| Data Required Time | 10.607 |
| From | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1 |
| To | u_npu_integration/ml_comp/pool/n517_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/SUM |
| 2.124 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/SUM |
| 2.916 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/I0 |
| 3.465 | 0.549 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/COUT |
| 3.465 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/CIN |
| 3.935 | 0.470 | tINS | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/SUM |
| 4.172 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/I3 |
| 4.543 | 0.371 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/F |
| 4.780 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/I2 |
| 5.233 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/F |
| 5.470 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s0/I2 |
| 5.923 | 0.453 | tINS | FF | 16 | u_npu_integration/prc/layer_in_data_Z_7_s0/F |
| 6.160 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s1/I2 |
| 6.613 | 0.453 | tINS | FF | 4 | u_npu_integration/prc/layer_in_data_Z_0_s1/F |
| 6.850 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s/I1 |
| 7.405 | 0.555 | tINS | FF | 3 | u_npu_integration/prc/layer_in_data_Z_0_s/F |
| 7.641 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n455_s/I1 |
| 8.212 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/n455_s/COUT |
| 8.212 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/n454_s/CIN |
| 8.247 | 0.035 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/n454_s/COUT |
| 8.247 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n453_s/CIN |
| 8.282 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n453_s/COUT |
| 8.282 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n452_s/CIN |
| 8.317 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n452_s/COUT |
| 8.317 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n451_s/CIN |
| 8.352 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n451_s/COUT |
| 8.352 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n450_s/CIN |
| 8.388 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n450_s/COUT |
| 8.388 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n449_s/CIN |
| 8.423 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n449_s/COUT |
| 8.423 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n448_s/CIN |
| 8.458 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n448_s/COUT |
| 8.458 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n447_s/CIN |
| 8.493 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n447_s/COUT |
| 8.493 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n446_s/CIN |
| 8.528 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n446_s/COUT |
| 8.528 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n445_s/CIN |
| 8.564 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n445_s/COUT |
| 8.564 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n444_s/CIN |
| 8.599 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n444_s/COUT |
| 8.599 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n443_s/CIN |
| 8.634 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n443_s/COUT |
| 8.634 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n442_s/CIN |
| 8.669 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n442_s/COUT |
| 8.669 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n441_s/CIN |
| 8.704 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n441_s/COUT |
| 8.704 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n440_s/CIN |
| 9.174 | 0.470 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n440_s/SUM |
| 9.411 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n461_s0/I0 |
| 9.928 | 0.517 | tINS | FF | 4 | u_npu_integration/ml_comp/pool/n461_s0/F |
| 10.165 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n517_s1/A[17] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/n517_s1/CLK |
| 10.607 | -0.255 | tSu | 1 | u_npu_integration/ml_comp/pool/n517_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.464, 69.482%; route: 2.607, 28.024%; tC2Q: 0.232, 2.494% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 0.442 |
| Data Arrival Time | 10.165 |
| Data Required Time | 10.607 |
| From | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1 |
| To | u_npu_integration/ml_comp/pool/n517_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/SUM |
| 2.124 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/SUM |
| 2.916 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/I0 |
| 3.465 | 0.549 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/COUT |
| 3.465 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/CIN |
| 3.935 | 0.470 | tINS | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/SUM |
| 4.172 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/I3 |
| 4.543 | 0.371 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/F |
| 4.780 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/I2 |
| 5.233 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/F |
| 5.470 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s0/I2 |
| 5.923 | 0.453 | tINS | FF | 16 | u_npu_integration/prc/layer_in_data_Z_7_s0/F |
| 6.160 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s1/I2 |
| 6.613 | 0.453 | tINS | FF | 4 | u_npu_integration/prc/layer_in_data_Z_0_s1/F |
| 6.850 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s/I1 |
| 7.405 | 0.555 | tINS | FF | 3 | u_npu_integration/prc/layer_in_data_Z_0_s/F |
| 7.641 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n455_s/I1 |
| 8.212 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/n455_s/COUT |
| 8.212 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/n454_s/CIN |
| 8.247 | 0.035 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/n454_s/COUT |
| 8.247 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n453_s/CIN |
| 8.282 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n453_s/COUT |
| 8.282 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n452_s/CIN |
| 8.317 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n452_s/COUT |
| 8.317 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n451_s/CIN |
| 8.352 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n451_s/COUT |
| 8.352 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n450_s/CIN |
| 8.388 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n450_s/COUT |
| 8.388 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n449_s/CIN |
| 8.423 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n449_s/COUT |
| 8.423 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n448_s/CIN |
| 8.458 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n448_s/COUT |
| 8.458 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n447_s/CIN |
| 8.493 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n447_s/COUT |
| 8.493 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n446_s/CIN |
| 8.528 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n446_s/COUT |
| 8.528 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n445_s/CIN |
| 8.564 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n445_s/COUT |
| 8.564 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n444_s/CIN |
| 8.599 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n444_s/COUT |
| 8.599 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n443_s/CIN |
| 8.634 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n443_s/COUT |
| 8.634 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n442_s/CIN |
| 8.669 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n442_s/COUT |
| 8.669 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n441_s/CIN |
| 8.704 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n441_s/COUT |
| 8.704 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n440_s/CIN |
| 9.174 | 0.470 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n440_s/SUM |
| 9.411 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n461_s0/I0 |
| 9.928 | 0.517 | tINS | FF | 4 | u_npu_integration/ml_comp/pool/n461_s0/F |
| 10.165 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n517_s1/A[16] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/n517_s1/CLK |
| 10.607 | -0.255 | tSu | 1 | u_npu_integration/ml_comp/pool/n517_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.464, 69.482%; route: 2.607, 28.024%; tC2Q: 0.232, 2.494% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 0.442 |
| Data Arrival Time | 10.165 |
| Data Required Time | 10.607 |
| From | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1 |
| To | u_npu_integration/ml_comp/pool/n517_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/SUM |
| 2.124 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/SUM |
| 2.916 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/I0 |
| 3.465 | 0.549 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/COUT |
| 3.465 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/CIN |
| 3.935 | 0.470 | tINS | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/SUM |
| 4.172 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/I3 |
| 4.543 | 0.371 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/F |
| 4.780 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/I2 |
| 5.233 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/F |
| 5.470 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s0/I2 |
| 5.923 | 0.453 | tINS | FF | 16 | u_npu_integration/prc/layer_in_data_Z_7_s0/F |
| 6.160 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s1/I2 |
| 6.613 | 0.453 | tINS | FF | 4 | u_npu_integration/prc/layer_in_data_Z_0_s1/F |
| 6.850 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s/I1 |
| 7.405 | 0.555 | tINS | FF | 3 | u_npu_integration/prc/layer_in_data_Z_0_s/F |
| 7.641 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n455_s/I1 |
| 8.212 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/n455_s/COUT |
| 8.212 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/n454_s/CIN |
| 8.247 | 0.035 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/n454_s/COUT |
| 8.247 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n453_s/CIN |
| 8.282 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n453_s/COUT |
| 8.282 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n452_s/CIN |
| 8.317 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n452_s/COUT |
| 8.317 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n451_s/CIN |
| 8.352 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n451_s/COUT |
| 8.352 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n450_s/CIN |
| 8.388 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n450_s/COUT |
| 8.388 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n449_s/CIN |
| 8.423 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n449_s/COUT |
| 8.423 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n448_s/CIN |
| 8.458 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n448_s/COUT |
| 8.458 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n447_s/CIN |
| 8.493 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n447_s/COUT |
| 8.493 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n446_s/CIN |
| 8.528 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n446_s/COUT |
| 8.528 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n445_s/CIN |
| 8.564 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n445_s/COUT |
| 8.564 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n444_s/CIN |
| 8.599 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n444_s/COUT |
| 8.599 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n443_s/CIN |
| 8.634 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n443_s/COUT |
| 8.634 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n442_s/CIN |
| 8.669 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n442_s/COUT |
| 8.669 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n441_s/CIN |
| 8.704 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n441_s/COUT |
| 8.704 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n440_s/CIN |
| 9.174 | 0.470 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n440_s/SUM |
| 9.411 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n461_s0/I0 |
| 9.928 | 0.517 | tINS | FF | 4 | u_npu_integration/ml_comp/pool/n461_s0/F |
| 10.165 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n517_s1/A[15] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/n517_s1/CLK |
| 10.607 | -0.255 | tSu | 1 | u_npu_integration/ml_comp/pool/n517_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.464, 69.482%; route: 2.607, 28.024%; tC2Q: 0.232, 2.494% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 0.477 |
| Data Arrival Time | 10.130 |
| Data Required Time | 10.607 |
| From | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1 |
| To | u_npu_integration/ml_comp/pool/n517_s1 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/image_addr_offset_0_s1/Q |
| 1.332 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s0/SUM |
| 2.124 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s1/SUM |
| 2.916 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/I0 |
| 3.465 | 0.549 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_0_s2/COUT |
| 3.465 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/CIN |
| 3.935 | 0.470 | tINS | RF | 2 | u_npu_integration/ml_comp/pool/addr_gen/layer_in_addr_1_s2/SUM |
| 4.172 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/I3 |
| 4.543 | 0.371 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s5/F |
| 4.780 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/I2 |
| 5.233 | 0.453 | tINS | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s2/F |
| 5.470 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_7_s0/I2 |
| 5.923 | 0.453 | tINS | FF | 16 | u_npu_integration/prc/layer_in_data_Z_7_s0/F |
| 6.160 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s1/I2 |
| 6.613 | 0.453 | tINS | FF | 4 | u_npu_integration/prc/layer_in_data_Z_0_s1/F |
| 6.850 | 0.237 | tNET | FF | 1 | u_npu_integration/prc/layer_in_data_Z_0_s/I1 |
| 7.405 | 0.555 | tINS | FF | 3 | u_npu_integration/prc/layer_in_data_Z_0_s/F |
| 7.641 | 0.237 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n455_s/I1 |
| 8.212 | 0.570 | tINS | FR | 1 | u_npu_integration/ml_comp/pool/n455_s/COUT |
| 8.212 | 0.000 | tNET | RR | 2 | u_npu_integration/ml_comp/pool/n454_s/CIN |
| 8.247 | 0.035 | tINS | RF | 1 | u_npu_integration/ml_comp/pool/n454_s/COUT |
| 8.247 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n453_s/CIN |
| 8.282 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n453_s/COUT |
| 8.282 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n452_s/CIN |
| 8.317 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n452_s/COUT |
| 8.317 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n451_s/CIN |
| 8.352 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n451_s/COUT |
| 8.352 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n450_s/CIN |
| 8.388 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n450_s/COUT |
| 8.388 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n449_s/CIN |
| 8.423 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n449_s/COUT |
| 8.423 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n448_s/CIN |
| 8.458 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n448_s/COUT |
| 8.458 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n447_s/CIN |
| 8.493 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n447_s/COUT |
| 8.493 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n446_s/CIN |
| 8.528 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n446_s/COUT |
| 8.528 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n445_s/CIN |
| 8.564 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n445_s/COUT |
| 8.564 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n444_s/CIN |
| 8.599 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n444_s/COUT |
| 8.599 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n443_s/CIN |
| 8.634 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n443_s/COUT |
| 8.634 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n442_s/CIN |
| 8.669 | 0.035 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n442_s/COUT |
| 8.669 | 0.000 | tNET | FF | 2 | u_npu_integration/ml_comp/pool/n441_s/CIN |
| 9.139 | 0.470 | tINS | FF | 1 | u_npu_integration/ml_comp/pool/n441_s/SUM |
| 9.376 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n462_s0/I0 |
| 9.893 | 0.517 | tINS | FF | 2 | u_npu_integration/ml_comp/pool/n462_s0/F |
| 10.130 | 0.237 | tNET | FF | 1 | u_npu_integration/ml_comp/pool/n517_s1/A[14] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2112 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_npu_integration/ml_comp/pool/n517_s1/CLK |
| 10.607 | -0.255 | tSu | 1 | u_npu_integration/ml_comp/pool/n517_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.429, 69.367%; route: 2.607, 28.130%; tC2Q: 0.232, 2.503% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |