Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\Interface\LPC_Peripheral\Gowin_LPC_Peripheral_RefDesign\project\src\LPC_Peripheral_Ref.v E:\myWork\IP\releaseVerify\RefDesign\Interface\LPC_Peripheral\Gowin_LPC_Peripheral_RefDesign\project\src\lpc_peripheral\lpc_peripheral.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW1N-LV9LQ144C6/I5 |
| Device | GW1N-9C |
| Created Time | Tue Jul 12 10:18:33 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | LPC_Peripheral_Ref |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.276s, Peak memory usage = 75.230MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 75.230MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 75.230MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 75.230MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 75.230MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 75.230MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.230MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 75.230MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 75.230MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.230MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 75.230MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.224s, Peak memory usage = 85.613MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 85.613MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 85.613MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.42s, Elapsed time = 0h 0m 0.605s, Peak memory usage = 85.613MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 7 |
| I/O Buf | 7 |
| IBUF | 3 |
| IOBUF | 4 |
| Register | 35 |
| DFFE | 16 |
| DFFS | 2 |
| DFFC | 16 |
| DFFCE | 1 |
| LUT | 99 |
| LUT2 | 17 |
| LUT3 | 16 |
| LUT4 | 66 |
| INV | 1 |
| INV | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 100(100 LUTs, 0 ALUs) / 8640 | 1% |
| Register | 35 / 6843 | 1% |
| --Register as Latch | 0 / 6843 | 0% |
| --Register as FF | 35 / 6843 | 1% |
| BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| LCLK | Base | 20.000 | 50.0 | 0.000 | 10.000 | LCLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | LCLK | 50.0(MHz) | 78.9(MHz) | 9 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 7.320 |
| Data Arrival Time | 13.625 |
| Data Required Time | 20.945 |
| From | lpc_peri_inst/u_lpc_peri/current_state_2_s0 |
| To | cnt_RdDelay_2_s0 |
| Launch Clk | LCLK[R] |
| Latch Clk | LCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | LCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 18 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s8/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/n423_s8/F |
| 3.862 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s6/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s6/F |
| 5.441 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n420_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n420_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3 |
| 8.948 | 0.626 | tINS | FF | 5 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/F |
| 9.428 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I0 |
| 10.460 | 1.032 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F |
| 10.940 | 0.480 | tNET | FF | 1 | n98_s3/I1 |
| 12.039 | 1.099 | tINS | FF | 2 | n98_s3/F |
| 12.519 | 0.480 | tNET | FF | 1 | n97_s3/I3 |
| 13.145 | 0.626 | tINS | FF | 1 | n97_s3/F |
| 13.625 | 0.480 | tNET | FF | 1 | cnt_RdDelay_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | LCLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | cnt_RdDelay_2_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | cnt_RdDelay_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 7.502, 61.090%; route: 4.320, 35.178%; tC2Q: 0.458, 3.732% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 2
Path Summary:| Slack | 7.320 |
| Data Arrival Time | 13.625 |
| Data Required Time | 20.945 |
| From | lpc_peri_inst/u_lpc_peri/current_state_2_s0 |
| To | cnt_RdDelay_3_s0 |
| Launch Clk | LCLK[R] |
| Latch Clk | LCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | LCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 18 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s8/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/n423_s8/F |
| 3.862 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s6/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s6/F |
| 5.441 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n420_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n420_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3 |
| 8.948 | 0.626 | tINS | FF | 5 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/F |
| 9.428 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I0 |
| 10.460 | 1.032 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F |
| 10.940 | 0.480 | tNET | FF | 1 | n98_s3/I1 |
| 12.039 | 1.099 | tINS | FF | 2 | n98_s3/F |
| 12.519 | 0.480 | tNET | FF | 1 | n96_s1/I3 |
| 13.145 | 0.626 | tINS | FF | 1 | n96_s1/F |
| 13.625 | 0.480 | tNET | FF | 1 | cnt_RdDelay_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | LCLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | cnt_RdDelay_3_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | cnt_RdDelay_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 7.502, 61.090%; route: 4.320, 35.178%; tC2Q: 0.458, 3.732% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 3
Path Summary:| Slack | 7.794 |
| Data Arrival Time | 13.507 |
| Data Required Time | 21.302 |
| From | lpc_peri_inst/u_lpc_peri/current_state_2_s0 |
| To | io_addr_hit_s1 |
| Launch Clk | LCLK[R] |
| Latch Clk | LCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | LCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 18 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s8/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/n423_s8/F |
| 3.862 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s6/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s6/F |
| 5.441 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n420_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n420_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3 |
| 8.948 | 0.626 | tINS | FF | 5 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/F |
| 9.428 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I0 |
| 10.460 | 1.032 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F |
| 10.940 | 0.480 | tNET | FF | 1 | n35_s0/I1 |
| 12.039 | 1.099 | tINS | FF | 2 | n35_s0/F |
| 12.519 | 0.480 | tNET | FF | 1 | n37_s0/I3 |
| 13.144 | 0.625 | tINS | FR | 1 | n37_s0/F |
| 13.507 | 0.363 | tNET | RR | 1 | io_addr_hit_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | LCLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | io_addr_hit_s1/CLK |
| 21.302 | -0.043 | tSu | 1 | io_addr_hit_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 7.501, 61.674%; route: 4.203, 34.558%; tC2Q: 0.458, 3.768% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 4
Path Summary:| Slack | 8.426 |
| Data Arrival Time | 12.519 |
| Data Required Time | 20.945 |
| From | lpc_peri_inst/u_lpc_peri/current_state_2_s0 |
| To | io_addr_hit_s1 |
| Launch Clk | LCLK[R] |
| Latch Clk | LCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | LCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 18 | lpc_peri_inst/u_lpc_peri/current_state_2_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s8/I1 |
| 3.382 | 1.099 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/n423_s8/F |
| 3.862 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s6/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s6/F |
| 5.441 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n423_s2/I1 |
| 6.540 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n423_s2/F |
| 7.020 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/n420_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/n420_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/I3 |
| 8.948 | 0.626 | tINS | FF | 5 | lpc_peri_inst/u_lpc_peri/next_state_3_s2/F |
| 9.428 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/I0 |
| 10.460 | 1.032 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/io_rd_en_d_s/F |
| 10.940 | 0.480 | tNET | FF | 1 | n35_s0/I1 |
| 12.039 | 1.099 | tINS | FF | 2 | n35_s0/F |
| 12.519 | 0.480 | tNET | FF | 1 | io_addr_hit_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | LCLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | io_addr_hit_s1/CLK |
| 20.945 | -0.400 | tSu | 1 | io_addr_hit_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 6.876, 61.534%; route: 3.840, 34.364%; tC2Q: 0.458, 4.102% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
Path 5
Path Summary:| Slack | 8.426 |
| Data Arrival Time | 12.519 |
| Data Required Time | 20.945 |
| From | lpc_peri_inst/u_lpc_peri/current_state_1_s0 |
| To | cnt_WrDelay_2_s0 |
| Launch Clk | LCLK[R] |
| Latch Clk | LCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | LCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 0.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 1.345 | 0.363 | tNET | RR | 1 | lpc_peri_inst/u_lpc_peri/current_state_1_s0/CLK |
| 1.803 | 0.458 | tC2Q | RF | 22 | lpc_peri_inst/u_lpc_peri/current_state_1_s0/Q |
| 2.283 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_2_s7/I1 |
| 3.382 | 1.099 | tINS | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_2_s7/F |
| 3.862 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_2_s6/I1 |
| 4.961 | 1.099 | tINS | FF | 2 | lpc_peri_inst/u_lpc_peri/next_state_2_s6/F |
| 5.441 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_2_s4/I1 |
| 6.540 | 1.099 | tINS | FF | 3 | lpc_peri_inst/u_lpc_peri/next_state_2_s4/F |
| 7.020 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/next_state_2_s1/I2 |
| 7.842 | 0.822 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/next_state_2_s1/F |
| 8.322 | 0.480 | tNET | FF | 1 | lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/I1 |
| 9.421 | 1.099 | tINS | FF | 4 | lpc_peri_inst/u_lpc_peri/io_wr_en_d_s/F |
| 9.901 | 0.480 | tNET | FF | 1 | n66_s3/I0 |
| 10.933 | 1.032 | tINS | FF | 2 | n66_s3/F |
| 11.413 | 0.480 | tNET | FF | 1 | n65_s3/I3 |
| 12.039 | 0.626 | tINS | FF | 1 | n65_s3/F |
| 12.519 | 0.480 | tNET | FF | 1 | cnt_WrDelay_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | LCLK | |||
| 20.000 | 0.000 | tCL | RR | 1 | LCLK_ibuf/I |
| 20.982 | 0.982 | tINS | RR | 35 | LCLK_ibuf/O |
| 21.345 | 0.363 | tNET | RR | 1 | cnt_WrDelay_2_s0/CLK |
| 20.945 | -0.400 | tSu | 1 | cnt_WrDelay_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |
| Arrival Data Path Delay: | cell: 6.876, 61.534%; route: 3.840, 34.364%; tC2Q: 0.458, 4.102% |
| Required Clock Path Delay: | cell: 0.982, 73.009%; route: 0.363, 26.991% |