Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\4_32_4_8_8\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\4_32_4_8_8\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\4_32_4_8_8\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 11:11:23 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	7421
Numbers of Endpoints Analyzed	7931
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	180.491(MHz)	8	TOP
2	tck_pad_i	20.000(MHz)	67.930(MHz)	7	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.360	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	1.209
2	2.797	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.772
3	4.399	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.310
4	4.460	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.505
5	4.495	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_31_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.470
6	4.530	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.435
7	4.565	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_29_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.400
8	4.600	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_28_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.365
9	4.636	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_27_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.329
10	4.671	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_26_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.294
11	4.706	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_25_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.259
12	4.741	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_24_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.224
13	4.776	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_23_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.189
14	4.784	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.925
15	4.792	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.917
16	4.812	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.153
17	4.813	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.896
18	4.813	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.896
19	4.846	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.863
20	4.846	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.863
21	4.847	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_21_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.118
22	4.857	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.852
23	4.877	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.832
24	4.882	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_20_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.083
25	4.906	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.804

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
5	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
6	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
7	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
8	0.239	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.488
9	0.239	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.488
10	0.242	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.491
11	0.242	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.491
12	0.242	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]	clk:[R]	clk:[R]	0.000	0.000	0.491
13	0.242	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.491
14	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_29_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
15	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_30_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
16	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_31_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
17	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_32_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
18	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_33_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
19	0.324	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_34_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
20	0.359	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[17]	clk:[R]	clk:[R]	0.000	0.000	0.608
21	0.359	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[16]	clk:[R]	clk:[R]	0.000	0.000	0.608
22	0.365	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[13]	clk:[R]	clk:[R]	0.000	0.000	0.483
23	0.365	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[13]	clk:[R]	clk:[R]	0.000	0.000	0.483
24	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_117_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.624
25	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_108_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[17]	clk:[R]	clk:[R]	0.000	0.000	0.624

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.183	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.759
2	3.183	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.759
3	3.183	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.759
4	3.183	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.759
5	3.183	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.759
6	3.187	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.755
7	3.187	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.755
8	3.192	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.750
9	3.192	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.750
10	3.192	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.750
11	3.317	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.625
12	3.339	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	1.603
13	3.339	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.603
14	3.339	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.603
15	3.378	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.564
16	3.378	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.564
17	3.438	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.504
18	3.438	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.504
19	3.460	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.482
20	3.460	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.482
21	3.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.333
22	3.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.333
23	3.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	5.000	0.023	1.333
24	3.686	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.256
25	3.686	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.256

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.343	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.341
2	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
3	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
4	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
5	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
6	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
7	5.474	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.473
8	5.474	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.473
9	5.474	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.473
10	5.486	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.485
11	5.486	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.485
12	5.486	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.485
13	5.607	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.606
14	5.607	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.606
15	5.607	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.606
16	5.607	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.606
17	5.607	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.606
18	5.616	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.615
19	5.616	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.615
20	5.765	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.764
21	5.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.777
22	5.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.777
23	5.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-5.000	0.012	0.777
24	5.793	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.792
25	5.793	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.792

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_11_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_9_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_5_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	cnt_1_s0
5	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_9_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_15_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/buff_delay[1]_3_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.360
Data Arrival Time	28.496
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R33C42[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R33C42[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.496	0.977	tNET	FF	1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.977, 80.815%; tC2Q: 0.232, 19.185%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.797
Data Arrival Time	28.059
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R39C43[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R39C43[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.059	0.540	tNET	FF	1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.540, 69.961%; tC2Q: 0.232, 30.039%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	4.399
Data Arrival Time	6.457
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/CLK
2.379	0.232	tC2Q	RF	3	R25C37[1][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_3_s0/Q
3.469	1.090	tNET	FF	1	R20C40[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I3
3.986	0.517	tINS	FF	1	R20C40[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
4.399	0.413	tNET	FF	1	R21C39[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
4.770	0.371	tINS	FF	3	R21C39[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.272	0.501	tNET	FF	1	R21C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
5.734	0.462	tINS	FR	1	R21C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
6.457	0.724	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
10.856	-0.035	tSu		1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.350, 31.321%; route: 2.728, 63.297%; tC2Q: 0.232, 5.382%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.460
Data Arrival Time	6.431
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.820	0.035	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
5.820	0.000	tNET	FF	2	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
5.856	0.035	tINS	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/COUT
5.856	0.000	tNET	FF	2	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/CIN
5.891	0.035	tINS	FF	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/COUT
5.891	0.000	tNET	FF	2	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/CIN
5.926	0.035	tINS	FF	1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/COUT
5.926	0.000	tNET	FF	2	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n114_s/CIN
5.961	0.035	tINS	FF	1	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n114_s/COUT
5.961	0.000	tNET	FF	2	R30C34[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/CIN
6.431	0.470	tINS	FF	1	R30C34[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/SUM
6.431	0.000	tNET	FF	1	R30C34[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C34[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0/CLK
10.891	-0.035	tSu		1	R30C34[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.828, 51.371%; route: 2.445, 44.415%; tC2Q: 0.232, 4.214%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.495
Data Arrival Time	6.396
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_31_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.820	0.035	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
5.820	0.000	tNET	FF	2	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
5.856	0.035	tINS	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/COUT
5.856	0.000	tNET	FF	2	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/CIN
5.891	0.035	tINS	FF	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/COUT
5.891	0.000	tNET	FF	2	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/CIN
5.926	0.035	tINS	FF	1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/COUT
5.926	0.000	tNET	FF	2	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n114_s/CIN
6.396	0.470	tINS	FF	1	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n114_s/SUM
6.396	0.000	tNET	FF	1	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_31_s0/CLK
10.891	-0.035	tSu		1	R30C34[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_31_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.793, 51.058%; route: 2.445, 44.701%; tC2Q: 0.232, 4.241%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.530
Data Arrival Time	6.361
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.820	0.035	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
5.820	0.000	tNET	FF	2	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
5.856	0.035	tINS	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/COUT
5.856	0.000	tNET	FF	2	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/CIN
5.891	0.035	tINS	FF	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/COUT
5.891	0.000	tNET	FF	2	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/CIN
6.361	0.470	tINS	FF	1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n115_s/SUM
6.361	0.000	tNET	FF	1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0/CLK
10.891	-0.035	tSu		1	R30C34[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.758, 50.741%; route: 2.445, 44.990%; tC2Q: 0.232, 4.269%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.565
Data Arrival Time	6.326
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.820	0.035	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
5.820	0.000	tNET	FF	2	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
5.856	0.035	tINS	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/COUT
5.856	0.000	tNET	FF	2	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/CIN
6.326	0.470	tINS	FF	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n116_s/SUM
6.326	0.000	tNET	FF	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_29_s0/CLK
10.891	-0.035	tSu		1	R30C34[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_29_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.723, 50.420%; route: 2.445, 45.284%; tC2Q: 0.232, 4.296%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.600
Data Arrival Time	6.290
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_28_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.820	0.035	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
5.820	0.000	tNET	FF	2	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
6.290	0.470	tINS	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/SUM
6.290	0.000	tNET	FF	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_28_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_28_s0/CLK
10.891	-0.035	tSu		1	R30C33[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_28_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.687, 50.095%; route: 2.445, 45.581%; tC2Q: 0.232, 4.325%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.636
Data Arrival Time	6.255
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_27_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.785	0.035	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
5.785	0.000	tNET	FF	2	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
6.255	0.470	tINS	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/SUM
6.255	0.000	tNET	FF	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_27_s0/CLK
10.891	-0.035	tSu		1	R30C33[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_27_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.652, 49.765%; route: 2.445, 45.882%; tC2Q: 0.232, 4.353%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.671
Data Arrival Time	6.220
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_26_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
5.750	0.035	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
5.750	0.000	tNET	FF	2	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
6.220	0.470	tINS	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/SUM
6.220	0.000	tNET	FF	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_26_s0/CLK
10.891	-0.035	tSu		1	R30C33[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_26_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.617, 49.431%; route: 2.445, 46.187%; tC2Q: 0.232, 4.382%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.706
Data Arrival Time	6.185
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
5.715	0.035	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
5.715	0.000	tNET	FF	2	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
6.185	0.470	tINS	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/SUM
6.185	0.000	tNET	FF	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_25_s0/CLK
10.891	-0.035	tSu		1	R30C33[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_25_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.582, 49.092%; route: 2.445, 46.496%; tC2Q: 0.232, 4.411%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.741
Data Arrival Time	6.150
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
5.680	0.035	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
5.680	0.000	tNET	FF	2	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
6.150	0.470	tINS	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/SUM
6.150	0.000	tNET	FF	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_24_s0/CLK
10.891	-0.035	tSu		1	R30C33[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.547, 48.749%; route: 2.445, 46.809%; tC2Q: 0.232, 4.441%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.776
Data Arrival Time	6.114
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
5.644	0.035	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
5.644	0.000	tNET	FF	2	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
6.114	0.470	tINS	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/SUM
6.114	0.000	tNET	FF	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_23_s0/CLK
10.891	-0.035	tSu		1	R30C33[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.511, 48.402%; route: 2.445, 47.127%; tC2Q: 0.232, 4.471%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.784
Data Arrival Time	6.072
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.523	0.576	tNET	FF	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n740_s1/I3
6.072	0.549	tINS	FR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n740_s1/F
6.072	0.000	tNET	RR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
10.856	-0.035	tSu		1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.112, 53.810%; route: 1.582, 40.304%; tC2Q: 0.231, 5.886%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.792
Data Arrival Time	6.064
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.494	0.548	tNET	FF	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s1/I2
6.064	0.570	tINS	FR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s1/F
6.064	0.000	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
10.856	-0.035	tSu		1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.133, 54.452%; route: 1.553, 39.651%; tC2Q: 0.231, 5.897%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	4.812
Data Arrival Time	6.079
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
5.609	0.035	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
5.609	0.000	tNET	FF	2	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
6.079	0.470	tINS	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/SUM
6.079	0.000	tNET	FF	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/CLK
10.891	-0.035	tSu		1	R30C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	7
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.476, 48.049%; route: 2.445, 47.449%; tC2Q: 0.232, 4.502%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	4.813
Data Arrival Time	6.043
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.494	0.548	tNET	FF	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n744_s1/I2
6.043	0.549	tINS	FR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n744_s1/F
6.043	0.000	tNET	RR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10.856	-0.035	tSu		1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.112, 54.206%; route: 1.553, 39.865%; tC2Q: 0.231, 5.929%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	4.813
Data Arrival Time	6.043
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.494	0.548	tNET	FF	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n743_s1/I3
6.043	0.549	tINS	FR	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n743_s1/F
6.043	0.000	tNET	RR	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.112, 54.206%; route: 1.553, 39.865%; tC2Q: 0.231, 5.929%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	4.846
Data Arrival Time	6.010
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.461	0.514	tNET	FF	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n742_s1/I2
6.010	0.549	tINS	FR	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n742_s1/F
6.010	0.000	tNET	RR	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.856	-0.035	tSu		1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.112, 54.670%; route: 1.520, 39.351%; tC2Q: 0.231, 5.980%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	4.846
Data Arrival Time	6.010
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.461	0.514	tNET	FF	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n741_s1/I3
6.010	0.549	tINS	FR	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n741_s1/F
6.010	0.000	tNET	RR	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.856	-0.035	tSu		1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.112, 54.670%; route: 1.520, 39.351%; tC2Q: 0.231, 5.980%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	4.847
Data Arrival Time	6.044
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
5.574	0.035	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
5.574	0.000	tNET	FF	2	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
6.044	0.470	tINS	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/SUM
6.044	0.000	tNET	FF	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_21_s0/CLK
10.891	-0.035	tSu		1	R30C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.441, 47.692%; route: 2.445, 47.775%; tC2Q: 0.232, 4.533%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	4.857
Data Arrival Time	5.999
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R24C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R24C40[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
3.413	1.034	tNET	FF	2	R36C43[0][B]	gw_gao_inst_0/u_la0_top/n4137_s0/I1
3.983	0.570	tINS	FR	1	R36C43[0][B]	gw_gao_inst_0/u_la0_top/n4137_s0/COUT
3.983	0.000	tNET	RR	2	R36C43[1][A]	gw_gao_inst_0/u_la0_top/n4138_s0/CIN
4.018	0.035	tINS	RF	1	R36C43[1][A]	gw_gao_inst_0/u_la0_top/n4138_s0/COUT
4.018	0.000	tNET	FF	2	R36C43[1][B]	gw_gao_inst_0/u_la0_top/n4139_s0/CIN
4.053	0.035	tINS	FF	1	R36C43[1][B]	gw_gao_inst_0/u_la0_top/n4139_s0/COUT
4.053	0.000	tNET	FF	2	R36C43[2][A]	gw_gao_inst_0/u_la0_top/n4140_s0/CIN
4.088	0.035	tINS	FF	5	R36C43[2][A]	gw_gao_inst_0/u_la0_top/n4140_s0/COUT
4.571	0.483	tNET	FF	1	R36C43[3][B]	gw_gao_inst_0/u_la0_top/n4182_s1/I0
5.120	0.549	tINS	FR	1	R36C43[3][B]	gw_gao_inst_0/u_la0_top/n4182_s1/F
5.122	0.001	tNET	RR	1	R36C43[3][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.671	0.549	tINS	RR	1	R36C43[3][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
5.999	0.328	tNET	RR	1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.774, 46.046%; route: 1.846, 47.930%; tC2Q: 0.232, 6.023%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	4.877
Data Arrival Time	5.979
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.373	0.426	tNET	FF	1	R21C43[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
5.835	0.462	tINS	FR	1	R21C43[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
5.979	0.144	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.856	-0.035	tSu		1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.025, 52.841%; route: 1.576, 41.131%; tC2Q: 0.231, 6.028%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	4.882
Data Arrival Time	6.009
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	21	R27C35[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
2.049	0.891	tNET	FF	4	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[1](chk_dup)
2.566	0.517	tINS	FF	1	R23C34	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/DO[1]
3.221	0.656	tNET	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/I1
3.776	0.555	tINS	FF	1	R27C33[3][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_5_s3/F
4.675	0.899	tNET	FF	2	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/I1
5.046	0.371	tINS	FF	1	R30C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n140_s/COUT
5.046	0.000	tNET	FF	2	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/CIN
5.081	0.035	tINS	FF	1	R30C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n139_s/COUT
5.081	0.000	tNET	FF	2	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/CIN
5.116	0.035	tINS	FF	1	R30C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n138_s/COUT
5.116	0.000	tNET	FF	2	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/CIN
5.152	0.035	tINS	FF	1	R30C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n137_s/COUT
5.152	0.000	tNET	FF	2	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/CIN
5.187	0.035	tINS	FF	1	R30C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n136_s/COUT
5.187	0.000	tNET	FF	2	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/CIN
5.222	0.035	tINS	FF	1	R30C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n135_s/COUT
5.222	0.000	tNET	FF	2	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/CIN
5.257	0.035	tINS	FF	1	R30C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n134_s/COUT
5.257	0.000	tNET	FF	2	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/CIN
5.292	0.035	tINS	FF	1	R30C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n133_s/COUT
5.292	0.000	tNET	FF	2	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/CIN
5.328	0.035	tINS	FF	1	R30C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n132_s/COUT
5.328	0.000	tNET	FF	2	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/CIN
5.363	0.035	tINS	FF	1	R30C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n131_s/COUT
5.363	0.000	tNET	FF	2	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/CIN
5.398	0.035	tINS	FF	1	R30C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n130_s/COUT
5.398	0.000	tNET	FF	2	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/CIN
5.433	0.035	tINS	FF	1	R30C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n129_s/COUT
5.433	0.000	tNET	FF	2	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/CIN
5.468	0.035	tINS	FF	1	R30C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n128_s/COUT
5.468	0.000	tNET	FF	2	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/CIN
5.504	0.035	tINS	FF	1	R30C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n127_s/COUT
5.504	0.000	tNET	FF	2	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/CIN
5.539	0.035	tINS	FF	1	R30C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n126_s/COUT
5.539	0.000	tNET	FF	2	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/CIN
6.009	0.470	tINS	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/SUM
6.009	0.000	tNET	FF	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_20_s0/CLK
10.891	-0.035	tSu		1	R30C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.406, 47.330%; route: 2.445, 48.106%; tC2Q: 0.232, 4.564%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	4.906
Data Arrival Time	5.950
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	485	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
2.378	0.231	tC2Q	RR	2	R23C38[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
2.551	0.174	tNET	RR	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/I2
3.106	0.555	tINS	RF	1	R23C39[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s9/F
3.520	0.413	tNET	FF	1	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/I1
3.973	0.453	tINS	FF	2	R22C41[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s6/F
4.391	0.419	tNET	FF	1	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/I0
4.946	0.555	tINS	FF	10	R20C42[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n739_s4/F
5.488	0.542	tNET	FF	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n747_s1/I2
5.950	0.462	tINS	FR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n747_s1/F
5.950	0.000	tNET	RR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.856	-0.035	tSu		1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.025, 53.240%; route: 1.548, 40.686%; tC2Q: 0.231, 6.073%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	14	R21C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.239
Data Arrival Time	1.347
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.347	0.286	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.286, 58.574%; tC2Q: 0.202, 41.426%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.239
Data Arrival Time	1.347
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.347	0.286	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.286, 58.574%; tC2Q: 0.202, 41.426%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.242
Data Arrival Time	1.350
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.350	0.289	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.828%; tC2Q: 0.202, 41.172%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.242
Data Arrival Time	1.350
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.350	0.289	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.828%; tC2Q: 0.202, 41.172%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.242
Data Arrival Time	1.350
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.350	0.289	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.828%; tC2Q: 0.202, 41.172%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.242
Data Arrival Time	1.350
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.350	0.289	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.289, 58.828%; tC2Q: 0.202, 41.172%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_29_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_29_s0/CLK
0.871	0.011	tHld		1	R18C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_29_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_30_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_30_s0/CLK
0.871	0.011	tHld		1	R18C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_30_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_31_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_31_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_31_s0/CLK
0.871	0.011	tHld		1	R18C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_31_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_32_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_32_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_32_s0/CLK
0.871	0.011	tHld		1	R18C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_32_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_33_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_33_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_33_s0/CLK
0.871	0.011	tHld		1	R18C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_33_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	70	R20C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R18C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_34_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_34_s0/CLK
0.871	0.011	tHld		1	R18C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_34_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.781%; tC2Q: 0.202, 60.219%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.359
Data Arrival Time	1.467
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.467	0.406	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.754%; tC2Q: 0.202, 33.246%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.359
Data Arrival Time	1.467
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/CLK
1.062	0.202	tC2Q	RR	31	R18C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_100_s0/Q
1.467	0.406	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.754%; tC2Q: 0.202, 33.246%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.365
Data Arrival Time	1.342
Data Required Time	0.978
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.062	0.202	tC2Q	RR	9	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.342	0.281	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/ADA[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.978	0.118	tHld		1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.281, 58.148%; tC2Q: 0.202, 41.852%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.365
Data Arrival Time	1.342
Data Required Time	0.978
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
1.062	0.202	tC2Q	RR	9	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/Q
1.342	0.281	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.978	0.118	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.281, 58.148%; tC2Q: 0.202, 41.852%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_117_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_117_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_117_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_108_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_108_s0/CLK
1.062	0.202	tC2Q	RR	1	R18C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_108_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.183
Data Arrival Time	7.708
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.708	1.527	tNET	FF	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tSu		1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.527, 86.809%; tC2Q: 0.232, 13.191%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.183
Data Arrival Time	7.708
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.708	1.527	tNET	FF	1	R18C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tSu		1	R18C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.527, 86.809%; tC2Q: 0.232, 13.191%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.183
Data Arrival Time	7.708
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.708	1.527	tNET	FF	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tSu		1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.527, 86.809%; tC2Q: 0.232, 13.191%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.183
Data Arrival Time	7.708
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.708	1.527	tNET	FF	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tSu		1	R18C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.527, 86.809%; tC2Q: 0.232, 13.191%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.183
Data Arrival Time	7.708
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.708	1.527	tNET	FF	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tSu		1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.527, 86.809%; tC2Q: 0.232, 13.191%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.187
Data Arrival Time	7.704
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.704	1.523	tNET	FF	1	R18C42[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C42[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R18C42[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.523, 86.779%; tC2Q: 0.232, 13.221%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.187
Data Arrival Time	7.704
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.704	1.523	tNET	FF	1	R18C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.891	-0.035	tSu		1	R18C42[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.523, 86.779%; tC2Q: 0.232, 13.221%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.192
Data Arrival Time	7.699
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.699	1.518	tNET	FF	1	R18C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
10.891	-0.035	tSu		1	R18C41[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.518, 86.742%; tC2Q: 0.232, 13.258%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.192
Data Arrival Time	7.699
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.699	1.518	tNET	FF	1	R18C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.891	-0.035	tSu		1	R18C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.518, 86.742%; tC2Q: 0.232, 13.258%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.192
Data Arrival Time	7.699
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.699	1.518	tNET	FF	1	R18C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.891	-0.035	tSu		1	R18C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.518, 86.742%; tC2Q: 0.232, 13.258%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.317
Data Arrival Time	7.574
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.574	1.393	tNET	FF	1	R20C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
10.891	-0.035	tSu		1	R20C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.393, 85.725%; tC2Q: 0.232, 14.275%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.339
Data Arrival Time	7.552
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.552	1.371	tNET	FF	1	R20C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R20C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.371, 85.525%; tC2Q: 0.232, 14.475%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.339
Data Arrival Time	7.552
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.552	1.371	tNET	FF	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.891	-0.035	tSu		1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.371, 85.525%; tC2Q: 0.232, 14.475%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	3.339
Data Arrival Time	7.552
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.552	1.371	tNET	FF	1	R20C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.891	-0.035	tSu		1	R20C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.371, 85.525%; tC2Q: 0.232, 14.475%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	3.378
Data Arrival Time	7.513
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.513	1.332	tNET	FF	1	R20C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.891	-0.035	tSu		1	R20C41[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.332, 85.166%; tC2Q: 0.232, 14.834%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	3.378
Data Arrival Time	7.513
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.513	1.332	tNET	FF	1	R20C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
10.891	-0.035	tSu		1	R20C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.332, 85.166%; tC2Q: 0.232, 14.834%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	3.438
Data Arrival Time	7.453
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.453	1.272	tNET	FF	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tSu		1	R18C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.272, 84.576%; tC2Q: 0.232, 15.424%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	3.438
Data Arrival Time	7.453
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.453	1.272	tNET	FF	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tSu		1	R18C43[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.272, 84.576%; tC2Q: 0.232, 15.424%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	3.460
Data Arrival Time	7.431
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.431	1.250	tNET	FF	1	R20C42[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C42[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tSu		1	R20C42[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.250, 84.347%; tC2Q: 0.232, 15.653%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	3.460
Data Arrival Time	7.431
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.431	1.250	tNET	FF	1	R20C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
10.891	-0.035	tSu		1	R20C42[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.250, 84.347%; tC2Q: 0.232, 15.653%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	3.609
Data Arrival Time	7.282
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.282	1.101	tNET	FF	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tSu		1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.101, 82.592%; tC2Q: 0.232, 17.408%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	3.609
Data Arrival Time	7.282
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.282	1.101	tNET	FF	1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
10.891	-0.035	tSu		1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.101, 82.592%; tC2Q: 0.232, 17.408%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	3.609
Data Arrival Time	7.282
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.282	1.101	tNET	FF	1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
10.891	-0.035	tSu		1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.101, 82.592%; tC2Q: 0.232, 17.408%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	3.686
Data Arrival Time	7.205
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.205	1.024	tNET	FF	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tSu		1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.024, 81.530%; tC2Q: 0.232, 18.470%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	3.686
Data Arrival Time	7.205
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.205	1.024	tNET	FF	1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	2060	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tSu		1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.024, 81.530%; tC2Q: 0.232, 18.470%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.343
Data Arrival Time	6.214
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.214	0.139	tNET	RR	1	R40C43[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C43[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R40C43[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.139, 40.848%; tC2Q: 0.202, 59.152%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R38C43[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C43[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871	0.011	tHld		1	R38C43[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.880%; tC2Q: 0.202, 43.120%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R38C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871	0.011	tHld		1	R38C43[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.880%; tC2Q: 0.202, 43.120%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R38C43[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C43[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871	0.011	tHld		1	R38C43[2][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.880%; tC2Q: 0.202, 43.120%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R38C43[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C43[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R38C43[0][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.880%; tC2Q: 0.202, 43.120%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.871	0.011	tHld		1	R38C43[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.880%; tC2Q: 0.202, 43.120%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.474
Data Arrival Time	6.345
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.345	0.271	tNET	RR	1	R38C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R38C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.269%; tC2Q: 0.202, 42.731%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.474
Data Arrival Time	6.345
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.345	0.271	tNET	RR	1	R38C42[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C42[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R38C42[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.269%; tC2Q: 0.202, 42.731%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.474
Data Arrival Time	6.345
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.345	0.271	tNET	RR	1	R38C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.871	0.011	tHld		1	R38C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.271, 57.269%; tC2Q: 0.202, 42.731%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.486
Data Arrival Time	6.357
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.357	0.283	tNET	RR	1	R36C42[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C42[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871	0.011	tHld		1	R36C42[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.334%; tC2Q: 0.202, 41.666%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.486
Data Arrival Time	6.357
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.357	0.283	tNET	RR	1	R36C42[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C42[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
0.871	0.011	tHld		1	R36C42[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.334%; tC2Q: 0.202, 41.666%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.486
Data Arrival Time	6.357
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.357	0.283	tNET	RR	1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R36C42[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.334%; tC2Q: 0.202, 41.666%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.607
Data Arrival Time	6.478
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.478	0.404	tNET	RR	1	R40C42[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C42[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R40C42[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.404, 66.646%; tC2Q: 0.202, 33.354%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.607
Data Arrival Time	6.478
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.478	0.404	tNET	RR	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R40C42[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.404, 66.646%; tC2Q: 0.202, 33.354%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.607
Data Arrival Time	6.478
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.478	0.404	tNET	RR	1	R40C42[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C42[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R40C42[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.404, 66.646%; tC2Q: 0.202, 33.354%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.607
Data Arrival Time	6.478
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.478	0.404	tNET	RR	1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R40C42[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.404, 66.646%; tC2Q: 0.202, 33.354%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.607
Data Arrival Time	6.478
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.478	0.404	tNET	RR	1	R40C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R40C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R40C42[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.404, 66.646%; tC2Q: 0.202, 33.354%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.616
Data Arrival Time	6.487
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.487	0.413	tNET	RR	1	R33C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.871	0.011	tHld		1	R33C43[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.413, 67.130%; tC2Q: 0.202, 32.870%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.616
Data Arrival Time	6.487
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.487	0.413	tNET	RR	1	R30C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.871	0.011	tHld		1	R30C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.413, 67.130%; tC2Q: 0.202, 32.870%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.765
Data Arrival Time	6.636
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.636	0.562	tNET	RR	1	R30C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871	0.011	tHld		1	R30C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.562, 73.553%; tC2Q: 0.202, 26.447%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.778
Data Arrival Time	6.649
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.649	0.575	tNET	RR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.871	0.011	tHld		1	R20C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.575, 74.006%; tC2Q: 0.202, 25.994%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.778
Data Arrival Time	6.649
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.649	0.575	tNET	RR	1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
0.871	0.011	tHld		1	R20C43[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.575, 74.006%; tC2Q: 0.202, 25.994%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.778
Data Arrival Time	6.649
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.649	0.575	tNET	RR	1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
0.871	0.011	tHld		1	R20C43[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.575, 74.006%; tC2Q: 0.202, 25.994%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.793
Data Arrival Time	6.664
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.664	0.590	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871	0.011	tHld		1	R21C43[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 74.503%; tC2Q: 0.202, 25.497%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.793
Data Arrival Time	6.664
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	2060	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R40C43[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.664	0.590	tNET	RR	1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	2060	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
0.871	0.011	tHld		1	R21C43[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.590, 74.503%; tC2Q: 0.202, 25.497%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_11_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_9_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_5_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	cnt_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	cnt_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	cnt_1_s0/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_30_s0/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_68_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_9_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_15_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/buff_delay[1]_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/buff_delay[1]_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/buff_delay[1]_3_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
2060	clk_d	3.183	0.261
485	control0[0]	2.360	0.912
197	comb_vaild_5[6]	8.256	1.477
192	comb_vaild_4[5]	7.586	2.147
187	comb_vaild_3[4]	8.127	1.606
182	comb_vaild_2[3]	7.586	2.147
177	comb_vaild_1[2]	7.752	1.981
172	comb_vaild_0[1]	7.521	2.212
167	comb_vaild[0]	7.614	2.119
141	n20_3	46.627	1.370

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R29C39	90.28%
R22C41	88.89%
R18C40	88.89%
R29C36	88.89%
R20C29	87.50%
R20C30	87.50%
R29C38	87.50%
R21C41	86.11%
R22C38	86.11%
R22C39	86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]