Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\src\cic_filter.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\src\cic_filter\cic_filter.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Fri Jul 15 10:53:31 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | cic_filter |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.779s, Peak memory usage = 127.164MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.093s, Peak memory usage = 127.164MB Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 127.164MB Optimizing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.138s, Peak memory usage = 127.164MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 127.164MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 127.164MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 127.164MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 127.164MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.095s, Peak memory usage = 127.164MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 127.164MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 127.164MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 135.941MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.101s, Peak memory usage = 135.941MB Generate output files: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.497s, Peak memory usage = 145.875MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 145.875MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 67 |
| I/O Buf | 67 |
| IBUF | 5 |
| OBUF | 62 |
| Register | 1290 |
| DFF | 27 |
| DFFE | 2 |
| DFFP | 1 |
| DFFPE | 38 |
| DFFC | 86 |
| DFFCE | 1125 |
| DFFNP | 2 |
| DFFNC | 7 |
| DFFNCE | 2 |
| LUT | 499 |
| LUT2 | 70 |
| LUT3 | 133 |
| LUT4 | 296 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 529 |
| ALU | 529 |
| SSRAM | 21 |
| RAM16S4 | 21 |
| INV | 6 |
| INV | 6 |
| BSRAM | 6 |
| SDPX9B | 5 |
| pROMX9 | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 1168(513 LUTs, 529 ALUs, 21 SSRAMs) / 20736 | 6% |
| Register | 1290 / 16173 | 8% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1290 / 16173 | 8% |
| BSRAM | 6 / 46 | 13% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 234.7(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.740 |
| Data Arrival Time | 5.088 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 10 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n554_s2/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n554_s2/F |
| 2.124 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n552_s2/I2 |
| 2.577 | 0.453 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n552_s2/F |
| 2.814 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n550_s3/I2 |
| 3.267 | 0.453 | tINS | FF | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n550_s3/F |
| 3.504 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s3/I1 |
| 4.059 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s3/F |
| 4.296 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s1/I1 |
| 4.851 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s1/F |
| 5.088 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.571, 60.852%; route: 1.422, 33.657%; tC2Q: 0.232, 5.491% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 5.740 |
| Data Arrival Time | 5.088 |
| Data Required Time | 10.828 |
| From | cnt_5_s0 |
| To | i_data_8_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | cnt_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | cnt_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | n188_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | n188_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | n207_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 4 | n207_s1/F |
| 2.916 | 0.237 | tNET | FF | 1 | n205_s1/I2 |
| 3.369 | 0.453 | tINS | FF | 3 | n205_s1/F |
| 3.606 | 0.237 | tNET | FF | 1 | n201_s1/I2 |
| 4.059 | 0.453 | tINS | FF | 3 | n201_s1/F |
| 4.296 | 0.237 | tNET | FF | 1 | n203_s0/I1 |
| 4.851 | 0.555 | tINS | FF | 1 | n203_s0/F |
| 5.088 | 0.237 | tNET | FF | 1 | i_data_8_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | i_data_8_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | i_data_8_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.571, 60.852%; route: 1.422, 33.657%; tC2Q: 0.232, 5.491% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 5.740 |
| Data Arrival Time | 5.088 |
| Data Required Time | 10.828 |
| From | cnt_5_s0 |
| To | i_data_10_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | cnt_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | cnt_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | n188_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | n188_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | n207_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 4 | n207_s1/F |
| 2.916 | 0.237 | tNET | FF | 1 | n205_s1/I2 |
| 3.369 | 0.453 | tINS | FF | 3 | n205_s1/F |
| 3.606 | 0.237 | tNET | FF | 1 | n201_s1/I2 |
| 4.059 | 0.453 | tINS | FF | 3 | n201_s1/F |
| 4.296 | 0.237 | tNET | FF | 1 | n201_s0/I1 |
| 4.851 | 0.555 | tINS | FF | 1 | n201_s0/F |
| 5.088 | 0.237 | tNET | FF | 1 | i_data_10_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | i_data_10_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | i_data_10_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.571, 60.852%; route: 1.422, 33.657%; tC2Q: 0.232, 5.491% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 5.778 |
| Data Arrival Time | 5.050 |
| Data Required Time | 10.828 |
| From | cnt_5_s0 |
| To | i_data_9_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | cnt_5_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | cnt_5_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | n188_s3/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | n188_s3/F |
| 2.124 | 0.237 | tNET | FF | 1 | n207_s1/I1 |
| 2.679 | 0.555 | tINS | FF | 4 | n207_s1/F |
| 2.916 | 0.237 | tNET | FF | 1 | n205_s1/I2 |
| 3.369 | 0.453 | tINS | FF | 3 | n205_s1/F |
| 3.606 | 0.237 | tNET | FF | 1 | n201_s1/I2 |
| 4.059 | 0.453 | tINS | FF | 3 | n201_s1/F |
| 4.296 | 0.237 | tNET | FF | 1 | n202_s1/I0 |
| 4.813 | 0.517 | tINS | FF | 1 | n202_s1/F |
| 5.050 | 0.237 | tNET | FF | 1 | i_data_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | i_data_9_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | i_data_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.533, 60.497%; route: 1.422, 33.962%; tC2Q: 0.232, 5.541% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.213 |
| Data Arrival Time | 4.615 |
| Data Required Time | 10.828 |
| From | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_0_s0 |
| To | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_58_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 3 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n67_s/I1 |
| 1.901 | 0.570 | tINS | FR | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n67_s/COUT |
| 1.901 | 0.000 | tNET | RR | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n66_s/CIN |
| 1.937 | 0.035 | tINS | RF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n66_s/COUT |
| 1.937 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n65_s/CIN |
| 1.972 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n65_s/COUT |
| 1.972 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n64_s/CIN |
| 2.007 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n64_s/COUT |
| 2.007 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n63_s/CIN |
| 2.042 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n63_s/COUT |
| 2.042 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n62_s/CIN |
| 2.078 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n62_s/COUT |
| 2.078 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n61_s/CIN |
| 2.113 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n61_s/COUT |
| 2.113 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n60_s/CIN |
| 2.148 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n60_s/COUT |
| 2.148 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n59_s/CIN |
| 2.183 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n59_s/COUT |
| 2.183 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n58_s/CIN |
| 2.218 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n58_s/COUT |
| 2.218 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n57_s/CIN |
| 2.254 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n57_s/COUT |
| 2.254 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n56_s/CIN |
| 2.289 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n56_s/COUT |
| 2.289 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n55_s/CIN |
| 2.324 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n55_s/COUT |
| 2.324 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n54_s/CIN |
| 2.359 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n54_s/COUT |
| 2.359 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n53_s/CIN |
| 2.394 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n53_s/COUT |
| 2.394 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n52_s/CIN |
| 2.430 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n52_s/COUT |
| 2.430 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n51_s/CIN |
| 2.465 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n51_s/COUT |
| 2.465 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n50_s/CIN |
| 2.500 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n50_s/COUT |
| 2.500 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n49_s/CIN |
| 2.535 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n49_s/COUT |
| 2.535 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n48_s/CIN |
| 2.570 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n48_s/COUT |
| 2.570 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n47_s/CIN |
| 2.606 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n47_s/COUT |
| 2.606 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n46_s/CIN |
| 2.641 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n46_s/COUT |
| 2.641 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n45_s/CIN |
| 2.676 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n45_s/COUT |
| 2.676 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n44_s/CIN |
| 2.711 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n44_s/COUT |
| 2.711 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n43_s/CIN |
| 2.746 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n43_s/COUT |
| 2.746 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n42_s/CIN |
| 2.782 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n42_s/COUT |
| 2.782 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n41_s/CIN |
| 2.817 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n41_s/COUT |
| 2.817 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n40_s/CIN |
| 2.852 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n40_s/COUT |
| 2.852 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n39_s/CIN |
| 2.887 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n39_s/COUT |
| 2.887 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n38_s/CIN |
| 2.922 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n38_s/COUT |
| 2.922 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n37_s/CIN |
| 2.958 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n37_s/COUT |
| 2.958 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n36_s/CIN |
| 2.993 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n36_s/COUT |
| 2.993 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n35_s/CIN |
| 3.028 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n35_s/COUT |
| 3.028 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n34_s/CIN |
| 3.063 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n34_s/COUT |
| 3.063 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n33_s/CIN |
| 3.098 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n33_s/COUT |
| 3.098 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n32_s/CIN |
| 3.134 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n32_s/COUT |
| 3.134 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n31_s/CIN |
| 3.169 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n31_s/COUT |
| 3.169 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n30_s/CIN |
| 3.204 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n30_s/COUT |
| 3.204 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n29_s/CIN |
| 3.239 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n29_s/COUT |
| 3.239 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n28_s/CIN |
| 3.274 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n28_s/COUT |
| 3.274 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n27_s/CIN |
| 3.310 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n27_s/COUT |
| 3.310 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n26_s/CIN |
| 3.345 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n26_s/COUT |
| 3.345 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n25_s/CIN |
| 3.380 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n25_s/COUT |
| 3.380 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n24_s/CIN |
| 3.415 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n24_s/COUT |
| 3.415 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n23_s/CIN |
| 3.450 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n23_s/COUT |
| 3.450 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n22_s/CIN |
| 3.486 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n22_s/COUT |
| 3.486 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n21_s/CIN |
| 3.521 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n21_s/COUT |
| 3.521 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n20_s/CIN |
| 3.556 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n20_s/COUT |
| 3.556 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n19_s/CIN |
| 3.591 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n19_s/COUT |
| 3.591 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n18_s/CIN |
| 3.626 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n18_s/COUT |
| 3.626 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n17_s/CIN |
| 3.662 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n17_s/COUT |
| 3.662 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n16_s/CIN |
| 3.697 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n16_s/COUT |
| 3.697 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n15_s/CIN |
| 3.732 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n15_s/COUT |
| 3.732 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n14_s/CIN |
| 3.767 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n14_s/COUT |
| 3.767 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n13_s/CIN |
| 3.802 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n13_s/COUT |
| 3.802 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n12_s/CIN |
| 3.838 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n12_s/COUT |
| 3.838 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n11_s/CIN |
| 3.873 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n11_s/COUT |
| 3.873 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n10_s/CIN |
| 3.908 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n10_s/COUT |
| 3.908 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n9_s/CIN |
| 4.378 | 0.470 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n9_s/SUM |
| 4.615 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_58_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 985 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_58_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_58_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 9 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.046, 81.185%; route: 0.474, 12.632%; tC2Q: 0.232, 6.183% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |