Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 10:29:14 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1972
Numbers of Endpoints Analyzed	2262
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	218.804(MHz)	5	TOP
2	tck_pad_i	20.000(MHz)	97.415(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.175	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	1.394
2	2.554	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	1.015
3	3.997	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.712
4	4.047	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.663
5	4.058	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.651
6	4.068	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.642
7	4.088	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.621
8	4.119	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.590
9	4.242	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.467
10	4.301	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.408
11	4.506	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.203
12	4.506	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.203
13	4.515	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.194
14	4.743	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.966
15	5.083	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.626
16	5.410	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.299
17	5.410	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.299
18	5.487	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.223
19	5.488	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.221
20	5.552	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.157
21	5.591	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.118
22	5.600	mem_data_mem_data_0_0_s/DO[1]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.365
23	5.635	mem_data_mem_data_0_0_s/DO[1]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.330
24	5.671	mem_data_mem_data_0_0_s/DO[1]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.294
25	5.706	mem_data_mem_data_0_0_s/DO[1]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.259

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.324	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[2]_2_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
5	0.324	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_2_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
6	0.324	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_2_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.335
7	0.327	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.339
8	0.330	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/AD[0]	clk:[R]	clk:[R]	0.000	0.000	0.342
9	0.369	gw_gao_inst_0/u_la0_top/triger_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[13]	clk:[R]	clk:[R]	0.000	0.000	0.618
10	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.624
11	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.624
12	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
13	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
14	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
15	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
16	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
17	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
18	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
19	0.425	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
20	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
21	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
22	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
23	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
24	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
25	0.425	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.647	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.295
2	3.647	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.295
3	3.675	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.267
4	3.675	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.267
5	3.771	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.171
6	3.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.164
7	3.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.164
8	3.778	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.164
9	3.800	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.142
10	3.849	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.093
11	3.859	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.083
12	3.912	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.030
13	3.912	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.030
14	4.003	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.939
15	4.003	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.939
16	4.008	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.934
17	4.008	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.934
18	4.014	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.928
19	4.048	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.894
20	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.856
21	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.856
22	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.856
23	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	5.000	0.023	0.856
24	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	0.856
25	4.086	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.856

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.344	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.343
2	5.344	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.343
3	5.344	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.343
4	5.464	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.463
5	5.464	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.463
6	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
7	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
8	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
9	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
10	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
11	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
12	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
13	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
14	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
15	5.471	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.470
16	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
17	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
18	5.487	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.485
19	5.583	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.582
20	5.597	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.595
21	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
22	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
23	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.599
24	5.603	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.601
25	5.603	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.601

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_10_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_8_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_4_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	i_data_9_s1
5	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_2_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_3_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_0_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_1_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.175
Data Arrival Time	28.681
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C29[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R27C29[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.681	1.162	tNET	FF	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.162, 83.358%; tC2Q: 0.232, 16.642%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.554
Data Arrival Time	28.302
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C34[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R27C34[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.302	0.783	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.783, 77.144%; tC2Q: 0.232, 22.856%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.997
Data Arrival Time	6.859
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.397	0.618	tNET	FF	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s1/I2
6.859	0.462	tINS	FR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s1/F
6.859	0.000	tNET	RR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
10.856	-0.035	tSu		1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.127, 45.138%; route: 2.353, 49.939%; tC2Q: 0.232, 4.923%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.047
Data Arrival Time	6.809
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.239	0.460	tNET	FF	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n395_s1/I2
6.809	0.570	tINS	FR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n395_s1/F
6.809	0.000	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
10.856	-0.035	tSu		1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 47.935%; route: 2.196, 47.089%; tC2Q: 0.232, 4.976%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.058
Data Arrival Time	6.798
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.228	0.449	tNET	FF	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n394_s1/I2
6.798	0.570	tINS	FR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n394_s1/F
6.798	0.000	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10.856	-0.035	tSu		1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 48.053%; route: 2.184, 46.959%; tC2Q: 0.232, 4.988%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.068
Data Arrival Time	6.788
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.239	0.460	tNET	FF	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n397_s1/I2
6.788	0.549	tINS	FR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n397_s1/F
6.788	0.000	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.856	-0.035	tSu		1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 47.699%; route: 2.196, 47.302%; tC2Q: 0.232, 4.998%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.088
Data Arrival Time	6.768
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.397	0.618	tNET	FF	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n392_s1/I2
6.768	0.371	tINS	FF	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n392_s1/F
6.768	0.000	tNET	FF	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.856	-0.035	tSu		1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.036, 44.057%; route: 2.353, 50.922%; tC2Q: 0.232, 5.020%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.119
Data Arrival Time	6.737
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.044	0.265	tNET	FF	1	R22C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
6.593	0.549	tINS	FR	1	R22C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
6.737	0.144	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.856	-0.035	tSu		1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 48.233%; route: 2.144, 46.712%; tC2Q: 0.232, 5.054%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.242
Data Arrival Time	6.614
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
6.044	0.265	tNET	FF	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n396_s1/I3
6.614	0.570	tINS	FR	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n396_s1/F
6.614	0.000	tNET	RR	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
10.856	-0.035	tSu		1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 50.034%; route: 2.000, 44.772%; tC2Q: 0.232, 5.194%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.301
Data Arrival Time	6.555
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
5.985	0.206	tNET	FF	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n393_s1/I3
6.555	0.570	tINS	FR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n393_s1/F
6.555	0.000	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 50.699%; route: 1.941, 44.038%; tC2Q: 0.232, 5.263%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.506
Data Arrival Time	6.350
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
5.801	0.022	tNET	FF	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n391_s1/I3
6.350	0.549	tINS	FR	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n391_s1/F
6.350	0.000	tNET	RR	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.856	-0.035	tSu		1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 52.674%; route: 1.757, 41.807%; tC2Q: 0.232, 5.520%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.506
Data Arrival Time	6.350
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0
5.779	0.555	tINS	FF	10	R22C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F
5.801	0.022	tNET	FF	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n390_s1/I3
6.350	0.549	tINS	FR	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n390_s1/F
6.350	0.000	tNET	RR	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
10.856	-0.035	tSu		1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 52.674%; route: 1.757, 41.807%; tC2Q: 0.232, 5.520%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.515
Data Arrival Time	6.341
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK
2.379	0.232	tC2Q	RF	2	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q
2.794	0.415	tNET	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3
3.349	0.555	tINS	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
4.005	0.656	tNET	FF	1	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
4.376	0.371	tINS	FF	3	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
4.799	0.423	tNET	FF	1	R21C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
5.369	0.570	tINS	FR	1	R21C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
6.341	0.971	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
10.856	-0.035	tSu		1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.496, 35.672%; route: 2.466, 58.796%; tC2Q: 0.232, 5.532%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.743
Data Arrival Time	6.113
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
3.142	0.763	tNET	FF	2	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/I1
3.712	0.570	tINS	FR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/COUT
3.712	0.000	tNET	RR	2	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/CIN
3.747	0.035	tINS	RF	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/COUT
3.747	0.000	tNET	FF	2	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/CIN
3.782	0.035	tINS	FF	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/COUT
3.782	0.000	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/CIN
3.817	0.035	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/COUT
4.956	1.139	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/n2285_s1/I0
5.505	0.549	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/n2285_s1/F
5.507	0.001	tNET	RR	1	R24C35[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.969	0.462	tINS	RR	1	R24C35[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
6.113	0.144	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.687, 42.525%; route: 2.048, 51.625%; tC2Q: 0.232, 5.850%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	5.083
Data Arrival Time	5.773
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_14_s0/Q
3.282	0.903	tNET	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/I2
3.837	0.555	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s8/F
4.250	0.413	tNET	FF	1	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I0
4.805	0.555	tINS	FF	2	R24C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F
5.224	0.419	tNET	FF	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n398_s2/I1
5.773	0.549	tINS	FR	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n398_s2/F
5.773	0.000	tNET	RR	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
10.856	-0.035	tSu		1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.659, 45.749%; route: 1.735, 47.853%; tC2Q: 0.232, 6.398%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	5.410
Data Arrival Time	5.446
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
3.142	0.763	tNET	FF	2	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/I1
3.712	0.570	tINS	FR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/COUT
3.712	0.000	tNET	RR	2	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/CIN
3.747	0.035	tINS	RF	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/COUT
3.747	0.000	tNET	FF	2	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/CIN
3.782	0.035	tINS	FF	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/COUT
3.782	0.000	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/CIN
3.817	0.035	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/COUT
4.305	0.488	tNET	FF	1	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2265_s2/I1
4.822	0.517	tINS	FF	2	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2265_s2/F
5.075	0.253	tNET	FF	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/n2263_s3/I3
5.446	0.371	tINS	FF	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/n2263_s3/F
5.446	0.000	tNET	FF	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
10.856	-0.035	tSu		1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.564, 47.398%; route: 1.503, 45.570%; tC2Q: 0.232, 7.033%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	5.410
Data Arrival Time	5.446
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
3.142	0.763	tNET	FF	2	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/I1
3.712	0.570	tINS	FR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/COUT
3.712	0.000	tNET	RR	2	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/CIN
3.747	0.035	tINS	RF	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/COUT
3.747	0.000	tNET	FF	2	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/CIN
3.782	0.035	tINS	FF	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/COUT
3.782	0.000	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/CIN
3.817	0.035	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/COUT
4.305	0.488	tNET	FF	1	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2265_s2/I1
4.822	0.517	tINS	FF	2	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2265_s2/F
5.075	0.253	tNET	FF	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/n2262_s1/I3
5.446	0.371	tINS	FF	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/n2262_s1/F
5.446	0.000	tNET	FF	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
10.856	-0.035	tSu		1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.564, 47.398%; route: 1.503, 45.570%; tC2Q: 0.232, 7.033%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	5.487
Data Arrival Time	5.369
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK
2.379	0.232	tC2Q	RF	2	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q
2.794	0.415	tNET	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3
3.349	0.555	tINS	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
4.005	0.656	tNET	FF	1	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
4.376	0.371	tINS	FF	3	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
4.799	0.423	tNET	FF	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n289_s3/I1
5.369	0.570	tINS	FR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n289_s3/F
5.369	0.000	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.496, 46.424%; route: 1.495, 46.377%; tC2Q: 0.232, 7.199%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	5.488
Data Arrival Time	5.367
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R29C30[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
3.142	0.763	tNET	FF	2	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/I1
3.712	0.570	tINS	FR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/n2240_s0/COUT
3.712	0.000	tNET	RR	2	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/CIN
3.747	0.035	tINS	RF	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/n2241_s0/COUT
3.747	0.000	tNET	FF	2	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/CIN
3.782	0.035	tINS	FF	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/n2242_s0/COUT
3.782	0.000	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/CIN
3.817	0.035	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n2243_s0/COUT
4.818	1.001	tNET	FF	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/n2285_s2/I1
5.367	0.549	tINS	FR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/n2285_s2/F
5.367	0.000	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_s0
10.856	-0.035	tSu		1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.225, 38.023%; route: 1.764, 54.773%; tC2Q: 0.232, 7.203%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	5.552
Data Arrival Time	5.304
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C31[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
2.379	0.232	tC2Q	RF	5	R27C31[2][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q
3.024	0.645	tNET	FF	2	R27C35[0][B]	gw_gao_inst_0/u_la0_top/n2214_s9/I0
3.573	0.549	tINS	FR	1	R27C35[0][B]	gw_gao_inst_0/u_la0_top/n2214_s9/COUT
3.573	0.000	tNET	RR	2	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n2214_s10/CIN
3.608	0.035	tINS	RF	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n2214_s10/COUT
4.734	1.126	tNET	FF	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg1_s0/I3
5.304	0.570	tINS	FR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg1_s0/F
5.304	0.000	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/start_reg_s0
10.856	-0.035	tSu		1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.154, 36.557%; route: 1.771, 56.094%; tC2Q: 0.232, 7.348%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	5.591
Data Arrival Time	5.265
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	300	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/CLK
2.379	0.232	tC2Q	RF	2	R30C31[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_15_s0/Q
2.794	0.415	tNET	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/I3
3.349	0.555	tINS	FF	1	R27C31[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s6/F
4.005	0.656	tNET	FF	1	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I0
4.376	0.371	tINS	FF	3	R24C33[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
4.794	0.418	tNET	FF	1	R21C33[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
5.121	0.327	tINS	FR	1	R21C33[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
5.265	0.144	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.253, 40.186%; route: 1.633, 52.373%; tC2Q: 0.232, 7.441%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	5.600
Data Arrival Time	5.291
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R10[7]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R10[7]	mem_data_mem_data_0_0_s/DO[1]
4.025	0.839	tNET	FF	2	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/I0
4.574	0.549	tINS	FR	1	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT
4.574	0.000	tNET	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN
4.609	0.035	tINS	RF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT
4.609	0.000	tNET	FF	2	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN
4.645	0.035	tINS	FF	1	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT
4.645	0.000	tNET	FF	2	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN
4.680	0.035	tINS	FF	1	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT
4.680	0.000	tNET	FF	2	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN
4.715	0.035	tINS	FF	1	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT
4.715	0.000	tNET	FF	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN
4.750	0.035	tINS	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT
4.750	0.000	tNET	FF	2	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN
4.785	0.035	tINS	FF	1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/COUT
4.785	0.000	tNET	FF	2	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/CIN
4.821	0.035	tINS	FF	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/COUT
4.821	0.000	tNET	FF	2	R21C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n31_s/CIN
5.291	0.470	tINS	FF	1	R21C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n31_s/SUM
5.291	0.000	tNET	FF	1	R21C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/CLK
10.891	-0.035	tSu		1	R21C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.265, 28.991%; route: 0.839, 19.230%; tC2Q: 2.260, 51.778%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	5.635
Data Arrival Time	5.255
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R10[7]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R10[7]	mem_data_mem_data_0_0_s/DO[1]
4.025	0.839	tNET	FF	2	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/I0
4.574	0.549	tINS	FR	1	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT
4.574	0.000	tNET	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN
4.609	0.035	tINS	RF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT
4.609	0.000	tNET	FF	2	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN
4.645	0.035	tINS	FF	1	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT
4.645	0.000	tNET	FF	2	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN
4.680	0.035	tINS	FF	1	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT
4.680	0.000	tNET	FF	2	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN
4.715	0.035	tINS	FF	1	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT
4.715	0.000	tNET	FF	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN
4.750	0.035	tINS	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT
4.750	0.000	tNET	FF	2	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN
4.785	0.035	tINS	FF	1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/COUT
4.785	0.000	tNET	FF	2	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/CIN
5.255	0.470	tINS	FF	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/SUM
5.255	0.000	tNET	FF	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/CLK
10.891	-0.035	tSu		1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.230, 28.414%; route: 0.839, 19.386%; tC2Q: 2.260, 52.199%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	5.671
Data Arrival Time	5.220
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R10[7]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R10[7]	mem_data_mem_data_0_0_s/DO[1]
4.025	0.839	tNET	FF	2	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/I0
4.574	0.549	tINS	FR	1	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT
4.574	0.000	tNET	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN
4.609	0.035	tINS	RF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT
4.609	0.000	tNET	FF	2	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN
4.645	0.035	tINS	FF	1	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT
4.645	0.000	tNET	FF	2	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN
4.680	0.035	tINS	FF	1	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT
4.680	0.000	tNET	FF	2	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN
4.715	0.035	tINS	FF	1	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT
4.715	0.000	tNET	FF	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN
4.750	0.035	tINS	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT
4.750	0.000	tNET	FF	2	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN
5.220	0.470	tINS	FF	1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/SUM
5.220	0.000	tNET	FF	1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/CLK
10.891	-0.035	tSu		1	R21C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.195, 27.827%; route: 0.839, 19.545%; tC2Q: 2.260, 52.627%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	5.706
Data Arrival Time	5.185
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R10[7]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R10[7]	mem_data_mem_data_0_0_s/DO[1]
4.025	0.839	tNET	FF	2	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/I0
4.574	0.549	tINS	FR	1	R21C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT
4.574	0.000	tNET	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN
4.609	0.035	tINS	RF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT
4.609	0.000	tNET	FF	2	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN
4.645	0.035	tINS	FF	1	R21C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT
4.645	0.000	tNET	FF	2	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN
4.680	0.035	tINS	FF	1	R21C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT
4.680	0.000	tNET	FF	2	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN
4.715	0.035	tINS	FF	1	R21C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT
4.715	0.000	tNET	FF	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN
5.185	0.470	tINS	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/SUM
5.185	0.000	tNET	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/CLK
10.891	-0.035	tSu		1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.160, 27.231%; route: 0.839, 19.707%; tC2Q: 2.260, 53.062%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[2]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	57	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R25C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[2]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[2]_2_s0/CLK
0.871	0.011	tHld		1	R25C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[2]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	57	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R25C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_2_s0/CLK
0.871	0.011	tHld		1	R25C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.324
Data Arrival Time	1.195
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	57	R25C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/out_valid_s0/Q
1.195	0.133	tNET	RR	1	R25C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_2_s0/CLK
0.871	0.011	tHld		1	R25C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.133, 39.771%; tC2Q: 0.202, 60.229%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.327
Data Arrival Time	1.199
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.061	0.201	tC2Q	RF	11	R22C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
1.199	0.138	tNET	FF	1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/CLK
0.872	0.012	tHld		1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.138, 40.758%; tC2Q: 0.201, 59.242%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.330
Data Arrival Time	1.201
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/CLK
1.061	0.201	tC2Q	RF	12	R22C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/Q
1.201	0.141	tNET	FF	1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/AD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29/CLK
0.872	0.012	tHld		1	R23C25	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s29

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 41.164%; tC2Q: 0.201, 58.836%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.369
Data Arrival Time	1.477
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/triger_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.062	0.202	tC2Q	RR	12	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/Q
1.477	0.416	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.416, 67.298%; tC2Q: 0.202, 32.702%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C31[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK
1.062	0.202	tC2Q	RR	1	R22C31[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/CLK
1.062	0.202	tC2Q	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/CLK
1.062	0.202	tC2Q	RR	3	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/Q
1.064	0.002	tNET	RR	2	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n18_s/I1
1.296	0.232	tINS	RF	1	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n18_s/SUM
1.296	0.000	tNET	FF	1	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/CLK
0.871	0.011	tHld		1	R31C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/Q
1.064	0.002	tNET	RR	2	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n30_s/I1
1.296	0.232	tINS	RF	1	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n30_s/SUM
1.296	0.000	tNET	FF	1	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R34C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/Q
1.064	0.002	tNET	RR	2	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n26_s/I1
1.296	0.232	tINS	RF	1	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n26_s/SUM
1.296	0.000	tNET	FF	1	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R34C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/Q
1.064	0.002	tNET	RR	2	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n24_s/I1
1.296	0.232	tINS	RF	1	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n24_s/SUM
1.296	0.000	tNET	FF	1	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R34C24[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/Q
1.064	0.002	tNET	RR	2	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n20_s/I1
1.296	0.232	tINS	RF	1	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n20_s/SUM
1.296	0.000	tNET	FF	1	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0/CLK
0.871	0.011	tHld		1	R34C25[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/Q
1.064	0.002	tNET	RR	2	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n18_s/I1
1.296	0.232	tINS	RF	1	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n18_s/SUM
1.296	0.000	tNET	FF	1	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0/CLK
0.871	0.011	tHld		1	R34C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/Q
1.064	0.002	tNET	RR	2	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n14_s/I1
1.296	0.232	tINS	RF	1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n14_s/SUM
1.296	0.000	tNET	FF	1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0/CLK
0.871	0.011	tHld		1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/Q
1.064	0.002	tNET	RR	2	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n12_s/I1
1.296	0.232	tINS	RF	1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/n12_s/SUM
1.296	0.000	tNET	FF	1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0/CLK
0.871	0.011	tHld		1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/Q
1.064	0.002	tNET	RR	2	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n30_s/I1
1.296	0.232	tINS	RF	1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n30_s/SUM
1.296	0.000	tNET	FF	1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/Q
1.064	0.002	tNET	RR	2	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n26_s/I1
1.296	0.232	tINS	RF	1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n26_s/SUM
1.296	0.000	tNET	FF	1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/Q
1.064	0.002	tNET	RR	2	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n24_s/I1
1.296	0.232	tINS	RF	1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n24_s/SUM
1.296	0.000	tNET	FF	1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/Q
1.064	0.002	tNET	RR	2	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n20_s/I1
1.296	0.232	tINS	RF	1	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n20_s/SUM
1.296	0.000	tNET	FF	1	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/CLK
0.871	0.011	tHld		1	R31C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/Q
1.064	0.002	tNET	RR	2	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n18_s/I1
1.296	0.232	tINS	RF	1	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n18_s/SUM
1.296	0.000	tNET	FF	1	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0/CLK
0.871	0.011	tHld		1	R31C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/CLK
1.062	0.202	tC2Q	RR	2	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/Q
1.064	0.002	tNET	RR	2	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n14_s/I1
1.296	0.232	tINS	RF	1	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/n14_s/SUM
1.296	0.000	tNET	FF	1	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0/CLK
0.871	0.011	tHld		1	R31C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.647
Data Arrival Time	7.244
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.244	1.063	tNET	FF	1	R27C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.891	-0.035	tSu		1	R27C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 82.088%; tC2Q: 0.232, 17.912%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.647
Data Arrival Time	7.244
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.244	1.063	tNET	FF	1	R27C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.891	-0.035	tSu		1	R27C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.063, 82.088%; tC2Q: 0.232, 17.912%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.675
Data Arrival Time	7.216
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.216	1.035	tNET	FF	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tSu		1	R29C36[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.035, 81.690%; tC2Q: 0.232, 18.310%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.675
Data Arrival Time	7.216
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.216	1.035	tNET	FF	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tSu		1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.035, 81.690%; tC2Q: 0.232, 18.310%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.771
Data Arrival Time	7.119
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.119	0.939	tNET	FF	1	R24C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R24C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
10.891	-0.035	tSu		1	R24C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.939, 80.180%; tC2Q: 0.232, 19.820%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.778
Data Arrival Time	7.113
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.113	0.932	tNET	FF	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R21C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.932, 80.067%; tC2Q: 0.232, 19.933%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.778
Data Arrival Time	7.113
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.113	0.932	tNET	FF	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tSu		1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.932, 80.067%; tC2Q: 0.232, 19.933%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.778
Data Arrival Time	7.113
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.113	0.932	tNET	FF	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tSu		1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.932, 80.067%; tC2Q: 0.232, 19.933%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.800
Data Arrival Time	7.091
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.091	0.910	tNET	FF	1	R27C35[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C35[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.891	-0.035	tSu		1	R27C35[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.910, 79.685%; tC2Q: 0.232, 20.315%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.849
Data Arrival Time	7.042
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.042	0.861	tNET	FF	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.891	-0.035	tSu		1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.861, 78.767%; tC2Q: 0.232, 21.233%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.859
Data Arrival Time	7.032
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.032	0.851	tNET	FF	1	R24C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R24C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.891	-0.035	tSu		1	R24C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.851, 78.586%; tC2Q: 0.232, 21.414%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.912
Data Arrival Time	6.979
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.979	0.798	tNET	FF	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.891	-0.035	tSu		1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 77.477%; tC2Q: 0.232, 22.523%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.912
Data Arrival Time	6.979
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.979	0.798	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.891	-0.035	tSu		1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.798, 77.477%; tC2Q: 0.232, 22.523%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.003
Data Arrival Time	6.888
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.888	0.707	tNET	FF	1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.891	-0.035	tSu		1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.707, 75.300%; tC2Q: 0.232, 24.700%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.003
Data Arrival Time	6.888
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.888	0.707	tNET	FF	1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
10.891	-0.035	tSu		1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.707, 75.300%; tC2Q: 0.232, 24.700%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	4.008
Data Arrival Time	6.882
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.882	0.702	tNET	FF	1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
10.891	-0.035	tSu		1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.702, 75.149%; tC2Q: 0.232, 24.851%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	4.008
Data Arrival Time	6.882
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.882	0.702	tNET	FF	1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.891	-0.035	tSu		1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.702, 75.149%; tC2Q: 0.232, 24.851%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	4.014
Data Arrival Time	6.877
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.877	0.696	tNET	FF	1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.891	-0.035	tSu		1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.696, 74.995%; tC2Q: 0.232, 25.005%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	4.048
Data Arrival Time	6.842
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.842	0.662	tNET	FF	1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.891	-0.035	tSu		1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.662, 74.036%; tC2Q: 0.232, 25.964%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tSu		1	R22C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tSu		1	R22C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tSu		1	R22C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R22C33[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C33[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
10.891	-0.035	tSu		1	R22C33[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R21C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R21C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	4.086
Data Arrival Time	6.805
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.805	0.624	tNET	FF	1	R21C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	430	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
10.891	-0.035	tSu		1	R21C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.624, 72.909%; tC2Q: 0.232, 27.091%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.344
Data Arrival Time	6.215
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.215	0.141	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.344
Data Arrival Time	6.215
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.215	0.141	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.344
Data Arrival Time	6.215
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.215	0.141	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 41.059%; tC2Q: 0.202, 58.941%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.464
Data Arrival Time	6.335
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.335	0.261	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871	0.011	tHld		1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.348%; tC2Q: 0.202, 43.652%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.464
Data Arrival Time	6.335
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.335	0.261	tNET	RR	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.261, 56.348%; tC2Q: 0.202, 43.652%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.871	0.011	tHld		1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871	0.011	tHld		1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.871	0.011	tHld		1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871	0.011	tHld		1	R21C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.871	0.011	tHld		1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R22C35[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R22C35[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.471
Data Arrival Time	6.342
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.342	0.268	tNET	RR	1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.268, 56.993%; tC2Q: 0.202, 43.007%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871	0.011	tHld		1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.871	0.011	tHld		1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.588%; tC2Q: 0.202, 42.412%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.487
Data Arrival Time	6.357
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.357	0.283	tNET	RR	1	R21C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871	0.011	tHld		1	R21C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.283, 58.375%; tC2Q: 0.202, 41.625%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.583
Data Arrival Time	6.454
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.454	0.380	tNET	RR	1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.871	0.011	tHld		1	R23C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.380, 65.277%; tC2Q: 0.202, 34.723%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.597
Data Arrival Time	6.467
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.467	0.393	tNET	RR	1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871	0.011	tHld		1	R24C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.393, 66.066%; tC2Q: 0.202, 33.934%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871	0.011	tHld		1	R23C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.236%; tC2Q: 0.202, 33.764%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.871	0.011	tHld		1	R23C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.236%; tC2Q: 0.202, 33.764%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.600
Data Arrival Time	6.471
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.471	0.397	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.397, 66.291%; tC2Q: 0.202, 33.709%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.603
Data Arrival Time	6.473
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.473	0.399	tNET	RR	1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871	0.011	tHld		1	R22C32[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.405%; tC2Q: 0.202, 33.595%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.603
Data Arrival Time	6.473
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	430	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R21C35[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.473	0.399	tNET	RR	1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	430	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
0.871	0.011	tHld		1	R22C32[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.399, 66.405%; tC2Q: 0.202, 33.595%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_10_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_8_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_4_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_9_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	i_data_9_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	i_data_9_s1/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_2_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_3_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_0_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_1_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
430	clk_d	3.647	0.261
300	control0[0]	2.175	0.912
72	n20_3	44.466	1.705
62	comb_vaild_1[2]	8.438	1.295
57	comb_vaild_0[1]	8.058	1.675
52	comb_vaild[0]	8.417	1.316
50	data_out_shift_reg_48_7	44.466	0.714
49	rst_ao	3.647	1.063
37	n751_9	45.083	1.047
36	op_reg_en	44.132	1.112

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R29C32	88.89%
R29C33	87.50%
R21C26	86.11%
R29C35	86.11%
R29C36	86.11%
R27C31	84.72%
R29C30	84.72%
R29C34	84.72%
R27C32	84.72%
R31C28	83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]