Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\2_9_4_8_3\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\2_9_4_8_3\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\2_9_4_8_3\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 08:31:41 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	4063
Numbers of Endpoints Analyzed	4592
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	177.887(MHz)	9	TOP
2	tck_pad_i	20.000(MHz)	96.867(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.797	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.772
2	2.797	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.772
3	4.378	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_40_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.587
4	4.414	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_39_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.551
5	4.445	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_40_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.520
6	4.449	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_38_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.516
7	4.480	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_39_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.485
8	4.484	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_37_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.481
9	4.506	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_40_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.459
10	4.515	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_38_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.450
11	4.519	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_36_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.446
12	4.530	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_40_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.435
13	4.541	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_39_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.424
14	4.550	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_37_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.415
15	4.554	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_35_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.411
16	4.566	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_39_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.399
17	4.569	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.140
18	4.571	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.138
19	4.576	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_38_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.389
20	4.586	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_36_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.379
21	4.590	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_34_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.375
22	4.596	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_40_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.369
23	4.601	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_38_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.364
24	4.612	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_37_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.353
25	4.621	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_35_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.344

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
5	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17]	clk:[R]	clk:[R]	0.000	0.000	0.474
6	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[16]	clk:[R]	clk:[R]	0.000	0.000	0.474
7	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_40_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s45/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.326
8	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_27_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.326
9	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_26_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.326
10	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_25_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[1]	clk:[R]	clk:[R]	0.000	0.000	0.326
11	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_24_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.326
12	0.314	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_32_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s41/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.326
13	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_37_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s43/DI[1]	clk:[R]	clk:[R]	0.000	0.000	0.326
14	0.314	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_34_s0/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s41/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.326
15	0.339	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s33/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.351
16	0.339	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s2/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s22/AD[0]	clk:[R]	clk:[R]	0.000	0.000	0.351
17	0.341	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s37/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.353
18	0.342	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.354
19	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[8]	clk:[R]	clk:[R]	0.000	0.000	0.481
20	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.612
21	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.612
22	0.364	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11]	clk:[R]	clk:[R]	0.000	0.000	0.482
23	0.425	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/Q	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
24	0.425	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
25	0.425	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.946	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.996
2	2.946	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.996
3	2.946	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.996
4	2.958	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	1.984
5	2.958	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.984
6	2.958	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.984
7	3.200	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.742
8	3.200	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.742
9	3.200	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.742
10	3.200	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.742
11	3.449	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.493
12	3.449	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.493
13	3.449	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.493
14	3.449	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.493
15	3.449	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.493
16	3.455	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.487
17	3.455	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.487
18	3.460	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.482
19	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
20	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
21	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
22	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
23	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
24	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239
25	3.703	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.239

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.465
2	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.465
3	5.470	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.468
4	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.593
5	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.593
6	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.593
7	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.593
8	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-5.000	0.012	0.593
9	5.726	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.724
10	5.726	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.724
11	5.726	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.724
12	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
13	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
14	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
15	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
16	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
17	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
18	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
19	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
20	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
21	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
22	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
23	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
24	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861
25	5.862	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.861

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_9_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_7_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_3_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	i_data_7_s1
5	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_34_s0
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_2_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_20_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_15_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_23_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_24_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.797
Data Arrival Time	28.059
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	339	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R26C40[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R26C40[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.059	0.540	tNET	FF	1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.540, 69.961%; tC2Q: 0.232, 30.039%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.797
Data Arrival Time	28.059
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	339	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R26C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R26C37[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.059	0.540	tNET	FF	1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.540, 69.961%; tC2Q: 0.232, 30.039%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	4.378
Data Arrival Time	6.512
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
5.902	0.035	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/COUT
5.902	0.000	tNET	FF	2	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/CIN
5.937	0.035	tINS	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/COUT
5.937	0.000	tNET	FF	2	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/CIN
5.972	0.035	tINS	FF	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/COUT
5.972	0.000	tNET	FF	2	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/CIN
6.007	0.035	tINS	FF	1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/COUT
6.007	0.000	tNET	FF	2	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n50_s/CIN
6.042	0.035	tINS	FF	1	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n50_s/COUT
6.042	0.000	tNET	FF	2	R17C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n49_s/CIN
6.512	0.470	tINS	FF	1	R17C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n49_s/SUM
6.512	0.000	tNET	FF	1	R17C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_40_s0/CLK
10.891	-0.035	tSu		1	R17C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_40_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.067, 54.893%; route: 2.288, 40.954%; tC2Q: 0.232, 4.153%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.414
Data Arrival Time	6.477
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
5.902	0.035	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/COUT
5.902	0.000	tNET	FF	2	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/CIN
5.937	0.035	tINS	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/COUT
5.937	0.000	tNET	FF	2	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/CIN
5.972	0.035	tINS	FF	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/COUT
5.972	0.000	tNET	FF	2	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/CIN
6.007	0.035	tINS	FF	1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/COUT
6.007	0.000	tNET	FF	2	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n50_s/CIN
6.477	0.470	tINS	FF	1	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n50_s/SUM
6.477	0.000	tNET	FF	1	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_39_s0/CLK
10.891	-0.035	tSu		1	R17C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_39_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.031, 54.607%; route: 2.288, 41.214%; tC2Q: 0.232, 4.179%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.445
Data Arrival Time	6.446
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
5.835	0.035	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/COUT
5.835	0.000	tNET	FF	2	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/CIN
5.870	0.035	tINS	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/COUT
5.870	0.000	tNET	FF	2	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/CIN
5.906	0.035	tINS	FF	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/COUT
5.906	0.000	tNET	FF	2	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/CIN
5.941	0.035	tINS	FF	1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/COUT
5.941	0.000	tNET	FF	2	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n50_s/CIN
5.976	0.035	tINS	FF	1	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n50_s/COUT
5.976	0.000	tNET	FF	2	R17C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n49_s/CIN
6.446	0.470	tINS	FF	1	R17C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n49_s/SUM
6.446	0.000	tNET	FF	1	R17C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_40_s0/CLK
10.891	-0.035	tSu		1	R17C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_40_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.151, 57.088%; route: 2.137, 38.709%; tC2Q: 0.232, 4.203%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.449
Data Arrival Time	6.442
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
5.902	0.035	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/COUT
5.902	0.000	tNET	FF	2	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/CIN
5.937	0.035	tINS	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/COUT
5.937	0.000	tNET	FF	2	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/CIN
5.972	0.035	tINS	FF	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/COUT
5.972	0.000	tNET	FF	2	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/CIN
6.442	0.470	tINS	FF	1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n51_s/SUM
6.442	0.000	tNET	FF	1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_38_s0/CLK
10.891	-0.035	tSu		1	R17C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_38_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.996, 54.317%; route: 2.288, 41.477%; tC2Q: 0.232, 4.206%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.480
Data Arrival Time	6.411
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
5.835	0.035	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/COUT
5.835	0.000	tNET	FF	2	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/CIN
5.870	0.035	tINS	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/COUT
5.870	0.000	tNET	FF	2	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/CIN
5.906	0.035	tINS	FF	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/COUT
5.906	0.000	tNET	FF	2	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/CIN
5.941	0.035	tINS	FF	1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/COUT
5.941	0.000	tNET	FF	2	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n50_s/CIN
6.411	0.470	tINS	FF	1	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n50_s/SUM
6.411	0.000	tNET	FF	1	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_39_s0/CLK
10.891	-0.035	tSu		1	R17C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_39_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.116, 56.813%; route: 2.137, 38.958%; tC2Q: 0.232, 4.230%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.484
Data Arrival Time	6.407
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
5.902	0.035	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/COUT
5.902	0.000	tNET	FF	2	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/CIN
5.937	0.035	tINS	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/COUT
5.937	0.000	tNET	FF	2	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/CIN
6.407	0.470	tINS	FF	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n52_s/SUM
6.407	0.000	tNET	FF	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_37_s0/CLK
10.891	-0.035	tSu		1	R17C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_37_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.961, 54.024%; route: 2.288, 41.744%; tC2Q: 0.232, 4.233%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.506
Data Arrival Time	6.385
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/CLK
1.158	0.232	tC2Q	RF	28	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q
2.193	1.036	tNET	FF	4	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/AD[0](chk_dup)
2.710	0.517	tINS	FF	1	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/DO[2]
3.124	0.413	tNET	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/I1
3.577	0.453	tINS	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/F
4.382	0.806	tNET	FF	2	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/I1
4.753	0.371	tINS	FF	1	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/COUT
4.753	0.000	tNET	FF	2	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/CIN
4.789	0.035	tINS	FF	1	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/COUT
4.789	0.000	tNET	FF	2	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/CIN
4.824	0.035	tINS	FF	1	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/COUT
4.824	0.000	tNET	FF	2	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/CIN
4.859	0.035	tINS	FF	1	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/COUT
4.859	0.000	tNET	FF	2	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/CIN
4.894	0.035	tINS	FF	1	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/COUT
4.894	0.000	tNET	FF	2	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/CIN
4.929	0.035	tINS	FF	1	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/COUT
4.929	0.000	tNET	FF	2	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/CIN
4.965	0.035	tINS	FF	1	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/COUT
4.965	0.000	tNET	FF	2	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/CIN
5.000	0.035	tINS	FF	1	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/COUT
5.000	0.000	tNET	FF	2	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/CIN
5.035	0.035	tINS	FF	1	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/COUT
5.035	0.000	tNET	FF	2	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/CIN
5.070	0.035	tINS	FF	1	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/COUT
5.070	0.000	tNET	FF	2	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/CIN
5.105	0.035	tINS	FF	1	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/COUT
5.105	0.000	tNET	FF	2	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/CIN
5.141	0.035	tINS	FF	1	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/COUT
5.141	0.000	tNET	FF	2	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/CIN
5.176	0.035	tINS	FF	1	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/COUT
5.176	0.000	tNET	FF	2	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/CIN
5.211	0.035	tINS	FF	1	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/COUT
5.211	0.000	tNET	FF	2	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/CIN
5.246	0.035	tINS	FF	1	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/COUT
5.246	0.000	tNET	FF	2	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/CIN
5.281	0.035	tINS	FF	1	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/COUT
5.281	0.000	tNET	FF	2	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/CIN
5.317	0.035	tINS	FF	1	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/COUT
5.317	0.000	tNET	FF	2	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/CIN
5.352	0.035	tINS	FF	1	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/COUT
5.352	0.000	tNET	FF	2	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/CIN
5.387	0.035	tINS	FF	1	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/COUT
5.387	0.000	tNET	FF	2	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/CIN
5.422	0.035	tINS	FF	1	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/COUT
5.422	0.000	tNET	FF	2	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/CIN
5.457	0.035	tINS	FF	1	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/COUT
5.457	0.000	tNET	FF	2	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/CIN
5.493	0.035	tINS	FF	1	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/COUT
5.493	0.000	tNET	FF	2	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/CIN
5.528	0.035	tINS	FF	1	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/COUT
5.528	0.000	tNET	FF	2	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/CIN
5.563	0.035	tINS	FF	1	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/COUT
5.563	0.000	tNET	FF	2	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/CIN
5.598	0.035	tINS	FF	1	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/COUT
5.598	0.000	tNET	FF	2	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/CIN
5.633	0.035	tINS	FF	1	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/COUT
5.633	0.000	tNET	FF	2	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/CIN
5.669	0.035	tINS	FF	1	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/COUT
5.669	0.000	tNET	FF	2	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/CIN
5.704	0.035	tINS	FF	1	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/COUT
5.704	0.000	tNET	FF	2	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/CIN
5.739	0.035	tINS	FF	1	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/COUT
5.739	0.000	tNET	FF	2	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/CIN
5.774	0.035	tINS	FF	1	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/COUT
5.774	0.000	tNET	FF	2	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/CIN
5.809	0.035	tINS	FF	1	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/COUT
5.809	0.000	tNET	FF	2	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/CIN
5.845	0.035	tINS	FF	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/COUT
5.845	0.000	tNET	FF	2	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/CIN
5.880	0.035	tINS	FF	1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/COUT
5.880	0.000	tNET	FF	2	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n50_s/CIN
5.915	0.035	tINS	FF	1	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n50_s/COUT
5.915	0.000	tNET	FF	2	R16C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n49_s/CIN
6.385	0.470	tINS	FF	1	R16C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n49_s/SUM
6.385	0.000	tNET	FF	1	R16C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R16C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_40_s0/CLK
10.891	-0.035	tSu		1	R16C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_40_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.973, 54.452%; route: 2.254, 41.298%; tC2Q: 0.232, 4.250%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.515
Data Arrival Time	6.376
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
5.835	0.035	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/COUT
5.835	0.000	tNET	FF	2	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/CIN
5.870	0.035	tINS	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/COUT
5.870	0.000	tNET	FF	2	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/CIN
5.906	0.035	tINS	FF	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/COUT
5.906	0.000	tNET	FF	2	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/CIN
6.376	0.470	tINS	FF	1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n51_s/SUM
6.376	0.000	tNET	FF	1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_38_s0/CLK
10.891	-0.035	tSu		1	R17C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_38_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.081, 56.534%; route: 2.137, 39.209%; tC2Q: 0.232, 4.257%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.519
Data Arrival Time	6.372
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_36_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
5.902	0.035	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/COUT
5.902	0.000	tNET	FF	2	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/CIN
6.372	0.470	tINS	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n53_s/SUM
6.372	0.000	tNET	FF	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_36_s0/CLK
10.891	-0.035	tSu		1	R17C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_36_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.926, 53.726%; route: 2.288, 42.013%; tC2Q: 0.232, 4.260%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.530
Data Arrival Time	6.360
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	27	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q
1.887	0.730	tNET	FF	4	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/AD[1](chk_dup)
2.404	0.517	tINS	FF	1	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/DO[2]
2.818	0.413	tNET	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/I1
3.335	0.517	tINS	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/F
4.217	0.882	tNET	FF	2	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/I1
4.588	0.371	tINS	FF	1	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/COUT
4.588	0.000	tNET	FF	2	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/CIN
4.623	0.035	tINS	FF	1	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/COUT
4.623	0.000	tNET	FF	2	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/CIN
4.658	0.035	tINS	FF	1	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/COUT
4.658	0.000	tNET	FF	2	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/CIN
4.694	0.035	tINS	FF	1	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/COUT
4.694	0.000	tNET	FF	2	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/CIN
4.729	0.035	tINS	FF	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/COUT
4.729	0.000	tNET	FF	2	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/CIN
4.764	0.035	tINS	FF	1	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/COUT
4.764	0.000	tNET	FF	2	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/CIN
4.799	0.035	tINS	FF	1	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/COUT
4.799	0.000	tNET	FF	2	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/CIN
4.834	0.035	tINS	FF	1	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/COUT
4.834	0.000	tNET	FF	2	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/CIN
4.870	0.035	tINS	FF	1	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/COUT
4.870	0.000	tNET	FF	2	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/CIN
4.905	0.035	tINS	FF	1	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/COUT
4.905	0.000	tNET	FF	2	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/CIN
4.940	0.035	tINS	FF	1	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/COUT
4.940	0.000	tNET	FF	2	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/CIN
4.975	0.035	tINS	FF	1	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/COUT
4.975	0.000	tNET	FF	2	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/CIN
5.010	0.035	tINS	FF	1	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/COUT
5.010	0.000	tNET	FF	2	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/CIN
5.046	0.035	tINS	FF	1	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/COUT
5.046	0.000	tNET	FF	2	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/CIN
5.081	0.035	tINS	FF	1	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/COUT
5.081	0.000	tNET	FF	2	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/CIN
5.116	0.035	tINS	FF	1	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/COUT
5.116	0.000	tNET	FF	2	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/CIN
5.151	0.035	tINS	FF	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/COUT
5.151	0.000	tNET	FF	2	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/CIN
5.186	0.035	tINS	FF	1	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/COUT
5.186	0.000	tNET	FF	2	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/CIN
5.222	0.035	tINS	FF	1	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/COUT
5.222	0.000	tNET	FF	2	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/CIN
5.257	0.035	tINS	FF	1	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/COUT
5.257	0.000	tNET	FF	2	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/CIN
5.292	0.035	tINS	FF	1	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/COUT
5.292	0.000	tNET	FF	2	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/CIN
5.327	0.035	tINS	FF	1	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/COUT
5.327	0.000	tNET	FF	2	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/CIN
5.362	0.035	tINS	FF	1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/COUT
5.362	0.000	tNET	FF	2	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/CIN
5.398	0.035	tINS	FF	1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/COUT
5.398	0.000	tNET	FF	2	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/CIN
5.433	0.035	tINS	FF	1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/COUT
5.433	0.000	tNET	FF	2	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/CIN
5.468	0.035	tINS	FF	1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/COUT
5.468	0.000	tNET	FF	2	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/CIN
5.503	0.035	tINS	FF	1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/COUT
5.503	0.000	tNET	FF	2	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/CIN
5.538	0.035	tINS	FF	1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/COUT
5.538	0.000	tNET	FF	2	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/CIN
5.574	0.035	tINS	FF	1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/COUT
5.574	0.000	tNET	FF	2	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/CIN
5.609	0.035	tINS	FF	1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/COUT
5.609	0.000	tNET	FF	2	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/CIN
5.644	0.035	tINS	FF	1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/COUT
5.644	0.000	tNET	FF	2	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/CIN
5.679	0.035	tINS	FF	1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/COUT
5.679	0.000	tNET	FF	2	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/CIN
5.714	0.035	tINS	FF	1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/COUT
5.714	0.000	tNET	FF	2	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/CIN
5.750	0.035	tINS	FF	1	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/COUT
5.750	0.000	tNET	FF	2	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/CIN
5.785	0.035	tINS	FF	1	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/COUT
5.785	0.000	tNET	FF	2	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/CIN
5.820	0.035	tINS	FF	1	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/COUT
5.820	0.000	tNET	FF	2	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/CIN
5.855	0.035	tINS	FF	1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/COUT
5.855	0.000	tNET	FF	2	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n50_s/CIN
5.890	0.035	tINS	FF	1	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n50_s/COUT
5.890	0.000	tNET	FF	2	R18C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n49_s/CIN
6.360	0.470	tINS	FF	1	R18C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n49_s/SUM
6.360	0.000	tNET	FF	1	R18C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_40_s0/CLK
10.891	-0.035	tSu		1	R18C32[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_40_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.177, 58.466%; route: 2.025, 37.265%; tC2Q: 0.232, 4.269%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.541
Data Arrival Time	6.350
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/CLK
1.158	0.232	tC2Q	RF	28	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q
2.193	1.036	tNET	FF	4	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/AD[0](chk_dup)
2.710	0.517	tINS	FF	1	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/DO[2]
3.124	0.413	tNET	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/I1
3.577	0.453	tINS	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/F
4.382	0.806	tNET	FF	2	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/I1
4.753	0.371	tINS	FF	1	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/COUT
4.753	0.000	tNET	FF	2	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/CIN
4.789	0.035	tINS	FF	1	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/COUT
4.789	0.000	tNET	FF	2	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/CIN
4.824	0.035	tINS	FF	1	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/COUT
4.824	0.000	tNET	FF	2	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/CIN
4.859	0.035	tINS	FF	1	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/COUT
4.859	0.000	tNET	FF	2	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/CIN
4.894	0.035	tINS	FF	1	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/COUT
4.894	0.000	tNET	FF	2	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/CIN
4.929	0.035	tINS	FF	1	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/COUT
4.929	0.000	tNET	FF	2	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/CIN
4.965	0.035	tINS	FF	1	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/COUT
4.965	0.000	tNET	FF	2	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/CIN
5.000	0.035	tINS	FF	1	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/COUT
5.000	0.000	tNET	FF	2	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/CIN
5.035	0.035	tINS	FF	1	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/COUT
5.035	0.000	tNET	FF	2	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/CIN
5.070	0.035	tINS	FF	1	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/COUT
5.070	0.000	tNET	FF	2	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/CIN
5.105	0.035	tINS	FF	1	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/COUT
5.105	0.000	tNET	FF	2	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/CIN
5.141	0.035	tINS	FF	1	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/COUT
5.141	0.000	tNET	FF	2	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/CIN
5.176	0.035	tINS	FF	1	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/COUT
5.176	0.000	tNET	FF	2	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/CIN
5.211	0.035	tINS	FF	1	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/COUT
5.211	0.000	tNET	FF	2	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/CIN
5.246	0.035	tINS	FF	1	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/COUT
5.246	0.000	tNET	FF	2	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/CIN
5.281	0.035	tINS	FF	1	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/COUT
5.281	0.000	tNET	FF	2	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/CIN
5.317	0.035	tINS	FF	1	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/COUT
5.317	0.000	tNET	FF	2	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/CIN
5.352	0.035	tINS	FF	1	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/COUT
5.352	0.000	tNET	FF	2	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/CIN
5.387	0.035	tINS	FF	1	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/COUT
5.387	0.000	tNET	FF	2	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/CIN
5.422	0.035	tINS	FF	1	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/COUT
5.422	0.000	tNET	FF	2	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/CIN
5.457	0.035	tINS	FF	1	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/COUT
5.457	0.000	tNET	FF	2	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/CIN
5.493	0.035	tINS	FF	1	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/COUT
5.493	0.000	tNET	FF	2	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/CIN
5.528	0.035	tINS	FF	1	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/COUT
5.528	0.000	tNET	FF	2	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/CIN
5.563	0.035	tINS	FF	1	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/COUT
5.563	0.000	tNET	FF	2	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/CIN
5.598	0.035	tINS	FF	1	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/COUT
5.598	0.000	tNET	FF	2	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/CIN
5.633	0.035	tINS	FF	1	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/COUT
5.633	0.000	tNET	FF	2	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/CIN
5.669	0.035	tINS	FF	1	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/COUT
5.669	0.000	tNET	FF	2	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/CIN
5.704	0.035	tINS	FF	1	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/COUT
5.704	0.000	tNET	FF	2	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/CIN
5.739	0.035	tINS	FF	1	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/COUT
5.739	0.000	tNET	FF	2	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/CIN
5.774	0.035	tINS	FF	1	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/COUT
5.774	0.000	tNET	FF	2	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/CIN
5.809	0.035	tINS	FF	1	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/COUT
5.809	0.000	tNET	FF	2	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/CIN
5.845	0.035	tINS	FF	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/COUT
5.845	0.000	tNET	FF	2	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/CIN
5.880	0.035	tINS	FF	1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/COUT
5.880	0.000	tNET	FF	2	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n50_s/CIN
6.350	0.470	tINS	FF	1	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n50_s/SUM
6.350	0.000	tNET	FF	1	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_39_s0/CLK
10.891	-0.035	tSu		1	R16C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_39_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.937, 54.157%; route: 2.254, 41.566%; tC2Q: 0.232, 4.277%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.550
Data Arrival Time	6.340
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
5.835	0.035	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/COUT
5.835	0.000	tNET	FF	2	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/CIN
5.870	0.035	tINS	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/COUT
5.870	0.000	tNET	FF	2	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/CIN
6.340	0.470	tINS	FF	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n52_s/SUM
6.340	0.000	tNET	FF	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_37_s0/CLK
10.891	-0.035	tSu		1	R17C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_37_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.046, 56.251%; route: 2.137, 39.464%; tC2Q: 0.232, 4.285%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.554
Data Arrival Time	6.336
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_35_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
5.866	0.035	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/COUT
5.866	0.000	tNET	FF	2	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/CIN
6.336	0.470	tINS	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n54_s/SUM
6.336	0.000	tNET	FF	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_35_s0/CLK
10.891	-0.035	tSu		1	R17C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_35_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.891, 53.425%; route: 2.288, 42.287%; tC2Q: 0.232, 4.288%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	4.566
Data Arrival Time	6.325
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	27	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q
1.887	0.730	tNET	FF	4	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/AD[1](chk_dup)
2.404	0.517	tINS	FF	1	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/DO[2]
2.818	0.413	tNET	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/I1
3.335	0.517	tINS	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/F
4.217	0.882	tNET	FF	2	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/I1
4.588	0.371	tINS	FF	1	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/COUT
4.588	0.000	tNET	FF	2	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/CIN
4.623	0.035	tINS	FF	1	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/COUT
4.623	0.000	tNET	FF	2	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/CIN
4.658	0.035	tINS	FF	1	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/COUT
4.658	0.000	tNET	FF	2	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/CIN
4.694	0.035	tINS	FF	1	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/COUT
4.694	0.000	tNET	FF	2	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/CIN
4.729	0.035	tINS	FF	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/COUT
4.729	0.000	tNET	FF	2	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/CIN
4.764	0.035	tINS	FF	1	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/COUT
4.764	0.000	tNET	FF	2	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/CIN
4.799	0.035	tINS	FF	1	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/COUT
4.799	0.000	tNET	FF	2	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/CIN
4.834	0.035	tINS	FF	1	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/COUT
4.834	0.000	tNET	FF	2	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/CIN
4.870	0.035	tINS	FF	1	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/COUT
4.870	0.000	tNET	FF	2	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/CIN
4.905	0.035	tINS	FF	1	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/COUT
4.905	0.000	tNET	FF	2	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/CIN
4.940	0.035	tINS	FF	1	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/COUT
4.940	0.000	tNET	FF	2	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/CIN
4.975	0.035	tINS	FF	1	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/COUT
4.975	0.000	tNET	FF	2	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/CIN
5.010	0.035	tINS	FF	1	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/COUT
5.010	0.000	tNET	FF	2	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/CIN
5.046	0.035	tINS	FF	1	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/COUT
5.046	0.000	tNET	FF	2	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/CIN
5.081	0.035	tINS	FF	1	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/COUT
5.081	0.000	tNET	FF	2	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/CIN
5.116	0.035	tINS	FF	1	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/COUT
5.116	0.000	tNET	FF	2	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/CIN
5.151	0.035	tINS	FF	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/COUT
5.151	0.000	tNET	FF	2	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/CIN
5.186	0.035	tINS	FF	1	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/COUT
5.186	0.000	tNET	FF	2	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/CIN
5.222	0.035	tINS	FF	1	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/COUT
5.222	0.000	tNET	FF	2	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/CIN
5.257	0.035	tINS	FF	1	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/COUT
5.257	0.000	tNET	FF	2	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/CIN
5.292	0.035	tINS	FF	1	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/COUT
5.292	0.000	tNET	FF	2	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/CIN
5.327	0.035	tINS	FF	1	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/COUT
5.327	0.000	tNET	FF	2	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/CIN
5.362	0.035	tINS	FF	1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/COUT
5.362	0.000	tNET	FF	2	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/CIN
5.398	0.035	tINS	FF	1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/COUT
5.398	0.000	tNET	FF	2	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/CIN
5.433	0.035	tINS	FF	1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/COUT
5.433	0.000	tNET	FF	2	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/CIN
5.468	0.035	tINS	FF	1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/COUT
5.468	0.000	tNET	FF	2	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/CIN
5.503	0.035	tINS	FF	1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/COUT
5.503	0.000	tNET	FF	2	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/CIN
5.538	0.035	tINS	FF	1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/COUT
5.538	0.000	tNET	FF	2	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/CIN
5.574	0.035	tINS	FF	1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/COUT
5.574	0.000	tNET	FF	2	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/CIN
5.609	0.035	tINS	FF	1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/COUT
5.609	0.000	tNET	FF	2	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/CIN
5.644	0.035	tINS	FF	1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/COUT
5.644	0.000	tNET	FF	2	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/CIN
5.679	0.035	tINS	FF	1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/COUT
5.679	0.000	tNET	FF	2	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/CIN
5.714	0.035	tINS	FF	1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/COUT
5.714	0.000	tNET	FF	2	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/CIN
5.750	0.035	tINS	FF	1	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/COUT
5.750	0.000	tNET	FF	2	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/CIN
5.785	0.035	tINS	FF	1	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/COUT
5.785	0.000	tNET	FF	2	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/CIN
5.820	0.035	tINS	FF	1	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/COUT
5.820	0.000	tNET	FF	2	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/CIN
5.855	0.035	tINS	FF	1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/COUT
5.855	0.000	tNET	FF	2	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n50_s/CIN
6.325	0.470	tINS	FF	1	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n50_s/SUM
6.325	0.000	tNET	FF	1	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_39_s0/CLK
10.891	-0.035	tSu		1	R18C32[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_39_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	9
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.142, 58.196%; route: 2.025, 37.507%; tC2Q: 0.232, 4.297%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	4.569
Data Arrival Time	6.287
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	339	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C42[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C42[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.065	0.686	tNET	FF	2	R26C41[2][A]	gw_gao_inst_0/u_la0_top/n2624_s0/I1
3.620	0.555	tINS	FF	5	R26C41[2][A]	gw_gao_inst_0/u_la0_top/n2624_s0/COUT
4.755	1.135	tNET	FF	1	R27C38[3][A]	gw_gao_inst_0/u_la0_top/n2666_s1/I0
5.217	0.462	tINS	FR	1	R27C38[3][A]	gw_gao_inst_0/u_la0_top/n2666_s1/F
5.389	0.172	tNET	RR	1	R27C39[3][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.959	0.570	tINS	RR	1	R27C39[3][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
6.287	0.328	tNET	RR	1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.587, 38.331%; route: 2.321, 56.066%; tC2Q: 0.232, 5.604%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	4.571
Data Arrival Time	6.284
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	339	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C42[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/CLK
2.378	0.231	tC2Q	RR	2	R21C42[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_2_s0/Q
2.551	0.174	tNET	RR	1	R21C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s12/I1
3.106	0.555	tINS	RF	1	R21C41[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s12/F
3.762	0.656	tNET	FF	1	R20C38[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s7/I2
4.317	0.555	tINS	FF	2	R20C38[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s7/F
4.722	0.405	tNET	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s4/I1
5.277	0.555	tINS	FF	10	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n459_s4/F
5.714	0.437	tNET	FF	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n463_s3/I3
6.284	0.570	tINS	FR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n463_s3/F
6.284	0.000	tNET	RR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 54.016%; route: 1.672, 40.401%; tC2Q: 0.231, 5.583%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	4.576
Data Arrival Time	6.315
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/CLK
1.158	0.232	tC2Q	RF	28	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q
2.193	1.036	tNET	FF	4	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/AD[0](chk_dup)
2.710	0.517	tINS	FF	1	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/DO[2]
3.124	0.413	tNET	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/I1
3.577	0.453	tINS	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/F
4.382	0.806	tNET	FF	2	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/I1
4.753	0.371	tINS	FF	1	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/COUT
4.753	0.000	tNET	FF	2	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/CIN
4.789	0.035	tINS	FF	1	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/COUT
4.789	0.000	tNET	FF	2	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/CIN
4.824	0.035	tINS	FF	1	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/COUT
4.824	0.000	tNET	FF	2	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/CIN
4.859	0.035	tINS	FF	1	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/COUT
4.859	0.000	tNET	FF	2	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/CIN
4.894	0.035	tINS	FF	1	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/COUT
4.894	0.000	tNET	FF	2	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/CIN
4.929	0.035	tINS	FF	1	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/COUT
4.929	0.000	tNET	FF	2	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/CIN
4.965	0.035	tINS	FF	1	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/COUT
4.965	0.000	tNET	FF	2	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/CIN
5.000	0.035	tINS	FF	1	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/COUT
5.000	0.000	tNET	FF	2	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/CIN
5.035	0.035	tINS	FF	1	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/COUT
5.035	0.000	tNET	FF	2	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/CIN
5.070	0.035	tINS	FF	1	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/COUT
5.070	0.000	tNET	FF	2	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/CIN
5.105	0.035	tINS	FF	1	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/COUT
5.105	0.000	tNET	FF	2	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/CIN
5.141	0.035	tINS	FF	1	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/COUT
5.141	0.000	tNET	FF	2	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/CIN
5.176	0.035	tINS	FF	1	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/COUT
5.176	0.000	tNET	FF	2	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/CIN
5.211	0.035	tINS	FF	1	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/COUT
5.211	0.000	tNET	FF	2	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/CIN
5.246	0.035	tINS	FF	1	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/COUT
5.246	0.000	tNET	FF	2	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/CIN
5.281	0.035	tINS	FF	1	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/COUT
5.281	0.000	tNET	FF	2	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/CIN
5.317	0.035	tINS	FF	1	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/COUT
5.317	0.000	tNET	FF	2	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/CIN
5.352	0.035	tINS	FF	1	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/COUT
5.352	0.000	tNET	FF	2	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/CIN
5.387	0.035	tINS	FF	1	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/COUT
5.387	0.000	tNET	FF	2	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/CIN
5.422	0.035	tINS	FF	1	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/COUT
5.422	0.000	tNET	FF	2	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/CIN
5.457	0.035	tINS	FF	1	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/COUT
5.457	0.000	tNET	FF	2	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/CIN
5.493	0.035	tINS	FF	1	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/COUT
5.493	0.000	tNET	FF	2	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/CIN
5.528	0.035	tINS	FF	1	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/COUT
5.528	0.000	tNET	FF	2	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/CIN
5.563	0.035	tINS	FF	1	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/COUT
5.563	0.000	tNET	FF	2	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/CIN
5.598	0.035	tINS	FF	1	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/COUT
5.598	0.000	tNET	FF	2	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/CIN
5.633	0.035	tINS	FF	1	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/COUT
5.633	0.000	tNET	FF	2	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/CIN
5.669	0.035	tINS	FF	1	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/COUT
5.669	0.000	tNET	FF	2	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/CIN
5.704	0.035	tINS	FF	1	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/COUT
5.704	0.000	tNET	FF	2	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/CIN
5.739	0.035	tINS	FF	1	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/COUT
5.739	0.000	tNET	FF	2	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/CIN
5.774	0.035	tINS	FF	1	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/COUT
5.774	0.000	tNET	FF	2	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/CIN
5.809	0.035	tINS	FF	1	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/COUT
5.809	0.000	tNET	FF	2	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/CIN
5.845	0.035	tINS	FF	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/COUT
5.845	0.000	tNET	FF	2	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/CIN
6.315	0.470	tINS	FF	1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n51_s/SUM
6.315	0.000	tNET	FF	1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_38_s0/CLK
10.891	-0.035	tSu		1	R16C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_38_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.902, 53.857%; route: 2.254, 41.837%; tC2Q: 0.232, 4.305%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	4.586
Data Arrival Time	6.305
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_36_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
5.835	0.035	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/COUT
5.835	0.000	tNET	FF	2	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/CIN
6.305	0.470	tINS	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n53_s/SUM
6.305	0.000	tNET	FF	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_36_s0/CLK
10.891	-0.035	tSu		1	R17C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_36_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.011, 55.965%; route: 2.137, 39.722%; tC2Q: 0.232, 4.313%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	4.590
Data Arrival Time	6.301
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19
To	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/CLK
1.158	0.232	tC2Q	RF	1	R18C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[0]_0_s19/Q
1.813	0.655	tNET	FF	1	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/I3
2.184	0.371	tINS	FF	41	R21C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_40_s4/F
3.254	1.070	tNET	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/I0
3.771	0.517	tINS	FF	1	R17C15[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[3]_1_s3/F
4.334	0.563	tNET	FF	2	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/I1
4.705	0.371	tINS	FF	1	R17C16[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n88_s/COUT
4.705	0.000	tNET	FF	2	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/CIN
4.740	0.035	tINS	FF	1	R17C16[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n87_s/COUT
4.740	0.000	tNET	FF	2	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/CIN
4.775	0.035	tINS	FF	1	R17C16[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n86_s/COUT
4.775	0.000	tNET	FF	2	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/CIN
4.810	0.035	tINS	FF	1	R17C16[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n85_s/COUT
4.810	0.000	tNET	FF	2	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/CIN
4.846	0.035	tINS	FF	1	R17C17[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n84_s/COUT
4.846	0.000	tNET	FF	2	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/CIN
4.881	0.035	tINS	FF	1	R17C17[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n83_s/COUT
4.881	0.000	tNET	FF	2	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/CIN
4.916	0.035	tINS	FF	1	R17C17[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n82_s/COUT
4.916	0.000	tNET	FF	2	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/CIN
4.951	0.035	tINS	FF	1	R17C17[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n81_s/COUT
4.951	0.000	tNET	FF	2	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/CIN
4.986	0.035	tINS	FF	1	R17C17[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n80_s/COUT
4.986	0.000	tNET	FF	2	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/CIN
5.022	0.035	tINS	FF	1	R17C17[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n79_s/COUT
5.022	0.000	tNET	FF	2	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/CIN
5.057	0.035	tINS	FF	1	R17C18[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n78_s/COUT
5.057	0.000	tNET	FF	2	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/CIN
5.092	0.035	tINS	FF	1	R17C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n77_s/COUT
5.092	0.000	tNET	FF	2	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/CIN
5.127	0.035	tINS	FF	1	R17C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n76_s/COUT
5.127	0.000	tNET	FF	2	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/CIN
5.162	0.035	tINS	FF	1	R17C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n75_s/COUT
5.162	0.000	tNET	FF	2	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/CIN
5.198	0.035	tINS	FF	1	R17C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n74_s/COUT
5.198	0.000	tNET	FF	2	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/CIN
5.233	0.035	tINS	FF	1	R17C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n73_s/COUT
5.233	0.000	tNET	FF	2	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/CIN
5.268	0.035	tINS	FF	1	R17C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n72_s/COUT
5.268	0.000	tNET	FF	2	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/CIN
5.303	0.035	tINS	FF	1	R17C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n71_s/COUT
5.303	0.000	tNET	FF	2	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/CIN
5.338	0.035	tINS	FF	1	R17C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n70_s/COUT
5.338	0.000	tNET	FF	2	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/CIN
5.374	0.035	tINS	FF	1	R17C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n69_s/COUT
5.374	0.000	tNET	FF	2	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/CIN
5.409	0.035	tINS	FF	1	R17C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n68_s/COUT
5.409	0.000	tNET	FF	2	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/CIN
5.444	0.035	tINS	FF	1	R17C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n67_s/COUT
5.444	0.000	tNET	FF	2	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/CIN
5.479	0.035	tINS	FF	1	R17C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n66_s/COUT
5.479	0.000	tNET	FF	2	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/CIN
5.514	0.035	tINS	FF	1	R17C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n65_s/COUT
5.514	0.000	tNET	FF	2	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/CIN
5.550	0.035	tINS	FF	1	R17C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n64_s/COUT
5.550	0.000	tNET	FF	2	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/CIN
5.585	0.035	tINS	FF	1	R17C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n63_s/COUT
5.585	0.000	tNET	FF	2	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/CIN
5.620	0.035	tINS	FF	1	R17C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n62_s/COUT
5.620	0.000	tNET	FF	2	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/CIN
5.655	0.035	tINS	FF	1	R17C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n61_s/COUT
5.655	0.000	tNET	FF	2	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/CIN
5.690	0.035	tINS	FF	1	R17C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n60_s/COUT
5.690	0.000	tNET	FF	2	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/CIN
5.726	0.035	tINS	FF	1	R17C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n59_s/COUT
5.726	0.000	tNET	FF	2	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/CIN
5.761	0.035	tINS	FF	1	R17C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n58_s/COUT
5.761	0.000	tNET	FF	2	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/CIN
5.796	0.035	tINS	FF	1	R17C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n57_s/COUT
5.796	0.000	tNET	FF	2	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/CIN
5.831	0.035	tINS	FF	1	R17C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n56_s/COUT
5.831	0.000	tNET	FF	2	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/CIN
6.301	0.470	tINS	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/n55_s/SUM
6.301	0.000	tNET	FF	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_34_s0/CLK
10.891	-0.035	tSu		1	R17C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/comb_out_34_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.855, 53.120%; route: 2.288, 42.564%; tC2Q: 0.232, 4.316%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	4.596
Data Arrival Time	6.295
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R35C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s2/CLK
1.158	0.232	tC2Q	RF	28	R35C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s2/Q
2.126	0.968	tNET	FF	4	R41C17	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s31/AD[0](chk_dup)
2.643	0.517	tINS	FF	1	R41C17	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s31/DO[0]
3.327	0.684	tNET	FF	1	R35C18[3][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[3]_12_s3/I1
3.698	0.371	tINS	FF	1	R35C18[3][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[3]_12_s3/F
4.504	0.806	tNET	FF	2	R31C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n77_s/I1
4.875	0.371	tINS	FF	1	R31C18[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n77_s/COUT
4.875	0.000	tNET	FF	2	R31C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n76_s/CIN
4.910	0.035	tINS	FF	1	R31C18[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n76_s/COUT
4.910	0.000	tNET	FF	2	R31C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n75_s/CIN
4.945	0.035	tINS	FF	1	R31C18[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n75_s/COUT
4.945	0.000	tNET	FF	2	R31C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n74_s/CIN
4.980	0.035	tINS	FF	1	R31C18[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n74_s/COUT
4.980	0.000	tNET	FF	2	R31C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n73_s/CIN
5.016	0.035	tINS	FF	1	R31C18[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n73_s/COUT
5.016	0.000	tNET	FF	2	R31C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n72_s/CIN
5.051	0.035	tINS	FF	1	R31C19[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n72_s/COUT
5.051	0.000	tNET	FF	2	R31C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n71_s/CIN
5.086	0.035	tINS	FF	1	R31C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n71_s/COUT
5.086	0.000	tNET	FF	2	R31C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n70_s/CIN
5.121	0.035	tINS	FF	1	R31C19[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n70_s/COUT
5.121	0.000	tNET	FF	2	R31C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n69_s/CIN
5.156	0.035	tINS	FF	1	R31C19[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n69_s/COUT
5.156	0.000	tNET	FF	2	R31C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n68_s/CIN
5.192	0.035	tINS	FF	1	R31C19[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n68_s/COUT
5.192	0.000	tNET	FF	2	R31C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n67_s/CIN
5.227	0.035	tINS	FF	1	R31C19[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n67_s/COUT
5.227	0.000	tNET	FF	2	R31C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n66_s/CIN
5.262	0.035	tINS	FF	1	R31C20[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n66_s/COUT
5.262	0.000	tNET	FF	2	R31C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n65_s/CIN
5.297	0.035	tINS	FF	1	R31C20[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n65_s/COUT
5.297	0.000	tNET	FF	2	R31C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n64_s/CIN
5.332	0.035	tINS	FF	1	R31C20[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n64_s/COUT
5.332	0.000	tNET	FF	2	R31C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n63_s/CIN
5.368	0.035	tINS	FF	1	R31C20[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n63_s/COUT
5.368	0.000	tNET	FF	2	R31C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n62_s/CIN
5.403	0.035	tINS	FF	1	R31C20[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n62_s/COUT
5.403	0.000	tNET	FF	2	R31C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n61_s/CIN
5.438	0.035	tINS	FF	1	R31C20[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n61_s/COUT
5.438	0.000	tNET	FF	2	R31C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n60_s/CIN
5.473	0.035	tINS	FF	1	R31C21[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n60_s/COUT
5.473	0.000	tNET	FF	2	R31C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n59_s/CIN
5.508	0.035	tINS	FF	1	R31C21[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n59_s/COUT
5.508	0.000	tNET	FF	2	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n58_s/CIN
5.544	0.035	tINS	FF	1	R31C21[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n58_s/COUT
5.544	0.000	tNET	FF	2	R31C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n57_s/CIN
5.579	0.035	tINS	FF	1	R31C21[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n57_s/COUT
5.579	0.000	tNET	FF	2	R31C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n56_s/CIN
5.614	0.035	tINS	FF	1	R31C21[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n56_s/COUT
5.614	0.000	tNET	FF	2	R31C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n55_s/CIN
5.649	0.035	tINS	FF	1	R31C21[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n55_s/COUT
5.649	0.000	tNET	FF	2	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n54_s/CIN
5.684	0.035	tINS	FF	1	R31C22[0][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n54_s/COUT
5.684	0.000	tNET	FF	2	R31C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n53_s/CIN
5.720	0.035	tINS	FF	1	R31C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n53_s/COUT
5.720	0.000	tNET	FF	2	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n52_s/CIN
5.755	0.035	tINS	FF	1	R31C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n52_s/COUT
5.755	0.000	tNET	FF	2	R31C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n51_s/CIN
5.790	0.035	tINS	FF	1	R31C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n51_s/COUT
5.790	0.000	tNET	FF	2	R31C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n50_s/CIN
5.825	0.035	tINS	FF	1	R31C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n50_s/COUT
5.825	0.000	tNET	FF	2	R31C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n49_s/CIN
6.295	0.470	tINS	FF	1	R31C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/n49_s/SUM
6.295	0.000	tNET	FF	1	R31C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R31C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_40_s0/CLK
10.891	-0.035	tSu		1	R31C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_40_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.679, 49.901%; route: 2.458, 45.778%; tC2Q: 0.232, 4.321%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	4.601
Data Arrival Time	6.290
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/CLK
1.158	0.232	tC2Q	RF	27	R21C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s4/Q
1.887	0.730	tNET	FF	4	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/AD[1](chk_dup)
2.404	0.517	tINS	FF	1	R15C30	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[0]_0_s25/DO[2]
2.818	0.413	tNET	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/I1
3.335	0.517	tINS	FF	1	R17C29[3][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s3/F
4.217	0.882	tNET	FF	2	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/I1
4.588	0.371	tINS	FF	1	R18C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n87_s/COUT
4.588	0.000	tNET	FF	2	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/CIN
4.623	0.035	tINS	FF	1	R18C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n86_s/COUT
4.623	0.000	tNET	FF	2	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/CIN
4.658	0.035	tINS	FF	1	R18C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n85_s/COUT
4.658	0.000	tNET	FF	2	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/CIN
4.694	0.035	tINS	FF	1	R18C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n84_s/COUT
4.694	0.000	tNET	FF	2	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/CIN
4.729	0.035	tINS	FF	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n83_s/COUT
4.729	0.000	tNET	FF	2	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/CIN
4.764	0.035	tINS	FF	1	R18C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n82_s/COUT
4.764	0.000	tNET	FF	2	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/CIN
4.799	0.035	tINS	FF	1	R18C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n81_s/COUT
4.799	0.000	tNET	FF	2	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/CIN
4.834	0.035	tINS	FF	1	R18C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n80_s/COUT
4.834	0.000	tNET	FF	2	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/CIN
4.870	0.035	tINS	FF	1	R18C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n79_s/COUT
4.870	0.000	tNET	FF	2	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/CIN
4.905	0.035	tINS	FF	1	R18C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n78_s/COUT
4.905	0.000	tNET	FF	2	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/CIN
4.940	0.035	tINS	FF	1	R18C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n77_s/COUT
4.940	0.000	tNET	FF	2	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/CIN
4.975	0.035	tINS	FF	1	R18C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n76_s/COUT
4.975	0.000	tNET	FF	2	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/CIN
5.010	0.035	tINS	FF	1	R18C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n75_s/COUT
5.010	0.000	tNET	FF	2	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/CIN
5.046	0.035	tINS	FF	1	R18C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n74_s/COUT
5.046	0.000	tNET	FF	2	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/CIN
5.081	0.035	tINS	FF	1	R18C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n73_s/COUT
5.081	0.000	tNET	FF	2	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/CIN
5.116	0.035	tINS	FF	1	R18C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n72_s/COUT
5.116	0.000	tNET	FF	2	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/CIN
5.151	0.035	tINS	FF	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n71_s/COUT
5.151	0.000	tNET	FF	2	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/CIN
5.186	0.035	tINS	FF	1	R18C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n70_s/COUT
5.186	0.000	tNET	FF	2	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/CIN
5.222	0.035	tINS	FF	1	R18C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n69_s/COUT
5.222	0.000	tNET	FF	2	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/CIN
5.257	0.035	tINS	FF	1	R18C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n68_s/COUT
5.257	0.000	tNET	FF	2	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/CIN
5.292	0.035	tINS	FF	1	R18C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n67_s/COUT
5.292	0.000	tNET	FF	2	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/CIN
5.327	0.035	tINS	FF	1	R18C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n66_s/COUT
5.327	0.000	tNET	FF	2	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/CIN
5.362	0.035	tINS	FF	1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n65_s/COUT
5.362	0.000	tNET	FF	2	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/CIN
5.398	0.035	tINS	FF	1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n64_s/COUT
5.398	0.000	tNET	FF	2	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/CIN
5.433	0.035	tINS	FF	1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n63_s/COUT
5.433	0.000	tNET	FF	2	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/CIN
5.468	0.035	tINS	FF	1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n62_s/COUT
5.468	0.000	tNET	FF	2	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/CIN
5.503	0.035	tINS	FF	1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n61_s/COUT
5.503	0.000	tNET	FF	2	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/CIN
5.538	0.035	tINS	FF	1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n60_s/COUT
5.538	0.000	tNET	FF	2	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/CIN
5.574	0.035	tINS	FF	1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n59_s/COUT
5.574	0.000	tNET	FF	2	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/CIN
5.609	0.035	tINS	FF	1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n58_s/COUT
5.609	0.000	tNET	FF	2	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/CIN
5.644	0.035	tINS	FF	1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n57_s/COUT
5.644	0.000	tNET	FF	2	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/CIN
5.679	0.035	tINS	FF	1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n56_s/COUT
5.679	0.000	tNET	FF	2	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/CIN
5.714	0.035	tINS	FF	1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n55_s/COUT
5.714	0.000	tNET	FF	2	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/CIN
5.750	0.035	tINS	FF	1	R18C32[0][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n54_s/COUT
5.750	0.000	tNET	FF	2	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/CIN
5.785	0.035	tINS	FF	1	R18C32[0][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n53_s/COUT
5.785	0.000	tNET	FF	2	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/CIN
5.820	0.035	tINS	FF	1	R18C32[1][A]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n52_s/COUT
5.820	0.000	tNET	FF	2	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/CIN
6.290	0.470	tINS	FF	1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/n51_s/SUM
6.290	0.000	tNET	FF	1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_38_s0/CLK
10.891	-0.035	tSu		1	R18C32[1][B]	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/comb_out_38_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 3.107, 57.921%; route: 2.025, 37.754%; tC2Q: 0.232, 4.325%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	4.612
Data Arrival Time	6.279
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/CLK
1.158	0.232	tC2Q	RF	28	R20C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s2/Q
2.193	1.036	tNET	FF	4	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/AD[0](chk_dup)
2.710	0.517	tINS	FF	1	R14C19	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[0]_0_s27/DO[2]
3.124	0.413	tNET	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/I1
3.577	0.453	tINS	FF	1	R15C20[3][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/buff_delay[3]_6_s3/F
4.382	0.806	tNET	FF	2	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/I1
4.753	0.371	tINS	FF	1	R16C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n83_s/COUT
4.753	0.000	tNET	FF	2	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/CIN
4.789	0.035	tINS	FF	1	R16C22[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n82_s/COUT
4.789	0.000	tNET	FF	2	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/CIN
4.824	0.035	tINS	FF	1	R16C22[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n81_s/COUT
4.824	0.000	tNET	FF	2	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/CIN
4.859	0.035	tINS	FF	1	R16C22[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n80_s/COUT
4.859	0.000	tNET	FF	2	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/CIN
4.894	0.035	tINS	FF	1	R16C22[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n79_s/COUT
4.894	0.000	tNET	FF	2	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/CIN
4.929	0.035	tINS	FF	1	R16C23[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n78_s/COUT
4.929	0.000	tNET	FF	2	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/CIN
4.965	0.035	tINS	FF	1	R16C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n77_s/COUT
4.965	0.000	tNET	FF	2	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/CIN
5.000	0.035	tINS	FF	1	R16C23[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n76_s/COUT
5.000	0.000	tNET	FF	2	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/CIN
5.035	0.035	tINS	FF	1	R16C23[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n75_s/COUT
5.035	0.000	tNET	FF	2	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/CIN
5.070	0.035	tINS	FF	1	R16C23[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n74_s/COUT
5.070	0.000	tNET	FF	2	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/CIN
5.105	0.035	tINS	FF	1	R16C23[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n73_s/COUT
5.105	0.000	tNET	FF	2	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/CIN
5.141	0.035	tINS	FF	1	R16C24[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n72_s/COUT
5.141	0.000	tNET	FF	2	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/CIN
5.176	0.035	tINS	FF	1	R16C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n71_s/COUT
5.176	0.000	tNET	FF	2	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/CIN
5.211	0.035	tINS	FF	1	R16C24[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n70_s/COUT
5.211	0.000	tNET	FF	2	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/CIN
5.246	0.035	tINS	FF	1	R16C24[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n69_s/COUT
5.246	0.000	tNET	FF	2	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/CIN
5.281	0.035	tINS	FF	1	R16C24[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n68_s/COUT
5.281	0.000	tNET	FF	2	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/CIN
5.317	0.035	tINS	FF	1	R16C24[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n67_s/COUT
5.317	0.000	tNET	FF	2	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/CIN
5.352	0.035	tINS	FF	1	R16C25[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n66_s/COUT
5.352	0.000	tNET	FF	2	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/CIN
5.387	0.035	tINS	FF	1	R16C25[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n65_s/COUT
5.387	0.000	tNET	FF	2	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/CIN
5.422	0.035	tINS	FF	1	R16C25[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n64_s/COUT
5.422	0.000	tNET	FF	2	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/CIN
5.457	0.035	tINS	FF	1	R16C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n63_s/COUT
5.457	0.000	tNET	FF	2	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/CIN
5.493	0.035	tINS	FF	1	R16C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n62_s/COUT
5.493	0.000	tNET	FF	2	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/CIN
5.528	0.035	tINS	FF	1	R16C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n61_s/COUT
5.528	0.000	tNET	FF	2	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/CIN
5.563	0.035	tINS	FF	1	R16C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n60_s/COUT
5.563	0.000	tNET	FF	2	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/CIN
5.598	0.035	tINS	FF	1	R16C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n59_s/COUT
5.598	0.000	tNET	FF	2	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/CIN
5.633	0.035	tINS	FF	1	R16C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n58_s/COUT
5.633	0.000	tNET	FF	2	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/CIN
5.669	0.035	tINS	FF	1	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n57_s/COUT
5.669	0.000	tNET	FF	2	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/CIN
5.704	0.035	tINS	FF	1	R16C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n56_s/COUT
5.704	0.000	tNET	FF	2	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/CIN
5.739	0.035	tINS	FF	1	R16C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n55_s/COUT
5.739	0.000	tNET	FF	2	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/CIN
5.774	0.035	tINS	FF	1	R16C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n54_s/COUT
5.774	0.000	tNET	FF	2	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/CIN
5.809	0.035	tINS	FF	1	R16C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n53_s/COUT
5.809	0.000	tNET	FF	2	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/CIN
6.279	0.470	tINS	FF	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/n52_s/SUM
6.279	0.000	tNET	FF	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_37_s0/CLK
10.891	-0.035	tSu		1	R16C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_37_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.867, 53.554%; route: 2.254, 42.113%; tC2Q: 0.232, 4.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	4.621
Data Arrival Time	6.270
Data Required Time	10.891
From	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_35_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/CLK
1.158	0.232	tC2Q	RF	1	R16C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s13/Q
1.647	0.489	tNET	FF	1	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/I0
2.202	0.555	tINS	FF	41	R20C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_40_s4/F
3.210	1.008	tNET	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/I0
3.663	0.453	tINS	FF	1	R15C23[3][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[3]_2_s3/F
4.303	0.640	tNET	FF	2	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/I1
4.674	0.371	tINS	FF	1	R17C25[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n87_s/COUT
4.674	0.000	tNET	FF	2	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/CIN
4.709	0.035	tINS	FF	1	R17C25[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n86_s/COUT
4.709	0.000	tNET	FF	2	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/CIN
4.744	0.035	tINS	FF	1	R17C25[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n85_s/COUT
4.744	0.000	tNET	FF	2	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/CIN
4.779	0.035	tINS	FF	1	R17C26[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n84_s/COUT
4.779	0.000	tNET	FF	2	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/CIN
4.814	0.035	tINS	FF	1	R17C26[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n83_s/COUT
4.814	0.000	tNET	FF	2	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/CIN
4.850	0.035	tINS	FF	1	R17C26[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n82_s/COUT
4.850	0.000	tNET	FF	2	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/CIN
4.885	0.035	tINS	FF	1	R17C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n81_s/COUT
4.885	0.000	tNET	FF	2	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/CIN
4.920	0.035	tINS	FF	1	R17C26[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n80_s/COUT
4.920	0.000	tNET	FF	2	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/CIN
4.955	0.035	tINS	FF	1	R17C26[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n79_s/COUT
4.955	0.000	tNET	FF	2	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/CIN
4.990	0.035	tINS	FF	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n78_s/COUT
4.990	0.000	tNET	FF	2	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/CIN
5.026	0.035	tINS	FF	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n77_s/COUT
5.026	0.000	tNET	FF	2	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/CIN
5.061	0.035	tINS	FF	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n76_s/COUT
5.061	0.000	tNET	FF	2	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/CIN
5.096	0.035	tINS	FF	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n75_s/COUT
5.096	0.000	tNET	FF	2	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/CIN
5.131	0.035	tINS	FF	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n74_s/COUT
5.131	0.000	tNET	FF	2	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/CIN
5.166	0.035	tINS	FF	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n73_s/COUT
5.166	0.000	tNET	FF	2	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/CIN
5.202	0.035	tINS	FF	1	R17C28[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n72_s/COUT
5.202	0.000	tNET	FF	2	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/CIN
5.237	0.035	tINS	FF	1	R17C28[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n71_s/COUT
5.237	0.000	tNET	FF	2	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/CIN
5.272	0.035	tINS	FF	1	R17C28[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n70_s/COUT
5.272	0.000	tNET	FF	2	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/CIN
5.307	0.035	tINS	FF	1	R17C28[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n69_s/COUT
5.307	0.000	tNET	FF	2	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/CIN
5.342	0.035	tINS	FF	1	R17C28[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n68_s/COUT
5.342	0.000	tNET	FF	2	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/CIN
5.378	0.035	tINS	FF	1	R17C28[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n67_s/COUT
5.378	0.000	tNET	FF	2	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/CIN
5.413	0.035	tINS	FF	1	R17C29[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n66_s/COUT
5.413	0.000	tNET	FF	2	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/CIN
5.448	0.035	tINS	FF	1	R17C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n65_s/COUT
5.448	0.000	tNET	FF	2	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/CIN
5.483	0.035	tINS	FF	1	R17C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n64_s/COUT
5.483	0.000	tNET	FF	2	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/CIN
5.518	0.035	tINS	FF	1	R17C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n63_s/COUT
5.518	0.000	tNET	FF	2	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/CIN
5.554	0.035	tINS	FF	1	R17C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n62_s/COUT
5.554	0.000	tNET	FF	2	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/CIN
5.589	0.035	tINS	FF	1	R17C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n61_s/COUT
5.589	0.000	tNET	FF	2	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/CIN
5.624	0.035	tINS	FF	1	R17C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n60_s/COUT
5.624	0.000	tNET	FF	2	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/CIN
5.659	0.035	tINS	FF	1	R17C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n59_s/COUT
5.659	0.000	tNET	FF	2	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/CIN
5.694	0.035	tINS	FF	1	R17C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n58_s/COUT
5.694	0.000	tNET	FF	2	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/CIN
5.730	0.035	tINS	FF	1	R17C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n57_s/COUT
5.730	0.000	tNET	FF	2	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/CIN
5.765	0.035	tINS	FF	1	R17C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n56_s/COUT
5.765	0.000	tNET	FF	2	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/CIN
5.800	0.035	tINS	FF	1	R17C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n55_s/COUT
5.800	0.000	tNET	FF	2	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/CIN
6.270	0.470	tINS	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/n54_s/SUM
6.270	0.000	tNET	FF	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_35_s0/CLK
10.891	-0.035	tSu		1	R17C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/comb_out_35_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	8
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 2.975, 55.675%; route: 2.137, 39.984%; tC2Q: 0.232, 4.341%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R21C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_53_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_52_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_40_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s45
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_40_s0/CLK
1.061	0.201	tC2Q	RF	2	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_40_s0/Q
1.186	0.125	tNET	FF	1	R33C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s45/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s45/CLK
0.872	0.012	tHld		1	R33C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s45

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_27_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_27_s0/CLK
1.061	0.201	tC2Q	RF	2	R34C26[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_27_s0/Q
1.186	0.125	tNET	FF	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/CLK
0.872	0.012	tHld		1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_26_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[0][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_26_s0/CLK
1.061	0.201	tC2Q	RF	2	R34C26[0][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_26_s0/Q
1.186	0.125	tNET	FF	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/CLK
0.872	0.012	tHld		1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_25_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_25_s0/CLK
1.061	0.201	tC2Q	RF	2	R34C26[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_25_s0/Q
1.186	0.125	tNET	FF	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/CLK
0.872	0.012	tHld		1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_24_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C26[1][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_24_s0/CLK
1.061	0.201	tC2Q	RF	2	R34C26[1][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_24_s0/Q
1.186	0.125	tNET	FF	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37/CLK
0.872	0.012	tHld		1	R33C26	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_32_s0
To	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s41
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_32_s0/CLK
1.062	0.202	tC2Q	RR	2	R16C26[1][B]	CIC_Fliter_tb/CIC_Filter/comb[5].comb_inst/comb_out_32_s0/Q
1.186	0.124	tNET	RR	1	R14C26	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s41/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R14C26	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s41/CLK
0.872	0.012	tHld		1	R14C26	CIC_Fliter_tb/CIC_Filter/comb[6].comb_inst/buff_delay[0]_0_s41

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_37_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s43
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[2][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_37_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C28[2][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_37_s0/Q
1.186	0.124	tNET	RR	1	R32C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s43/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R32C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s43/CLK
0.872	0.012	tHld		1	R32C28	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s43

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.314
Data Arrival Time	1.186
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_34_s0
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s41
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R35C27[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_34_s0/CLK
1.062	0.202	tC2Q	RR	2	R35C27[1][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/buffer_out_34_s0/Q
1.186	0.124	tNET	RR	1	R33C27	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s41/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C27	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s41/CLK
0.872	0.012	tHld		1	R33C27	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s41

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.124, 38.121%; tC2Q: 0.202, 61.879%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.339
Data Arrival Time	1.210
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s33
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.062	0.202	tC2Q	RR	27	R31C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
1.210	0.149	tNET	RR	1	R33C24	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s33/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C24	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s33/CLK
0.872	0.012	tHld		1	R33C24	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s33

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 42.377%; tC2Q: 0.202, 57.623%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.339
Data Arrival Time	1.211
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s2
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s22
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R16C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s2/CLK
1.062	0.202	tC2Q	RR	29	R16C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s2/Q
1.211	0.149	tNET	RR	1	R15C38	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s22/AD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R15C38	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s22/CLK
0.872	0.012	tHld		1	R15C38	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s22

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 42.496%; tC2Q: 0.202, 57.504%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.341
Data Arrival Time	1.213
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s37
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R35C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s4/CLK
1.062	0.202	tC2Q	RR	27	R35C19[0][B]	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s4/Q
1.213	0.151	tNET	RR	1	R33C19	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s37/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C19	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s37/CLK
0.872	0.012	tHld		1	R33C19	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_0_s37

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.151, 42.776%; tC2Q: 0.202, 57.224%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.342
Data Arrival Time	1.214
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/CLK
1.062	0.202	tC2Q	RR	27	R26C24[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/Q
1.214	0.152	tNET	RR	1	R24C24	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C24	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/CLK
0.872	0.012	tHld		1	R24C24	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.152, 42.974%; tC2Q: 0.202, 57.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.363
Data Arrival Time	1.340
Data Required Time	0.978
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.062	0.202	tC2Q	RR	9	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.340	0.279	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.978	0.118	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.968%; tC2Q: 0.202, 42.032%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/CLK
1.062	0.202	tC2Q	RR	1	R18C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_61_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/CLK
1.062	0.202	tC2Q	RR	1	R18C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.364
Data Arrival Time	1.341
Data Required Time	0.978
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.062	0.202	tC2Q	RR	8	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.341	0.280	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/ADA[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.978	0.118	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.058%; tC2Q: 0.202, 41.942%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0
To	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/CLK
1.062	0.202	tC2Q	RR	3	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/Q
1.064	0.002	tNET	RR	1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/n14_s2/I0
1.296	0.232	tINS	RF	1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/n14_s2/F
1.296	0.000	tNET	FF	1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0/CLK
0.871	0.011	tHld		1	R38C25[0][A]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/CLK
1.062	0.202	tC2Q	RR	2	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/Q
1.064	0.002	tNET	RR	2	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/n48_s/I1
1.296	0.232	tINS	RF	1	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/n48_s/SUM
1.296	0.000	tNET	FF	1	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R36C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/CLK
1.062	0.202	tC2Q	RR	2	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/Q
1.064	0.002	tNET	RR	2	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/n44_s/I1
1.296	0.232	tINS	RF	1	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/n44_s/SUM
1.296	0.000	tNET	FF	1	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R36C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[7].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.946
Data Arrival Time	7.945
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.945	1.764	tNET	FF	1	R21C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.891	-0.035	tSu		1	R21C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.764, 88.375%; tC2Q: 0.232, 11.625%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.946
Data Arrival Time	7.945
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.945	1.764	tNET	FF	1	R21C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.891	-0.035	tSu		1	R21C41[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.764, 88.375%; tC2Q: 0.232, 11.625%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	2.946
Data Arrival Time	7.945
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.945	1.764	tNET	FF	1	R21C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.891	-0.035	tSu		1	R21C41[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.764, 88.375%; tC2Q: 0.232, 11.625%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	2.958
Data Arrival Time	7.933
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.933	1.752	tNET	FF	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.752, 88.308%; tC2Q: 0.232, 11.692%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	2.958
Data Arrival Time	7.933
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.933	1.752	tNET	FF	1	R21C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.891	-0.035	tSu		1	R21C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.752, 88.308%; tC2Q: 0.232, 11.692%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	2.958
Data Arrival Time	7.933
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.933	1.752	tNET	FF	1	R21C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.891	-0.035	tSu		1	R21C40[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.752, 88.308%; tC2Q: 0.232, 11.692%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.200
Data Arrival Time	7.690
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.690	1.510	tNET	FF	1	R26C38[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C38[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.891	-0.035	tSu		1	R26C38[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.510, 86.678%; tC2Q: 0.232, 13.322%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.200
Data Arrival Time	7.690
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.690	1.510	tNET	FF	1	R26C38[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C38[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.891	-0.035	tSu		1	R26C38[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.510, 86.678%; tC2Q: 0.232, 13.322%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.200
Data Arrival Time	7.690
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.690	1.510	tNET	FF	1	R26C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tSu		1	R26C38[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.510, 86.678%; tC2Q: 0.232, 13.322%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.200
Data Arrival Time	7.690
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.690	1.510	tNET	FF	1	R26C38[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C38[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
10.891	-0.035	tSu		1	R26C38[1][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.510, 86.678%; tC2Q: 0.232, 13.322%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.449
Data Arrival Time	7.442
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.442	1.261	tNET	FF	1	R21C37[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C37[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
10.891	-0.035	tSu		1	R21C37[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.261, 84.461%; tC2Q: 0.232, 15.539%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.449
Data Arrival Time	7.442
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.442	1.261	tNET	FF	1	R21C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
10.891	-0.035	tSu		1	R21C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.261, 84.461%; tC2Q: 0.232, 15.539%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.449
Data Arrival Time	7.442
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.442	1.261	tNET	FF	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tSu		1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.261, 84.461%; tC2Q: 0.232, 15.539%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	3.449
Data Arrival Time	7.442
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.442	1.261	tNET	FF	1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.891	-0.035	tSu		1	R26C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.261, 84.461%; tC2Q: 0.232, 15.539%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	3.449
Data Arrival Time	7.442
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.442	1.261	tNET	FF	1	R26C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R26C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.891	-0.035	tSu		1	R26C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.261, 84.461%; tC2Q: 0.232, 15.539%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	3.455
Data Arrival Time	7.436
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.436	1.255	tNET	FF	1	R21C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tSu		1	R21C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.255, 84.402%; tC2Q: 0.232, 15.598%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	3.455
Data Arrival Time	7.436
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.436	1.255	tNET	FF	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
10.891	-0.035	tSu		1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.255, 84.402%; tC2Q: 0.232, 15.598%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	3.460
Data Arrival Time	7.430
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.430	1.250	tNET	FF	1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tSu		1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.250, 84.341%; tC2Q: 0.232, 15.659%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.891	-0.035	tSu		1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.891	-0.035	tSu		1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
10.891	-0.035	tSu		1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tSu		1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tSu		1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	3.703
Data Arrival Time	7.188
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.188	1.007	tNET	FF	1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	973	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tSu		1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.007, 81.273%; tC2Q: 0.232, 18.727%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.467
Data Arrival Time	6.337
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.337	0.263	tNET	RR	1	R29C39[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C39[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R29C39[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.263, 56.595%; tC2Q: 0.202, 43.405%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.467
Data Arrival Time	6.337
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.337	0.263	tNET	RR	1	R29C39[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C39[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R29C39[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.263, 56.595%; tC2Q: 0.202, 43.405%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.470
Data Arrival Time	6.340
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.340	0.266	tNET	RR	1	R29C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R29C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.266, 56.873%; tC2Q: 0.202, 43.127%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.595
Data Arrival Time	6.465
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.465	0.391	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.391, 65.958%; tC2Q: 0.202, 34.042%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.595
Data Arrival Time	6.465
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.465	0.391	tNET	RR	1	R29C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R29C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.391, 65.958%; tC2Q: 0.202, 34.042%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.595
Data Arrival Time	6.465
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.465	0.391	tNET	RR	1	R29C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R29C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.391, 65.958%; tC2Q: 0.202, 34.042%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.595
Data Arrival Time	6.465
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.465	0.391	tNET	RR	1	R29C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R29C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.391, 65.958%; tC2Q: 0.202, 34.042%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.595
Data Arrival Time	6.465
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.465	0.391	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
0.871	0.011	tHld		1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.391, 65.958%; tC2Q: 0.202, 34.042%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.726
Data Arrival Time	6.596
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.596	0.522	tNET	RR	1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R27C40[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.522, 72.112%; tC2Q: 0.202, 27.888%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.726
Data Arrival Time	6.596
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.596	0.522	tNET	RR	1	R27C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R27C40[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.522, 72.112%; tC2Q: 0.202, 27.888%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.726
Data Arrival Time	6.596
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.596	0.522	tNET	RR	1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R27C40[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.522, 72.112%; tC2Q: 0.202, 27.888%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.871	0.011	tHld		1	R22C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.871	0.011	tHld		1	R22C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871	0.011	tHld		1	R22C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.871	0.011	tHld		1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.871	0.011	tHld		1	R20C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871	0.011	tHld		1	R20C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.871	0.011	tHld		1	R20C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
0.871	0.011	tHld		1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871	0.011	tHld		1	R20C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
0.871	0.011	tHld		1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
0.871	0.011	tHld		1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.871	0.011	tHld		1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871	0.011	tHld		1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.862
Data Arrival Time	6.733
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	973	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R29C41[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.733	0.659	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	973	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871	0.011	tHld		1	R21C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.659, 76.545%; tC2Q: 0.202, 23.455%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_9_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_7_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_3_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_7_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	i_data_7_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	i_data_7_s1/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_34_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_34_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_34_s0/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_2_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[2].integrator_inst/add_out_20_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_15_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_15_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_15_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_23_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_23_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_23_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/comb_out_24_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
973	clk_d	2.946	0.261
339	control0[0]	2.797	0.912
330	in_valid	7.792	1.941
85	n20_3	45.776	2.406
65	data_out_shift_reg_62_7	45.449	1.213
63	n824_5	44.937	1.290
59	comb_vaild_5[6]	8.128	1.003
59	down_vaild	7.211	1.576
59	comb_vaild_4[5]	7.036	2.039
59	comb_vaild_3[4]	7.114	1.596

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R16C22	91.67%
R34C18	90.28%
R16C26	88.89%
R17C17	88.89%
R29C35	88.89%
R17C22	87.50%
R17C28	87.50%
R17C30	87.50%
R16C24	87.50%
R34C21	87.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]