Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\3_9_4_7_63\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 10:53:39 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	3953
Numbers of Endpoints Analyzed	4350
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	194.195(MHz)	6	TOP
2	tck_pad_i	20.000(MHz)	79.257(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.793	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.776
2	2.797	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.772
3	4.095	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.614
4	4.198	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.511
5	4.198	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.511
6	4.211	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.498
7	4.219	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.490
8	4.230	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.479
9	4.232	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.477
10	4.319	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.390
11	4.319	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.390
12	4.417	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.292
13	4.888	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.821
14	4.928	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.781
15	5.078	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.631
16	5.167	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.542
17	5.278	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.431
18	5.441	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.268
19	5.441	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.268
20	5.444	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_58_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.521
21	5.479	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.486
22	5.514	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.451
23	5.549	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.160
24	5.549	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.160
25	5.550	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.415

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
5	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
6	0.320	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.569
7	0.324	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[17]	clk:[R]	clk:[R]	0.000	0.000	0.573
8	0.325	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[0]	clk:[R]	clk:[R]	0.000	0.000	0.337
9	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_75_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.584
10	0.335	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.584
11	0.337	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.586
12	0.337	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.586
13	0.355	gw_gao_inst_0/u_la0_top/triger_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.604
14	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.612
15	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]	clk:[R]	clk:[R]	0.000	0.000	0.612
16	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[15]	clk:[R]	clk:[R]	0.000	0.000	0.612
17	0.378	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.627
18	0.378	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[16]	clk:[R]	clk:[R]	0.000	0.000	0.627
19	0.425	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
20	0.425	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
21	0.425	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
22	0.425	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
23	0.425	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
24	0.425	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
25	0.425	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.738	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.204
2	3.738	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.204
3	3.783	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.159
4	3.968	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.974
5	3.968	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.974
6	3.968	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.974
7	3.968	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.974
8	3.968	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.974
9	3.983	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.959
10	3.983	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.959
11	3.983	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.959
12	3.988	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953
13	3.998	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.944
14	4.001	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.941
15	4.001	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.941
16	4.006	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	0.936
17	4.006	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.936
18	4.014	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.928
19	4.017	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.925
20	4.017	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.925
21	4.026	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.916
22	4.026	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.916
23	4.026	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.916
24	4.026	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.916
25	4.026	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.916

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.463	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	-5.000	0.012	0.462
2	5.468	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.467
3	5.468	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.467
4	5.468	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.467
5	5.476	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.475
6	5.477	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
7	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
8	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
9	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
10	5.478	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
11	5.480	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.479
12	5.480	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.479
13	5.482	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.481
14	5.482	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.481
15	5.482	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.481
16	5.482	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.481
17	5.483	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
18	5.483	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
19	5.483	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
20	5.483	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
21	5.483	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
22	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.594
23	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.594
24	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.594
25	5.595	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.594

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_14_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_12_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_8_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	counter_0_s0
5	3.911	4.911	1.000	Low Pulse Width	clk	i_data_2_s1
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_0_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_1_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_9_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_11_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_12_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.793
Data Arrival Time	28.062
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R26C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R26C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.062	0.544	tNET	FF	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.544, 70.088%; tC2Q: 0.232, 29.912%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.797
Data Arrival Time	28.059
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R27C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.059	0.540	tNET	FF	1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.540, 69.961%; tC2Q: 0.232, 30.039%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	4.095
Data Arrival Time	6.761
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.067	0.426	tNET	FF	1	R25C38[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
6.616	0.549	tINS	FR	1	R25C38[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
6.761	0.144	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.856	-0.035	tSu		1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.074, 44.952%; route: 2.308, 50.020%; tC2Q: 0.232, 5.028%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.198
Data Arrival Time	6.658
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.088	0.447	tNET	FF	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n552_s1/I2
6.658	0.570	tINS	FR	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n552_s1/F
6.658	0.000	tNET	RR	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.856	-0.035	tSu		1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.095, 46.441%; route: 2.184, 48.416%; tC2Q: 0.232, 5.143%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.198
Data Arrival Time	6.658
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.088	0.447	tNET	FF	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n551_s1/I3
6.658	0.570	tINS	FR	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n551_s1/F
6.658	0.000	tNET	RR	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.856	-0.035	tSu		1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.095, 46.441%; route: 2.184, 48.416%; tC2Q: 0.232, 5.143%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.211
Data Arrival Time	6.645
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.075	0.434	tNET	FF	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n555_s1/I2
6.645	0.570	tINS	FR	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n555_s1/F
6.645	0.000	tNET	RR	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
10.856	-0.035	tSu		1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.095, 46.577%; route: 2.171, 48.265%; tC2Q: 0.232, 5.158%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.219
Data Arrival Time	6.637
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.088	0.447	tNET	FF	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n556_s1/I3
6.637	0.549	tINS	FR	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n556_s1/F
6.637	0.000	tNET	RR	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
10.856	-0.035	tSu		1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.074, 46.190%; route: 2.184, 48.643%; tC2Q: 0.232, 5.167%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.230
Data Arrival Time	6.625
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.076	0.435	tNET	FF	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n553_s1/I3
6.625	0.549	tINS	FR	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n553_s1/F
6.625	0.000	tNET	RR	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.074, 46.309%; route: 2.173, 48.511%; tC2Q: 0.232, 5.180%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.232
Data Arrival Time	6.624
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.075	0.434	tNET	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s1/I2
6.624	0.549	tINS	FR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s1/F
6.624	0.000	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
10.856	-0.035	tSu		1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.074, 46.326%; route: 2.171, 48.492%; tC2Q: 0.232, 5.182%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.319
Data Arrival Time	6.537
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.075	0.434	tNET	FF	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n557_s1/I2
6.537	0.462	tINS	FR	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n557_s1/F
6.537	0.000	tNET	RR	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.856	-0.035	tSu		1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.987, 45.263%; route: 2.171, 49.453%; tC2Q: 0.232, 5.285%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.319
Data Arrival Time	6.537
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.075	0.434	tNET	FF	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n554_s1/I2
6.537	0.462	tINS	FR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n554_s1/F
6.537	0.000	tNET	RR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10.856	-0.035	tSu		1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.987, 45.263%; route: 2.171, 49.453%; tC2Q: 0.232, 5.285%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.417
Data Arrival Time	6.438
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.124	0.418	tNET	FF	1	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/I0
5.641	0.517	tINS	FF	10	R23C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s4/F
6.067	0.426	tNET	FF	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n550_s1/I3
6.438	0.371	tINS	FF	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n550_s1/F
6.438	0.000	tNET	FF	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
10.856	-0.035	tSu		1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.896, 44.179%; route: 2.164, 50.415%; tC2Q: 0.232, 5.406%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.888
Data Arrival Time	5.968
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/CLK
2.379	0.232	tC2Q	RF	3	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q
3.438	1.060	tNET	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I1
3.955	0.517	tINS	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
4.595	0.640	tNET	FF	1	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
5.144	0.549	tINS	FR	3	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.321	0.177	tNET	RR	1	R20C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
5.783	0.462	tINS	RR	1	R20C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
5.968	0.185	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
10.856	-0.035	tSu		1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.528, 39.986%; route: 2.061, 53.943%; tC2Q: 0.232, 6.071%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.928
Data Arrival Time	5.927
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/CLK
2.379	0.232	tC2Q	RF	3	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q
3.438	1.060	tNET	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I1
3.955	0.517	tINS	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
4.595	0.640	tNET	FF	1	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
5.144	0.549	tINS	FR	3	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.321	0.177	tNET	RR	1	R20C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
5.783	0.462	tINS	RR	1	R20C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
5.927	0.144	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.528, 40.417%; route: 2.021, 53.446%; tC2Q: 0.232, 6.137%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	5.078
Data Arrival Time	5.778
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C33[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_0_s0/Q
3.285	0.907	tNET	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/I3
3.738	0.453	tINS	FF	1	R22C35[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s10/F
4.151	0.413	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/I2
4.706	0.555	tINS	FF	2	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n549_s6/F
5.229	0.522	tNET	FF	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n558_s2/I1
5.778	0.549	tINS	FR	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n558_s2/F
5.778	0.000	tNET	RR	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
10.856	-0.035	tSu		1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.557, 42.879%; route: 1.842, 50.731%; tC2Q: 0.232, 6.389%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	5.167
Data Arrival Time	5.689
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/CLK
2.379	0.232	tC2Q	RF	3	R27C34[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_1_s0/Q
3.438	1.060	tNET	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/I1
3.955	0.517	tINS	FF	1	R24C37[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s9/F
4.595	0.640	tNET	FF	1	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I3
5.144	0.549	tINS	FR	3	R20C37[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.318	0.174	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n449_s3/I1
5.689	0.371	tINS	RF	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n449_s3/F
5.689	0.000	tNET	FF	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.437, 40.568%; route: 1.873, 52.883%; tC2Q: 0.232, 6.550%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	5.278
Data Arrival Time	5.578
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.280	0.901	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/I1
3.835	0.555	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/COUT
4.488	0.654	tNET	FF	1	R27C37[0][B]	gw_gao_inst_0/u_la0_top/n3153_s1/I0
4.859	0.371	tINS	FF	1	R27C37[0][B]	gw_gao_inst_0/u_la0_top/n3153_s1/F
4.864	0.004	tNET	FF	1	R27C37[1][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.434	0.570	tINS	FR	1	R27C37[1][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
5.578	0.144	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.496, 43.603%; route: 1.703, 49.635%; tC2Q: 0.232, 6.762%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	5.441
Data Arrival Time	5.415
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.280	0.901	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/I1
3.835	0.555	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/COUT
4.488	0.654	tNET	FF	1	R27C35[3][A]	gw_gao_inst_0/u_la0_top/n3133_s2/I1
4.950	0.462	tINS	FR	2	R27C35[3][A]	gw_gao_inst_0/u_la0_top/n3133_s2/F
4.953	0.003	tNET	RR	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/n3131_s3/I3
5.415	0.462	tINS	RR	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/n3131_s3/F
5.415	0.000	tNET	RR	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
10.856	-0.035	tSu		1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.479, 45.256%; route: 1.557, 47.645%; tC2Q: 0.232, 7.099%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	5.441
Data Arrival Time	5.415
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.280	0.901	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/I1
3.835	0.555	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/COUT
4.488	0.654	tNET	FF	1	R27C35[3][A]	gw_gao_inst_0/u_la0_top/n3133_s2/I1
4.950	0.462	tINS	FR	2	R27C35[3][A]	gw_gao_inst_0/u_la0_top/n3133_s2/F
4.953	0.003	tNET	RR	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n3130_s1/I3
5.415	0.462	tINS	RR	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n3130_s1/F
5.415	0.000	tNET	RR	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
10.856	-0.035	tSu		1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.479, 45.256%; route: 1.557, 47.645%; tC2Q: 0.232, 7.099%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	5.444
Data Arrival Time	5.447
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_58_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.146	0.960	tNET	FF	2	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/I0
4.695	0.549	tINS	FR	1	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
4.695	0.000	tNET	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
4.730	0.035	tINS	RF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
4.730	0.000	tNET	FF	2	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
4.766	0.035	tINS	FF	1	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
4.766	0.000	tNET	FF	2	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
4.801	0.035	tINS	FF	1	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
4.801	0.000	tNET	FF	2	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
4.836	0.035	tINS	FF	1	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
4.836	0.000	tNET	FF	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
4.871	0.035	tINS	FF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
4.871	0.000	tNET	FF	2	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
4.906	0.035	tINS	FF	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
4.906	0.000	tNET	FF	2	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
4.942	0.035	tINS	FF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
4.942	0.000	tNET	FF	2	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
4.977	0.035	tINS	FF	1	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/COUT
4.977	0.000	tNET	FF	2	R34C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n67_s/CIN
5.447	0.470	tINS	FF	1	R34C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n67_s/SUM
5.447	0.000	tNET	FF	1	R34C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_58_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R34C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_58_s0/CLK
10.891	-0.035	tSu		1	R34C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_58_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.301, 28.768%; route: 0.960, 21.243%; tC2Q: 2.260, 49.989%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	5.479
Data Arrival Time	5.412
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.146	0.960	tNET	FF	2	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/I0
4.695	0.549	tINS	FR	1	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
4.695	0.000	tNET	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
4.730	0.035	tINS	RF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
4.730	0.000	tNET	FF	2	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
4.766	0.035	tINS	FF	1	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
4.766	0.000	tNET	FF	2	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
4.801	0.035	tINS	FF	1	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
4.801	0.000	tNET	FF	2	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
4.836	0.035	tINS	FF	1	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
4.836	0.000	tNET	FF	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
4.871	0.035	tINS	FF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
4.871	0.000	tNET	FF	2	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
4.906	0.035	tINS	FF	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
4.906	0.000	tNET	FF	2	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
4.942	0.035	tINS	FF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/COUT
4.942	0.000	tNET	FF	2	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/CIN
5.412	0.470	tINS	FF	1	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n117_s/SUM
5.412	0.000	tNET	FF	1	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/CLK
10.891	-0.035	tSu		1	R34C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.265, 28.209%; route: 0.960, 21.410%; tC2Q: 2.260, 50.381%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	5.514
Data Arrival Time	5.376
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.146	0.960	tNET	FF	2	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/I0
4.695	0.549	tINS	FR	1	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
4.695	0.000	tNET	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
4.730	0.035	tINS	RF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
4.730	0.000	tNET	FF	2	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
4.766	0.035	tINS	FF	1	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
4.766	0.000	tNET	FF	2	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
4.801	0.035	tINS	FF	1	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
4.801	0.000	tNET	FF	2	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
4.836	0.035	tINS	FF	1	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
4.836	0.000	tNET	FF	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
4.871	0.035	tINS	FF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
4.871	0.000	tNET	FF	2	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
4.906	0.035	tINS	FF	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/COUT
4.906	0.000	tNET	FF	2	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/CIN
5.376	0.470	tINS	FF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n118_s/SUM
5.376	0.000	tNET	FF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/CLK
10.891	-0.035	tSu		1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.230, 27.641%; route: 0.960, 21.579%; tC2Q: 2.260, 50.780%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	5.549
Data Arrival Time	5.307
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.280	0.901	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/I1
3.835	0.555	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/COUT
4.737	0.902	tNET	FF	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/n3133_s5/I2
5.307	0.570	tINS	FR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/n3133_s5/F
5.307	0.000	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
10.856	-0.035	tSu		1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.125, 35.603%; route: 1.803, 57.055%; tC2Q: 0.232, 7.342%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	5.549
Data Arrival Time	5.307
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	387	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R21C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_3_s0/Q
3.280	0.901	tNET	FF	2	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/I1
3.835	0.555	tINS	FF	5	R27C36[2][A]	gw_gao_inst_0/u_la0_top/n3111_s0/COUT
4.737	0.902	tNET	FF	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/n3153_s2/I1
5.307	0.570	tINS	FR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/n3153_s2/F
5.307	0.000	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_s0
10.856	-0.035	tSu		1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.125, 35.603%; route: 1.803, 57.055%; tC2Q: 0.232, 7.342%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	5.550
Data Arrival Time	5.341
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.146	0.960	tNET	FF	2	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/I0
4.695	0.549	tINS	FR	1	R34C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n125_s/COUT
4.695	0.000	tNET	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/CIN
4.730	0.035	tINS	RF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n124_s/COUT
4.730	0.000	tNET	FF	2	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/CIN
4.766	0.035	tINS	FF	1	R34C29[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n123_s/COUT
4.766	0.000	tNET	FF	2	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/CIN
4.801	0.035	tINS	FF	1	R34C29[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n122_s/COUT
4.801	0.000	tNET	FF	2	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/CIN
4.836	0.035	tINS	FF	1	R34C29[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n121_s/COUT
4.836	0.000	tNET	FF	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/CIN
4.871	0.035	tINS	FF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n120_s/COUT
4.871	0.000	tNET	FF	2	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/CIN
5.341	0.470	tINS	FF	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n119_s/SUM
5.341	0.000	tNET	FF	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/CLK
10.891	-0.035	tSu		1	R34C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.195, 27.064%; route: 0.960, 21.751%; tC2Q: 2.260, 51.185%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	12	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	12	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	12	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	12	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	12	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.320
Data Arrival Time	1.429
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/CLK
1.062	0.202	tC2Q	RR	1	R26C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q
1.429	0.367	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.367, 64.513%; tC2Q: 0.202, 35.487%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.324
Data Arrival Time	1.433
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_71_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/CLK
1.062	0.202	tC2Q	RR	1	R26C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_71_s0/Q
1.433	0.371	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.371, 64.759%; tC2Q: 0.202, 35.241%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.325
Data Arrival Time	1.197
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R35C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/CLK
1.062	0.202	tC2Q	RR	12	R35C29[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s2/Q
1.197	0.135	tNET	RR	1	R33C29	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/AD[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R33C29	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27/CLK
0.872	0.012	tHld		1	R33C29	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s27

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 40.119%; tC2Q: 0.202, 59.881%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_75_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_75_s0/CLK
1.062	0.202	tC2Q	RR	1	R25C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_75_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.335
Data Arrival Time	1.444
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/CLK
1.062	0.202	tC2Q	RR	1	R25C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_72_s0/Q
1.444	0.382	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.337
Data Arrival Time	1.445
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/CLK
1.061	0.201	tC2Q	RF	1	R26C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_78_s0/Q
1.445	0.385	tNET	FF	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.385, 65.673%; tC2Q: 0.201, 34.327%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.337
Data Arrival Time	1.445
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/CLK
1.061	0.201	tC2Q	RF	1	R26C40[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_76_s0/Q
1.445	0.385	tNET	FF	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.385, 65.673%; tC2Q: 0.201, 34.327%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.355
Data Arrival Time	1.464
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/triger_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.062	0.202	tC2Q	RR	11	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/Q
1.464	0.402	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.563%; tC2Q: 0.202, 33.437%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_79_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_69_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.378
Data Arrival Time	1.487
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_80_s0/Q
1.487	0.425	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[11]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.425, 67.773%; tC2Q: 0.202, 32.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.378
Data Arrival Time	1.487
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_70_s0/Q
1.487	0.425	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.425, 67.773%; tC2Q: 0.202, 32.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/CLK
1.062	0.202	tC2Q	RR	3	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/Q
1.064	0.002	tNET	RR	2	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n56_s/I1
1.296	0.232	tINS	RF	1	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n56_s/SUM
1.296	0.000	tNET	FF	1	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0/CLK
0.871	0.011	tHld		1	R20C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/CLK
1.062	0.202	tC2Q	RR	3	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/Q
1.064	0.002	tNET	RR	2	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n26_s/I1
1.296	0.232	tINS	RF	1	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/n26_s/SUM
1.296	0.000	tNET	FF	1	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0/CLK
0.871	0.011	tHld		1	R20C35[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[6].integrator_inst/add_out_41_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/CLK
1.062	0.202	tC2Q	RR	2	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/Q
1.064	0.002	tNET	RR	2	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n66_s/I1
1.296	0.232	tINS	RF	1	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n66_s/SUM
1.296	0.000	tNET	FF	1	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R21C25[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/CLK
1.062	0.202	tC2Q	RR	2	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/Q
1.064	0.002	tNET	RR	2	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n62_s/I1
1.296	0.232	tINS	RF	1	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n62_s/SUM
1.296	0.000	tNET	FF	1	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R21C26[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/CLK
1.062	0.202	tC2Q	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/Q
1.064	0.002	tNET	RR	2	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n60_s/I1
1.296	0.232	tINS	RF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n60_s/SUM
1.296	0.000	tNET	FF	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R21C26[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/CLK
1.062	0.202	tC2Q	RR	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/Q
1.064	0.002	tNET	RR	2	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n56_s/I1
1.296	0.232	tINS	RF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n56_s/SUM
1.296	0.000	tNET	FF	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0/CLK
0.871	0.011	tHld		1	R21C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/CLK
1.062	0.202	tC2Q	RR	2	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/Q
1.064	0.002	tNET	RR	2	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n54_s/I1
1.296	0.232	tINS	RF	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/n54_s/SUM
1.296	0.000	tNET	FF	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0/CLK
0.871	0.011	tHld		1	R21C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.738
Data Arrival Time	7.153
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.153	0.972	tNET	FF	1	R18C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.891	-0.035	tSu		1	R18C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.972, 80.731%; tC2Q: 0.232, 19.269%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.738
Data Arrival Time	7.153
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.153	0.972	tNET	FF	1	R18C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R18C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
10.891	-0.035	tSu		1	R18C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.972, 80.731%; tC2Q: 0.232, 19.269%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.783
Data Arrival Time	7.108
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.108	0.927	tNET	FF	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.891	-0.035	tSu		1	R29C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.927, 79.983%; tC2Q: 0.232, 20.017%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.968
Data Arrival Time	6.923
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.923	0.742	tNET	FF	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R21C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.742, 76.181%; tC2Q: 0.232, 23.819%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.968
Data Arrival Time	6.923
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.923	0.742	tNET	FF	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tSu		1	R21C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.742, 76.181%; tC2Q: 0.232, 23.819%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.968
Data Arrival Time	6.923
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.923	0.742	tNET	FF	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tSu		1	R21C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.742, 76.181%; tC2Q: 0.232, 23.819%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.968
Data Arrival Time	6.923
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.923	0.742	tNET	FF	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tSu		1	R21C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.742, 76.181%; tC2Q: 0.232, 23.819%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.968
Data Arrival Time	6.923
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.923	0.742	tNET	FF	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tSu		1	R21C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.742, 76.181%; tC2Q: 0.232, 23.819%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.983
Data Arrival Time	6.908
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.908	0.727	tNET	FF	1	R27C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.891	-0.035	tSu		1	R27C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.727, 75.814%; tC2Q: 0.232, 24.186%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.983
Data Arrival Time	6.908
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.908	0.727	tNET	FF	1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.891	-0.035	tSu		1	R27C34[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.727, 75.814%; tC2Q: 0.232, 24.186%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.983
Data Arrival Time	6.908
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.908	0.727	tNET	FF	1	R27C34[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C34[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.891	-0.035	tSu		1	R27C34[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.727, 75.814%; tC2Q: 0.232, 24.186%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.988
Data Arrival Time	6.902
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.902	0.721	tNET	FF	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tSu		1	R20C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.668%; tC2Q: 0.232, 24.332%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.998
Data Arrival Time	6.893
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.893	0.712	tNET	FF	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tSu		1	R20C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.712, 75.435%; tC2Q: 0.232, 24.565%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.001
Data Arrival Time	6.890
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.890	0.709	tNET	FF	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tSu		1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.709, 75.345%; tC2Q: 0.232, 24.655%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.001
Data Arrival Time	6.890
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.890	0.709	tNET	FF	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tSu		1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.709, 75.345%; tC2Q: 0.232, 24.655%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	4.006
Data Arrival Time	6.885
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.885	0.704	tNET	FF	1	R22C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R22C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.704, 75.216%; tC2Q: 0.232, 24.784%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	4.006
Data Arrival Time	6.885
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.885	0.704	tNET	FF	1	R22C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.891	-0.035	tSu		1	R22C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.704, 75.216%; tC2Q: 0.232, 24.784%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	4.014
Data Arrival Time	6.877
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.877	0.696	tNET	FF	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
10.891	-0.035	tSu		1	R20C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.696, 75.007%; tC2Q: 0.232, 24.993%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	4.017
Data Arrival Time	6.874
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.874	0.693	tNET	FF	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.891	-0.035	tSu		1	R29C37[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.693, 74.928%; tC2Q: 0.232, 25.072%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	4.017
Data Arrival Time	6.874
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.874	0.693	tNET	FF	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
10.891	-0.035	tSu		1	R29C37[0][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.693, 74.928%; tC2Q: 0.232, 25.072%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	4.026
Data Arrival Time	6.865
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.865	0.684	tNET	FF	1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.891	-0.035	tSu		1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 74.666%; tC2Q: 0.232, 25.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	4.026
Data Arrival Time	6.865
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.865	0.684	tNET	FF	1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.891	-0.035	tSu		1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 74.666%; tC2Q: 0.232, 25.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	4.026
Data Arrival Time	6.865
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.865	0.684	tNET	FF	1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.891	-0.035	tSu		1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 74.666%; tC2Q: 0.232, 25.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	4.026
Data Arrival Time	6.865
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.865	0.684	tNET	FF	1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
10.891	-0.035	tSu		1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 74.666%; tC2Q: 0.232, 25.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	4.026
Data Arrival Time	6.865
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.865	0.684	tNET	FF	1	R22C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	995	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
10.891	-0.035	tSu		1	R22C39[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.684, 74.666%; tC2Q: 0.232, 25.334%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.463
Data Arrival Time	6.334
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.334	0.260	tNET	RR	1	R26C40[1][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C40[1][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
0.871	0.011	tHld		1	R26C40[1][B]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.260, 56.295%; tC2Q: 0.202, 43.705%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.468
Data Arrival Time	6.339
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.339	0.265	tNET	RR	1	R26C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871	0.011	tHld		1	R26C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 56.760%; tC2Q: 0.202, 43.240%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.468
Data Arrival Time	6.339
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.339	0.265	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871	0.011	tHld		1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 56.760%; tC2Q: 0.202, 43.240%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.468
Data Arrival Time	6.339
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.339	0.265	tNET	RR	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R26C37[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.265, 56.760%; tC2Q: 0.202, 43.240%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.476
Data Arrival Time	6.347
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.347	0.273	tNET	RR	1	R27C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R27C40[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.273, 57.434%; tC2Q: 0.202, 42.566%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.477
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R25C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871	0.011	tHld		1	R25C40[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.538%; tC2Q: 0.202, 42.462%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R27C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R27C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.598%; tC2Q: 0.202, 42.402%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R27C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R27C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.598%; tC2Q: 0.202, 42.402%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R27C38[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C38[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R27C38[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.598%; tC2Q: 0.202, 42.402%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.478
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R27C38[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C38[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R27C38[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.598%; tC2Q: 0.202, 42.402%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.480
Data Arrival Time	6.351
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.351	0.277	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871	0.011	tHld		1	R25C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.804%; tC2Q: 0.202, 42.196%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.480
Data Arrival Time	6.351
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.351	0.277	tNET	RR	1	R25C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871	0.011	tHld		1	R25C38[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.277, 57.804%; tC2Q: 0.202, 42.196%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.482
Data Arrival Time	6.353
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.353	0.279	tNET	RR	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.965%; tC2Q: 0.202, 42.035%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.482
Data Arrival Time	6.353
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.353	0.279	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.965%; tC2Q: 0.202, 42.035%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.482
Data Arrival Time	6.353
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.353	0.279	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.965%; tC2Q: 0.202, 42.035%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.482
Data Arrival Time	6.353
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.353	0.279	tNET	RR	1	R27C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R27C37[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.279, 57.965%; tC2Q: 0.202, 42.035%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.483
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.871	0.011	tHld		1	R25C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.067%; tC2Q: 0.202, 41.933%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.483
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.871	0.011	tHld		1	R25C37[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.067%; tC2Q: 0.202, 41.933%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.483
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871	0.011	tHld		1	R25C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.067%; tC2Q: 0.202, 41.933%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.483
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.871	0.011	tHld		1	R25C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.067%; tC2Q: 0.202, 41.933%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.483
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
0.871	0.011	tHld		1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.067%; tC2Q: 0.202, 41.933%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.595
Data Arrival Time	6.466
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.466	0.392	tNET	RR	1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.871	0.011	tHld		1	R22C39[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 66.001%; tC2Q: 0.202, 33.999%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.595
Data Arrival Time	6.466
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.466	0.392	tNET	RR	1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.871	0.011	tHld		1	R22C39[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 66.001%; tC2Q: 0.202, 33.999%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.595
Data Arrival Time	6.466
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.466	0.392	tNET	RR	1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871	0.011	tHld		1	R22C39[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 66.001%; tC2Q: 0.202, 33.999%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.595
Data Arrival Time	6.466
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	995	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R26C39[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.466	0.392	tNET	RR	1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	995	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871	0.011	tHld		1	R22C39[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.392, 66.001%; tC2Q: 0.202, 33.999%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_14_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_12_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_8_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_0_s0/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_2_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	i_data_2_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	i_data_2_s1/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/comb_out_0_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_1_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_9_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_11_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_12_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
995	clk_d	3.738	0.261
387	control0[0]	2.793	0.912
103	n20_3	46.758	1.357
81	n915_5	43.724	1.270
81	data_out_shift_reg_80_9	44.645	0.967
77	comb_vaild_4[5]	8.332	1.401
72	comb_vaild_3[4]	8.242	1.491
68	n915_4	43.724	1.607
67	comb_vaild_2[3]	8.374	1.359
62	comb_vaild_1[2]	8.833	0.900

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R20C35	90.28%
R26C35	90.28%
R20C34	88.89%
R31C33	88.89%
R22C37	87.50%
R11C32	87.50%
R29C39	87.50%
R18C33	86.11%
R21C32	86.11%
R22C35	86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]