Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\2_9_4_8_3\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\2_9_4_8_3\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\2_9_4_8_3\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 10:44:21 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	3701
Numbers of Endpoints Analyzed	4033
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	185.320(MHz)	5	TOP
2	tck_pad_i	20.000(MHz)	109.743(MHz)	5	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.308	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	1.261
2	2.797	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.772
3	3.093	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	5.616
4	3.856	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.853
5	3.856	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.853
6	3.932	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.777
7	3.946	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.763
8	4.023	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.686
9	4.023	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.686
10	4.099	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.610
11	4.280	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.429
12	4.496	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.213
13	4.593	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.116
14	4.810	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.899
15	4.910	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.799
16	5.073	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.637
17	5.129	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.580
18	5.487	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_38_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.478
19	5.522	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.443
20	5.557	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.408
21	5.592	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.373
22	5.628	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.337
23	5.663	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_4_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.302
24	5.698	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_3_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.267
25	5.733	mem_data_mem_data_0_0_s/DO[0]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_2_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.232

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.074	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15]	clk:[R]	clk:[R]	0.000	0.000	0.323
2	0.080	gw_gao_inst_0/u_la0_top/triger_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[10]	clk:[R]	clk:[R]	0.000	0.000	0.329
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
5	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
6	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
7	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14]	clk:[R]	clk:[R]	0.000	0.000	0.474
8	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[13]	clk:[R]	clk:[R]	0.000	0.000	0.474
9	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_0_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
10	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
11	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_2_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
12	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_3_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
13	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_4_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
14	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
15	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_6_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
16	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
17	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_8_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
18	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_9_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
19	0.323	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_10_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.334
20	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_5_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336
21	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_6_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336
22	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_7_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336
23	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_8_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336
24	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_9_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336
25	0.325	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_10_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.336

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.916	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	2.026
2	3.159	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.783
3	3.159	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.783
4	3.491	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.451
5	3.491	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.451
6	3.491	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.451
7	3.527	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.415
8	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
9	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
10	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
11	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
12	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
13	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
14	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
15	3.734	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.208
16	3.742	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.200
17	3.742	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	5.000	0.023	1.200
18	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
19	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
20	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
21	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
22	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
23	3.837	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.105
24	3.989	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	0.953
25	3.989	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.340	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.339
2	5.340	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.339
3	5.340	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.339
4	5.457	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.456
5	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
6	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
7	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
8	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
9	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
10	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
11	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
12	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
13	5.467	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
14	5.484	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
15	5.484	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.482
16	5.579	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.578
17	5.579	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.578
18	5.616	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.615
19	5.616	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.615
20	5.616	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.615
21	5.626	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	-5.000	0.012	0.625
22	5.626	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.625
23	5.626	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.625
24	5.754	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.753
25	5.754	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.753

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_10_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_8_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_4_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	i_data_10_s1
5	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_3_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_1_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_3_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.308
Data Arrival Time	28.548
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C31[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R27C31[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.548	1.029	tNET	FF	1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.029, 81.603%; tC2Q: 0.232, 18.397%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.797
Data Arrival Time	28.059
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C31[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R27C31[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.059	0.540	tNET	FF	1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.540, 69.961%; tC2Q: 0.232, 30.039%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.093
Data Arrival Time	7.763
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.713	0.944	tNET	FF	1	R25C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
7.040	0.327	tINS	FR	1	R25C33[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
7.763	0.724	tNET	RR	1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.856	-0.035	tSu		1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.992, 35.468%; route: 3.392, 60.401%; tC2Q: 0.232, 4.131%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.856
Data Arrival Time	7.000
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.451	0.682	tNET	FF	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n467_s1/I3
7.000	0.549	tINS	FR	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n467_s1/F
7.000	0.000	tNET	RR	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.856	-0.035	tSu		1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 45.621%; route: 2.407, 49.598%; tC2Q: 0.232, 4.781%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.856
Data Arrival Time	7.000
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.451	0.682	tNET	FF	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n465_s1/I3
7.000	0.549	tINS	FR	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n465_s1/F
7.000	0.000	tNET	RR	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
10.856	-0.035	tSu		1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 45.621%; route: 2.407, 49.598%; tC2Q: 0.232, 4.781%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.932
Data Arrival Time	6.924
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.462	0.694	tNET	FF	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s3/I3
6.924	0.462	tINS	FR	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n468_s3/F
6.924	0.000	tNET	RR	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.127, 44.521%; route: 2.418, 50.623%; tC2Q: 0.232, 4.856%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.946
Data Arrival Time	6.909
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.447	0.679	tNET	FF	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n472_s1/I2
6.909	0.462	tINS	FR	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n472_s1/F
6.909	0.000	tNET	RR	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.856	-0.035	tSu		1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.127, 44.659%; route: 2.404, 50.469%; tC2Q: 0.232, 4.871%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.023
Data Arrival Time	6.833
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.462	0.694	tNET	FF	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n471_s1/I3
6.833	0.371	tINS	FF	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n471_s1/F
6.833	0.000	tNET	FF	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
10.856	-0.035	tSu		1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.036, 43.444%; route: 2.418, 51.606%; tC2Q: 0.232, 4.950%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.023
Data Arrival Time	6.833
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.462	0.694	tNET	FF	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n466_s1/I3
6.833	0.371	tINS	FF	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n466_s1/F
6.833	0.000	tNET	FF	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.856	-0.035	tSu		1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.036, 43.444%; route: 2.418, 51.606%; tC2Q: 0.232, 4.950%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.099
Data Arrival Time	6.757
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.208	0.440	tNET	FF	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s1/I3
6.757	0.549	tINS	FR	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s1/F
6.757	0.000	tNET	RR	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
10.856	-0.035	tSu		1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.214, 48.023%; route: 2.164, 46.945%; tC2Q: 0.232, 5.032%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.280
Data Arrival Time	6.576
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
6.205	0.436	tNET	FF	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n469_s1/I2
6.576	0.371	tINS	FF	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n469_s1/F
6.576	0.000	tNET	FF	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
10.856	-0.035	tSu		1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.036, 45.970%; route: 2.161, 48.792%; tC2Q: 0.232, 5.238%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.496
Data Arrival Time	6.360
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/I0
5.768	0.555	tINS	FF	10	R20C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s4/F
5.790	0.022	tNET	FF	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n470_s1/I2
6.360	0.570	tINS	FR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n470_s1/F
6.360	0.000	tNET	RR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
10.856	-0.035	tSu		1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.235, 53.044%; route: 1.746, 41.450%; tC2Q: 0.232, 5.506%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.593
Data Arrival Time	6.262
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q
3.308	0.929	tNET	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I3
3.863	0.555	tINS	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F
4.276	0.413	tNET	FF	1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2
4.831	0.555	tINS	FF	3	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.569	0.738	tNET	FF	1	R17C33[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
6.118	0.549	tINS	FR	1	R17C33[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
6.262	0.144	tNET	RR	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.659, 40.310%; route: 2.225, 54.053%; tC2Q: 0.232, 5.637%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.810
Data Arrival Time	6.046
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q
3.308	0.929	tNET	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I3
3.863	0.555	tINS	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F
4.276	0.413	tNET	FF	1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2
4.831	0.555	tINS	FF	3	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.575	0.744	tNET	FF	1	R17C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
5.902	0.327	tINS	FR	1	R17C33[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
6.046	0.144	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
10.856	-0.035	tSu		1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.437, 36.852%; route: 2.230, 57.198%; tC2Q: 0.232, 5.950%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.910
Data Arrival Time	5.946
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C39[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_11_s0/Q
3.308	0.929	tNET	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/I3
3.863	0.555	tINS	FF	1	R20C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s8/F
4.276	0.413	tNET	FF	1	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I2
4.831	0.555	tINS	FF	3	R20C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
5.575	0.744	tNET	FF	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n364_s3/I1
5.946	0.371	tINS	FF	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n364_s3/F
5.946	0.000	tNET	FF	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
10.856	-0.035	tSu		1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.481, 38.982%; route: 2.086, 54.911%; tC2Q: 0.232, 6.107%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	5.073
Data Arrival Time	5.783
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C37[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_8_s0/Q
3.285	0.907	tNET	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/I1
3.840	0.555	tINS	FF	1	R23C34[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s9/F
4.253	0.413	tNET	FF	1	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/I0
4.808	0.555	tINS	FF	2	R22C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n464_s7/F
5.213	0.405	tNET	FF	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n473_s2/I1
5.783	0.570	tINS	FR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n473_s2/F
5.783	0.000	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
10.856	-0.035	tSu		1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.680, 46.198%; route: 1.725, 47.423%; tC2Q: 0.232, 6.380%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	5.129
Data Arrival Time	5.727
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	342	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R27C32[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
2.379	0.232	tC2Q	RF	2	R27C32[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
2.944	0.565	tNET	FF	2	R27C35[0][B]	gw_gao_inst_0/u_la0_top/n2647_s0/I1
3.514	0.570	tINS	FR	1	R27C35[0][B]	gw_gao_inst_0/u_la0_top/n2647_s0/COUT
3.514	0.000	tNET	RR	2	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n2648_s0/CIN
3.549	0.035	tINS	RF	1	R27C35[1][A]	gw_gao_inst_0/u_la0_top/n2648_s0/COUT
3.549	0.000	tNET	FF	2	R27C35[1][B]	gw_gao_inst_0/u_la0_top/n2649_s0/CIN
3.584	0.035	tINS	FF	1	R27C35[1][B]	gw_gao_inst_0/u_la0_top/n2649_s0/COUT
3.584	0.000	tNET	FF	2	R27C35[2][A]	gw_gao_inst_0/u_la0_top/n2650_s0/CIN
3.620	0.035	tINS	FF	6	R27C35[2][A]	gw_gao_inst_0/u_la0_top/n2650_s0/COUT
4.291	0.672	tNET	FF	1	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2692_s1/I0
4.840	0.549	tINS	FR	1	R27C36[3][A]	gw_gao_inst_0/u_la0_top/n2692_s1/F
5.013	0.172	tNET	RR	1	R27C37[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.583	0.570	tINS	RR	1	R27C37[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
5.727	0.144	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.795, 50.122%; route: 1.554, 43.398%; tC2Q: 0.232, 6.480%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	5.487
Data Arrival Time	5.404
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
4.793	0.035	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/COUT
4.793	0.000	tNET	FF	2	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/CIN
4.828	0.035	tINS	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/COUT
4.828	0.000	tNET	FF	2	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/CIN
4.864	0.035	tINS	FF	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/COUT
4.864	0.000	tNET	FF	2	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/CIN
4.899	0.035	tINS	FF	1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/COUT
4.899	0.000	tNET	FF	2	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/CIN
4.934	0.035	tINS	FF	1	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/COUT
4.934	0.000	tNET	FF	2	R25C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN
5.404	0.470	tINS	FF	1	R25C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/SUM
5.404	0.000	tNET	FF	1	R25C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_38_s0/CLK
10.891	-0.035	tSu		1	R25C31[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_38_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.301, 29.043%; route: 0.918, 20.491%; tC2Q: 2.260, 50.466%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	5.522
Data Arrival Time	5.369
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
4.793	0.035	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/COUT
4.793	0.000	tNET	FF	2	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/CIN
4.828	0.035	tINS	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/COUT
4.828	0.000	tNET	FF	2	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/CIN
4.864	0.035	tINS	FF	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/COUT
4.864	0.000	tNET	FF	2	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/CIN
4.899	0.035	tINS	FF	1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/COUT
4.899	0.000	tNET	FF	2	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/CIN
5.369	0.470	tINS	FF	1	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n77_s/SUM
5.369	0.000	tNET	FF	1	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/CLK
10.891	-0.035	tSu		1	R25C31[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.265, 28.480%; route: 0.918, 20.653%; tC2Q: 2.260, 50.866%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	5.557
Data Arrival Time	5.334
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
4.793	0.035	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/COUT
4.793	0.000	tNET	FF	2	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/CIN
4.828	0.035	tINS	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/COUT
4.828	0.000	tNET	FF	2	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/CIN
4.864	0.035	tINS	FF	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/COUT
4.864	0.000	tNET	FF	2	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/CIN
5.334	0.470	tINS	FF	1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n78_s/SUM
5.334	0.000	tNET	FF	1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/CLK
10.891	-0.035	tSu		1	R25C31[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.230, 27.909%; route: 0.918, 20.818%; tC2Q: 2.260, 51.272%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	5.592
Data Arrival Time	5.298
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
4.793	0.035	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/COUT
4.793	0.000	tNET	FF	2	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/CIN
4.828	0.035	tINS	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/COUT
4.828	0.000	tNET	FF	2	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/CIN
5.298	0.470	tINS	FF	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n79_s/SUM
5.298	0.000	tNET	FF	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/CLK
10.891	-0.035	tSu		1	R25C31[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.195, 27.329%; route: 0.918, 20.986%; tC2Q: 2.260, 51.685%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	5.628
Data Arrival Time	5.263
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
4.793	0.035	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/COUT
4.793	0.000	tNET	FF	2	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/CIN
5.263	0.470	tINS	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n80_s/SUM
5.263	0.000	tNET	FF	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0/CLK
10.891	-0.035	tSu		1	R25C30[2][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_5_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.160, 26.739%; route: 0.918, 21.156%; tC2Q: 2.260, 52.104%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	5.663
Data Arrival Time	5.228
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
4.758	0.035	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/COUT
4.758	0.000	tNET	FF	2	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/CIN
5.228	0.470	tINS	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n81_s/SUM
5.228	0.000	tNET	FF	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_4_s0/CLK
10.891	-0.035	tSu		1	R25C30[2][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_4_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.125, 26.140%; route: 0.918, 21.329%; tC2Q: 2.260, 52.531%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	5.698
Data Arrival Time	5.193
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
4.723	0.035	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/COUT
4.723	0.000	tNET	FF	2	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/CIN
5.193	0.470	tINS	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n82_s/SUM
5.193	0.000	tNET	FF	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_3_s0/CLK
10.891	-0.035	tSu		1	R25C30[1][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_3_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.089, 25.531%; route: 0.918, 21.505%; tC2Q: 2.260, 52.964%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	5.733
Data Arrival Time	5.158
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[10]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	3	BSRAM_R28[10]	mem_data_mem_data_0_0_s/DO[0]
4.103	0.918	tNET	FF	2	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/I0
4.652	0.549	tINS	FR	1	R25C30[0][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n85_s/COUT
4.652	0.000	tNET	RR	2	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/CIN
4.688	0.035	tINS	RF	1	R25C30[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n84_s/COUT
4.688	0.000	tNET	FF	2	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/CIN
5.158	0.470	tINS	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n83_s/SUM
5.158	0.000	tNET	FF	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_2_s0/CLK
10.891	-0.035	tSu		1	R25C30[1][A]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_2_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.054, 24.911%; route: 0.918, 21.684%; tC2Q: 2.260, 53.405%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.074
Data Arrival Time	1.183
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R11C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/CLK
1.061	0.201	tC2Q	RF	1	R11C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_51_s0/Q
1.183	0.122	tNET	FF	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[15]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.080
Data Arrival Time	1.189
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/triger_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.061	0.201	tC2Q	RF	7	R27C36[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/Q
1.189	0.128	tNET	FF	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 38.990%; tC2Q: 0.201, 61.010%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/CLK
1.062	0.202	tC2Q	RR	1	R18C38[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_50_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[14]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/CLK
1.062	0.202	tC2Q	RR	1	R17C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_49_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[10]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_0_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_0_s0/CLK
0.871	0.011	tHld		1	R18C30[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R18C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_2_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_2_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_2_s0/CLK
0.871	0.011	tHld		1	R18C30[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_3_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_3_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_3_s0/CLK
0.871	0.011	tHld		1	R18C30[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_4_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_4_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_4_s0/CLK
0.871	0.011	tHld		1	R18C30[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R18C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_6_s0/CLK
0.871	0.011	tHld		1	R18C31[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R18C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_8_s0/CLK
0.871	0.011	tHld		1	R18C31[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_9_s0/CLK
0.871	0.011	tHld		1	R18C31[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.323
Data Arrival Time	1.193
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C29[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/out_valid_s0/Q
1.193	0.132	tNET	RR	1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_10_s0/CLK
0.871	0.011	tHld		1	R18C31[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[5].integrator_inst/add_out_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.461%; tC2Q: 0.202, 60.539%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_5_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R17C27[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_6_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_6_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_6_s0/CLK
0.871	0.011	tHld		1	R17C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_7_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R17C27[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_8_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_8_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_8_s0/CLK
0.871	0.011	tHld		1	R17C27[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_9_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_9_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_9_s0/CLK
0.871	0.011	tHld		1	R17C27[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.325
Data Arrival Time	1.196
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_10_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	40	R18C27[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.196	0.134	tNET	RR	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_10_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_10_s0/CLK
0.871	0.011	tHld		1	R17C27[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[4].integrator_inst/add_out_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.134, 39.901%; tC2Q: 0.202, 60.099%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.916
Data Arrival Time	7.975
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.975	1.794	tNET	FF	1	R32C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R32C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
10.891	-0.035	tSu		1	R32C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.794, 88.548%; tC2Q: 0.232, 11.452%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.159
Data Arrival Time	7.732
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.732	1.551	tNET	FF	1	R33C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R33C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.891	-0.035	tSu		1	R33C32[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.551, 86.989%; tC2Q: 0.232, 13.011%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.159
Data Arrival Time	7.732
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.732	1.551	tNET	FF	1	R33C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R33C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.891	-0.035	tSu		1	R33C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.551, 86.989%; tC2Q: 0.232, 13.011%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.491
Data Arrival Time	7.399
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.399	1.219	tNET	FF	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tSu		1	R17C33[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.219, 84.006%; tC2Q: 0.232, 15.994%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.491
Data Arrival Time	7.399
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.399	1.219	tNET	FF	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tSu		1	R17C33[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.219, 84.006%; tC2Q: 0.232, 15.994%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.491
Data Arrival Time	7.399
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.399	1.219	tNET	FF	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tSu		1	R17C33[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.219, 84.006%; tC2Q: 0.232, 15.994%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.527
Data Arrival Time	7.363
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.363	1.183	tNET	FF	1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tSu		1	R25C33[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.183, 83.598%; tC2Q: 0.232, 16.402%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R17C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tSu		1	R17C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tSu		1	R17C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tSu		1	R17C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tSu		1	R17C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tSu		1	R17C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tSu		1	R17C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	3.734
Data Arrival Time	7.157
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.157	0.976	tNET	FF	1	R17C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
10.891	-0.035	tSu		1	R17C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.976, 80.792%; tC2Q: 0.232, 19.208%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	3.742
Data Arrival Time	7.149
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.149	0.968	tNET	FF	1	R17C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
10.891	-0.035	tSu		1	R17C36[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.968, 80.667%; tC2Q: 0.232, 19.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	3.742
Data Arrival Time	7.149
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.149	0.968	tNET	FF	1	R17C36[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R17C36[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
10.891	-0.035	tSu		1	R17C36[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.968, 80.667%; tC2Q: 0.232, 19.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
10.891	-0.035	tSu		1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tSu		1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
10.891	-0.035	tSu		1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
10.891	-0.035	tSu		1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
10.891	-0.035	tSu		1	R20C36[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	3.837
Data Arrival Time	7.053
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.053	0.873	tNET	FF	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
10.891	-0.035	tSu		1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.873, 78.996%; tC2Q: 0.232, 21.004%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	3.989
Data Arrival Time	6.901
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.901	0.721	tNET	FF	1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.646%; tC2Q: 0.232, 24.354%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	3.989
Data Arrival Time	6.901
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.901	0.721	tNET	FF	1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	964	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.891	-0.035	tSu		1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.646%; tC2Q: 0.232, 24.354%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.340
Data Arrival Time	6.211
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.211	0.137	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3/CLK
0.871	0.011	tHld		1	R27C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 40.422%; tC2Q: 0.202, 59.578%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.340
Data Arrival Time	6.211
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.211	0.137	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R27C37[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 40.422%; tC2Q: 0.202, 59.578%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.340
Data Arrival Time	6.211
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.211	0.137	tNET	RR	1	R27C37[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C37[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R27C37[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.137, 40.422%; tC2Q: 0.202, 59.578%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.457
Data Arrival Time	6.328
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.328	0.254	tNET	RR	1	R27C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R27C38[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.254, 55.710%; tC2Q: 0.202, 44.290%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871	0.011	tHld		1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R27C39[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C39[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C39[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R27C39[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C39[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C39[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R27C39[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
0.871	0.011	tHld		1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871	0.011	tHld		1	R27C36[1][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C39[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C39[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R27C39[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
0.871	0.011	tHld		1	R27C36[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.467
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
0.871	0.011	tHld		1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.654%; tC2Q: 0.202, 43.346%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.484
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
0.871	0.011	tHld		1	R27C31[1][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.123%; tC2Q: 0.202, 41.877%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.484
Data Arrival Time	6.354
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.354	0.280	tNET	RR	1	R27C31[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C31[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
0.871	0.011	tHld		1	R27C31[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.280, 58.123%; tC2Q: 0.202, 41.877%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.579
Data Arrival Time	6.450
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.450	0.376	tNET	RR	1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871	0.011	tHld		1	R27C34[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.376, 65.057%; tC2Q: 0.202, 34.943%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.579
Data Arrival Time	6.450
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.450	0.376	tNET	RR	1	R27C34[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C34[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871	0.011	tHld		1	R27C34[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.376, 65.057%; tC2Q: 0.202, 34.943%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.616
Data Arrival Time	6.487
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.487	0.413	tNET	RR	1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
0.871	0.011	tHld		1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.413, 67.144%; tC2Q: 0.202, 32.856%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.616
Data Arrival Time	6.487
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.487	0.413	tNET	RR	1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
0.871	0.011	tHld		1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.413, 67.144%; tC2Q: 0.202, 32.856%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.616
Data Arrival Time	6.487
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.487	0.413	tNET	RR	1	R20C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871	0.011	tHld		1	R20C37[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.413, 67.144%; tC2Q: 0.202, 32.856%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.626
Data Arrival Time	6.497
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.497	0.423	tNET	RR	1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
0.871	0.011	tHld		1	R20C38[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.691%; tC2Q: 0.202, 32.309%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.626
Data Arrival Time	6.497
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.497	0.423	tNET	RR	1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871	0.011	tHld		1	R20C38[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.691%; tC2Q: 0.202, 32.309%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.626
Data Arrival Time	6.497
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.497	0.423	tNET	RR	1	R20C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
0.871	0.011	tHld		1	R20C38[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.423, 67.691%; tC2Q: 0.202, 32.309%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.754
Data Arrival Time	6.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.625	0.551	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
0.871	0.011	tHld		1	R20C35[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.179%; tC2Q: 0.202, 26.821%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.754
Data Arrival Time	6.625
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	964	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R27C37[1][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.625	0.551	tNET	RR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	964	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871	0.011	tHld		1	R20C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.551, 73.179%; tC2Q: 0.202, 26.821%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_10_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_10_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_10_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_8_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_8_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_8_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_4_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_10_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	i_data_10_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	i_data_10_s1/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_6_s0/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[1].comb_inst/buff_delay[0]_3_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[1]_4_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[4].comb_inst/buff_delay[1]_1_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_2_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[7].comb_inst/buff_delay[3]_3_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
964	clk_d	2.916	0.261
342	control0[0]	2.308	0.912
86	n20_3	46.321	1.599
82	comb_vaild_5[6]	8.674	1.059
77	comb_vaild_4[5]	7.883	1.850
72	comb_vaild_3[4]	8.061	1.672
67	comb_vaild_2[3]	8.934	0.951
66	data_out_shift_reg_63_7	45.914	0.979
63	n828_5	44.912	1.169
62	comb_vaild_1[2]	8.684	1.049

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R26C35	88.89%
R11C35	87.50%
R26C37	87.50%
R18C19	86.11%
R18C24	86.11%
R18C22	86.11%
R18C23	86.11%
R26C33	86.11%
R21C33	86.11%
R21C34	86.11%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]