Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\src\cic_filter.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\src\cic_filter\cic_filter.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Interpolator\1_9_4_4_4\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Fri Jul 15 10:29:08 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | cic_filter |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.531s, Elapsed time = 0h 0m 0.554s, Peak memory usage = 131.320MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 131.320MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.033s, Peak memory usage = 131.320MB Optimizing Phase 2: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.079s, Peak memory usage = 131.320MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 131.320MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 131.320MB Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 131.320MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 131.320MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 131.320MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 131.320MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 131.320MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 142.156MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.075s, Peak memory usage = 142.156MB Generate output files: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 142.156MB |
| Total Time and Memory Usage | CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 142.156MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 31 |
| I/O Buf | 31 |
| IBUF | 5 |
| OBUF | 26 |
| Register | 670 |
| DFF | 27 |
| DFFE | 2 |
| DFFP | 1 |
| DFFPE | 35 |
| DFFC | 68 |
| DFFCE | 526 |
| DFFNP | 2 |
| DFFNC | 7 |
| DFFNCE | 2 |
| LUT | 444 |
| LUT2 | 85 |
| LUT3 | 138 |
| LUT4 | 221 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 159 |
| ALU | 159 |
| SSRAM | 13 |
| RAM16S4 | 13 |
| INV | 6 |
| INV | 6 |
| BSRAM | 4 |
| SDPX9B | 3 |
| pROMX9 | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 695(458 LUTs, 159 ALUs, 13 SSRAMs) / 20736 | 3% |
| Register | 670 / 16173 | 4% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 670 / 16173 | 4% |
| BSRAM | 4 / 46 | 9% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 234.7(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.740 |
| Data Arrival Time | 5.088 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n394_s2/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n394_s2/F |
| 2.124 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n392_s2/I2 |
| 2.577 | 0.453 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n392_s2/F |
| 2.814 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n390_s3/I2 |
| 3.267 | 0.453 | tINS | FF | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n390_s3/F |
| 3.504 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s3/I1 |
| 4.059 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s3/F |
| 4.296 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s1/I1 |
| 4.851 | 0.555 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s1/F |
| 5.088 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.571, 60.852%; route: 1.422, 33.657%; tC2Q: 0.232, 5.491% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 6.391 |
| Data Arrival Time | 4.436 |
| Data Required Time | 10.828 |
| From | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15 |
| To | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/Q |
| 1.332 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 9 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/I0 |
| 2.641 | 0.517 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/F |
| 2.878 | 0.237 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/I1 |
| 3.447 | 0.570 | tINS | FR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/COUT |
| 3.447 | 0.000 | tNET | RR | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/CIN |
| 3.483 | 0.035 | tINS | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT |
| 3.483 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN |
| 3.518 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT |
| 3.518 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN |
| 3.553 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT |
| 3.553 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN |
| 3.588 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT |
| 3.588 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN |
| 3.624 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT |
| 3.624 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN |
| 3.659 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT |
| 3.659 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN |
| 3.694 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/COUT |
| 3.694 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/CIN |
| 3.729 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/COUT |
| 3.729 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n31_s/CIN |
| 4.199 | 0.470 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n31_s/SUM |
| 4.436 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_22_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.394, 66.980%; route: 0.948, 26.528%; tC2Q: 0.232, 6.492% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.427 |
| Data Arrival Time | 4.401 |
| Data Required Time | 10.828 |
| From | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15 |
| To | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/Q |
| 1.332 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 9 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/I0 |
| 2.641 | 0.517 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/F |
| 2.878 | 0.237 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/I1 |
| 3.447 | 0.570 | tINS | FR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/COUT |
| 3.447 | 0.000 | tNET | RR | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/CIN |
| 3.483 | 0.035 | tINS | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT |
| 3.483 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN |
| 3.518 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT |
| 3.518 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN |
| 3.553 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT |
| 3.553 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN |
| 3.588 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT |
| 3.588 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN |
| 3.624 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT |
| 3.624 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN |
| 3.659 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT |
| 3.659 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN |
| 3.694 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/COUT |
| 3.694 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/CIN |
| 4.164 | 0.470 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n45_s/SUM |
| 4.401 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_8_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.358, 66.651%; route: 0.948, 26.792%; tC2Q: 0.232, 6.557% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.462 |
| Data Arrival Time | 4.366 |
| Data Required Time | 10.828 |
| From | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15 |
| To | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/CLK |
| 1.095 | 0.232 | tC2Q | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s15/Q |
| 1.332 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/I1 |
| 1.887 | 0.555 | tINS | FF | 9 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_8_s4/F |
| 2.124 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/I0 |
| 2.641 | 0.517 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[3]_0_s3/F |
| 2.878 | 0.237 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/I1 |
| 3.447 | 0.570 | tINS | FR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n53_s/COUT |
| 3.447 | 0.000 | tNET | RR | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/CIN |
| 3.483 | 0.035 | tINS | RF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n52_s/COUT |
| 3.483 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/CIN |
| 3.518 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n51_s/COUT |
| 3.518 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/CIN |
| 3.553 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n50_s/COUT |
| 3.553 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/CIN |
| 3.588 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n49_s/COUT |
| 3.588 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/CIN |
| 3.624 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n48_s/COUT |
| 3.624 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/CIN |
| 3.659 | 0.035 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n47_s/COUT |
| 3.659 | 0.000 | tNET | FF | 2 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/CIN |
| 4.129 | 0.470 | tINS | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/n46_s/SUM |
| 4.366 | 0.237 | tNET | FF | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/comb_out_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.323, 66.316%; route: 0.948, 27.061%; tC2Q: 0.232, 6.623% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.467 |
| Data Arrival Time | 4.360 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s9/I0 |
| 1.849 | 0.517 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s9/F |
| 2.086 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/I1 |
| 2.641 | 0.555 | tINS | FF | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s6/F |
| 2.878 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/I0 |
| 3.395 | 0.517 | tINS | FF | 10 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n389_s4/F |
| 3.632 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0 |
| 4.181 | 0.549 | tINS | FR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F |
| 4.360 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 420 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.138, 61.121%; route: 1.128, 32.247%; tC2Q: 0.232, 6.632% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |