Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\1_9_4_4_4\project\impl\gwsynthesis\fpga_project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\1_9_4_4_4\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_CIC_Filter\Gowin_CIC_Filter_RefDesign\Decimator\1_9_4_4_4\project\src\fpga_project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Fri Jul 15 08:16:48 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	2002
Numbers of Endpoints Analyzed	2346
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
clk	Base	10.000	100.000	0.000	5.000			clk
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	184.609(MHz)	5	TOP
2	tck_pad_i	20.000(MHz)	92.647(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.009	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	1.560
2	2.813	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D	tck_pad_i:[F]	clk:[R]	5.000	1.361	0.756
3	4.560	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	4.149
4	4.583	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_24_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.382
5	4.618	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_23_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.347
6	4.654	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_22_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.311
7	4.689	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_21_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.276
8	4.724	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_20_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.241
9	4.737	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.972
10	4.742	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.967
11	4.758	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.951
12	4.758	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.951
13	4.759	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_19_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.206
14	4.763	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.946
15	4.794	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.171
16	4.830	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_17_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.135
17	4.832	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.878
18	4.839	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.870
19	4.841	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.868
20	4.865	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_16_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.100
21	4.900	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_15_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.065
22	4.930	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.779
23	4.930	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	clk:[R]	10.000	1.221	3.779
24	4.935	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_14_s0/D	clk:[R]	clk:[R]	10.000	0.000	5.030
25	4.970	mem_data_mem_data_0_0_s/DO[3]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	10.000	0.000	4.995

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	clk:[R]	clk:[R]	0.000	0.000	0.202
4	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10]	clk:[R]	clk:[R]	0.000	0.000	0.474
5	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7]	clk:[R]	clk:[R]	0.000	0.000	0.474
6	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]	clk:[R]	clk:[R]	0.000	0.000	0.474
7	0.319	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0/CE	clk:[R]	clk:[R]	0.000	0.000	0.330
8	0.334	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.346
9	0.337	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s31/AD[1]	clk:[R]	clk:[R]	0.000	0.000	0.349
10	0.339	gw_gao_inst_0/u_la0_top/triger_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]	clk:[R]	clk:[R]	0.000	0.000	0.588
11	0.351	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]	clk:[R]	clk:[R]	0.000	0.000	0.600
12	0.351	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	clk:[R]	clk:[R]	0.000	0.000	0.600
13	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_45_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9]	clk:[R]	clk:[R]	0.000	0.000	0.612
14	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]	clk:[R]	clk:[R]	0.000	0.000	0.612
15	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]	clk:[R]	clk:[R]	0.000	0.000	0.612
16	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]	clk:[R]	clk:[R]	0.000	0.000	0.612
17	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]	clk:[R]	clk:[R]	0.000	0.000	0.612
18	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
19	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
20	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
21	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
22	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
23	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
24	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436
25	0.425	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/Q	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	3.732	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.210
2	3.732	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.210
3	3.732	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.210
4	3.759	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	0.023	1.183
5	3.759	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.183
6	3.759	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.183
7	3.759	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.183
8	3.822	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.119
9	3.822	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.119
10	3.865	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.077
11	3.865	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.077
12	3.865	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	1.077
13	3.987	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.955
14	3.987	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.955
15	3.987	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.955
16	3.987	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.955
17	3.988	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953
18	3.988	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953
19	3.988	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953
20	3.988	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.953
21	3.995	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.947
22	3.995	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.947
23	3.995	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.947
24	3.995	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.947
25	3.995	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.023	0.947

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.468	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
2	5.468	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.466
3	5.477	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
4	5.477	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
5	5.477	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.476
6	5.590	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.588
7	5.590	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.588
8	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
9	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
10	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
11	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.598
12	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.599
13	5.600	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.599
14	5.603	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.602
15	5.603	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.602
16	5.605	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.604
17	5.605	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.604
18	5.605	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.604
19	5.605	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.604
20	5.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.608
21	5.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.608
22	5.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.608
23	5.609	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.608
24	5.624	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.623
25	5.624	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.012	0.623

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	3.911	4.911	1.000	Low Pulse Width	clk	counter_9_s0
2	3.911	4.911	1.000	Low Pulse Width	clk	counter_7_s0
3	3.911	4.911	1.000	Low Pulse Width	clk	counter_3_s0
4	3.911	4.911	1.000	Low Pulse Width	clk	i_data_7_s1
5	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0
6	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0
7	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0
8	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_19_s0
9	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_20_s0
10	3.911	4.911	1.000	Low Pulse Width	clk	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_24_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.009
Data Arrival Time	28.847
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_start_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C28[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/CLK
27.519	0.232	tC2Q	FF	2	R27C28[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_s3/Q
28.847	1.328	tNET	FF	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
30.856	-0.035	tSu		1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.328, 85.129%; tC2Q: 0.232, 14.871%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	2.813
Data Arrival Time	28.043
Data Required Time	30.856
From	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	tck_pad_i:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
25.000	25.000					active clock edge time
25.000	0.000					tck_pad_i
25.000	0.000	tCL	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
25.688	0.688	tINS	FF	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
25.688	0.000	tNET	FF	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
26.375	0.688	tINS	FF	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
27.287	0.912	tNET	FF	1	R27C28[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/CLK
27.519	0.232	tC2Q	FF	1	R27C28[0][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_s3/Q
28.043	0.524	tNET	FF	1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
30.000	30.000					active clock edge time
30.000	0.000					clk
30.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
30.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
30.926	0.243	tNET	RR	1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
30.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
30.856	-0.035	tSu		1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-1.361
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.375, 60.128%; route: 0.912, 39.872%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.524, 69.317%; tC2Q: 0.232, 30.683%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	4.560
Data Arrival Time	6.295
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R26C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/CLK
2.379	0.232	tC2Q	RF	2	R26C36[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_2_s0/Q
2.944	0.565	tNET	FF	2	R27C37[1][B]	gw_gao_inst_0/u_la0_top/n2190_s0/I1
3.514	0.570	tINS	FR	1	R27C37[1][B]	gw_gao_inst_0/u_la0_top/n2190_s0/COUT
3.514	0.000	tNET	RR	2	R27C37[2][A]	gw_gao_inst_0/u_la0_top/n2191_s0/CIN
3.549	0.035	tINS	RF	6	R27C37[2][A]	gw_gao_inst_0/u_la0_top/n2191_s0/COUT
4.523	0.974	tNET	FF	1	R25C35[3][A]	gw_gao_inst_0/u_la0_top/n2233_s1/I0
5.072	0.549	tINS	FR	1	R25C35[3][A]	gw_gao_inst_0/u_la0_top/n2233_s1/F
5.245	0.172	tNET	RR	1	R24C35[3][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
5.572	0.327	tINS	RR	1	R24C35[3][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
6.295	0.724	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
10.856	-0.035	tSu		1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.481, 35.702%; route: 2.436, 58.705%; tC2Q: 0.232, 5.592%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.583
Data Arrival Time	6.308
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
5.697	0.035	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/COUT
5.697	0.000	tNET	FF	2	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/CIN
5.732	0.035	tINS	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/COUT
5.732	0.000	tNET	FF	2	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/CIN
5.767	0.035	tINS	FF	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/COUT
5.767	0.000	tNET	FF	2	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/CIN
5.802	0.035	tINS	FF	1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/COUT
5.802	0.000	tNET	FF	2	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n10_s/CIN
5.838	0.035	tINS	FF	1	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n10_s/COUT
5.838	0.000	tNET	FF	2	R35C24[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n9_s/CIN
6.308	0.470	tINS	FF	1	R35C24[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n9_s/SUM
6.308	0.000	tNET	FF	1	R35C24[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C24[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_24_s0/CLK
10.891	-0.035	tSu		1	R35C24[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_24_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.744, 32.405%; route: 1.378, 25.602%; tC2Q: 2.260, 41.993%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.618
Data Arrival Time	6.272
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
5.697	0.035	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/COUT
5.697	0.000	tNET	FF	2	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/CIN
5.732	0.035	tINS	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/COUT
5.732	0.000	tNET	FF	2	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/CIN
5.767	0.035	tINS	FF	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/COUT
5.767	0.000	tNET	FF	2	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/CIN
5.802	0.035	tINS	FF	1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/COUT
5.802	0.000	tNET	FF	2	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n10_s/CIN
6.272	0.470	tINS	FF	1	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n10_s/SUM
6.272	0.000	tNET	FF	1	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_23_s0/CLK
10.891	-0.035	tSu		1	R35C24[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_23_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.709, 31.960%; route: 1.378, 25.770%; tC2Q: 2.260, 42.269%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.654
Data Arrival Time	6.237
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
5.697	0.035	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/COUT
5.697	0.000	tNET	FF	2	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/CIN
5.732	0.035	tINS	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/COUT
5.732	0.000	tNET	FF	2	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/CIN
5.767	0.035	tINS	FF	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/COUT
5.767	0.000	tNET	FF	2	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/CIN
6.237	0.470	tINS	FF	1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n11_s/SUM
6.237	0.000	tNET	FF	1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_22_s0/CLK
10.891	-0.035	tSu		1	R35C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_22_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.674, 31.509%; route: 1.378, 25.941%; tC2Q: 2.260, 42.550%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.689
Data Arrival Time	6.202
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
5.697	0.035	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/COUT
5.697	0.000	tNET	FF	2	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/CIN
5.732	0.035	tINS	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/COUT
5.732	0.000	tNET	FF	2	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/CIN
6.202	0.470	tINS	FF	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n12_s/SUM
6.202	0.000	tNET	FF	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_21_s0/CLK
10.891	-0.035	tSu		1	R35C23[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_21_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.638, 31.052%; route: 1.378, 26.114%; tC2Q: 2.260, 42.833%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.724
Data Arrival Time	6.167
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
5.697	0.035	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/COUT
5.697	0.000	tNET	FF	2	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/CIN
6.167	0.470	tINS	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n13_s/SUM
6.167	0.000	tNET	FF	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_20_s0/CLK
10.891	-0.035	tSu		1	R35C23[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_20_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.603, 30.589%; route: 1.378, 26.290%; tC2Q: 2.260, 43.121%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.737
Data Arrival Time	6.119
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.549	0.432	tNET	FF	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n383_s1/I3
6.119	0.570	tINS	FR	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n383_s1/F
6.119	0.000	tNET	RR	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
10.856	-0.035	tSu		1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.002, 50.400%; route: 1.738, 43.759%; tC2Q: 0.232, 5.841%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.742
Data Arrival Time	6.114
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.544	0.426	tNET	FF	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s3/I2
6.114	0.570	tINS	FR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n388_s3/F
6.114	0.000	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3
10.856	-0.035	tSu		1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.002, 50.467%; route: 1.733, 43.685%; tC2Q: 0.232, 5.848%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	4.758
Data Arrival Time	6.098
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.549	0.432	tNET	FF	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n381_s1/I3
6.098	0.549	tINS	FR	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n381_s1/F
6.098	0.000	tNET	RR	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
10.856	-0.035	tSu		1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.981, 50.137%; route: 1.738, 43.992%; tC2Q: 0.232, 5.872%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	4.758
Data Arrival Time	6.098
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.549	0.432	tNET	FF	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s1/I3
6.098	0.549	tINS	FR	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s1/F
6.098	0.000	tNET	RR	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
10.856	-0.035	tSu		1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.981, 50.137%; route: 1.738, 43.992%; tC2Q: 0.232, 5.872%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	4.759
Data Arrival Time	6.132
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
5.662	0.035	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/COUT
5.662	0.000	tNET	FF	2	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/CIN
6.132	0.470	tINS	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n14_s/SUM
6.132	0.000	tNET	FF	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_19_s0/CLK
10.891	-0.035	tSu		1	R35C23[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_19_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.568, 30.120%; route: 1.378, 26.467%; tC2Q: 2.260, 43.413%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	4.763
Data Arrival Time	6.093
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.544	0.426	tNET	FF	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n386_s1/I3
6.093	0.549	tINS	FR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n386_s1/F
6.093	0.000	tNET	RR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
10.856	-0.035	tSu		1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.981, 50.203%; route: 1.733, 43.918%; tC2Q: 0.232, 5.879%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	4.794
Data Arrival Time	6.096
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
5.626	0.035	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/COUT
5.626	0.000	tNET	FF	2	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/CIN
6.096	0.470	tINS	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n15_s/SUM
6.096	0.000	tNET	FF	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0/CLK
10.891	-0.035	tSu		1	R35C23[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.533, 29.644%; route: 1.378, 26.647%; tC2Q: 2.260, 43.708%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	4.830
Data Arrival Time	6.061
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
5.591	0.035	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/COUT
5.591	0.000	tNET	FF	2	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/CIN
6.061	0.470	tINS	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n16_s/SUM
6.061	0.000	tNET	FF	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_17_s0/CLK
10.891	-0.035	tSu		1	R35C23[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_17_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.498, 29.162%; route: 1.378, 26.830%; tC2Q: 2.260, 44.008%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	4.832
Data Arrival Time	6.024
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.310	0.193	tNET	FF	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
5.880	0.570	tINS	FR	1	R21C36[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
6.024	0.144	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
10.856	-0.035	tSu		1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.002, 51.631%; route: 1.644, 42.386%; tC2Q: 0.232, 5.983%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	4.839
Data Arrival Time	6.017
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.555	0.438	tNET	FF	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n387_s1/I2
6.017	0.462	tINS	FR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n387_s1/F
6.017	0.000	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
10.856	-0.035	tSu		1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.894, 48.935%; route: 1.744, 45.071%; tC2Q: 0.232, 5.994%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	4.841
Data Arrival Time	6.015
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.553	0.435	tNET	FF	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n380_s1/I2
6.015	0.462	tINS	FR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n380_s1/F
6.015	0.000	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
10.856	-0.035	tSu		1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.894, 48.965%; route: 1.742, 45.037%; tC2Q: 0.232, 5.998%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	4.865
Data Arrival Time	6.026
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.556	0.035	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/COUT
5.556	0.000	tNET	FF	2	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/CIN
6.026	0.470	tINS	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n17_s/SUM
6.026	0.000	tNET	FF	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_16_s0/CLK
10.891	-0.035	tSu		1	R35C22[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_16_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.462, 28.673%; route: 1.378, 27.015%; tC2Q: 2.260, 44.312%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	4.900
Data Arrival Time	5.991
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_15_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.521	0.035	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/COUT
5.521	0.000	tNET	FF	2	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/CIN
5.991	0.470	tINS	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n18_s/SUM
5.991	0.000	tNET	FF	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_15_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_15_s0/CLK
10.891	-0.035	tSu		1	R35C22[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_15_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.427, 28.177%; route: 1.378, 27.203%; tC2Q: 2.260, 44.620%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	4.930
Data Arrival Time	5.926
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.555	0.438	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n385_s1/I2
5.926	0.371	tINS	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n385_s1/F
5.926	0.000	tNET	FF	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
10.856	-0.035	tSu		1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.803, 47.705%; route: 1.744, 46.156%; tC2Q: 0.232, 6.138%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	4.930
Data Arrival Time	5.926
Data Required Time	10.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	296	-	gw_gao_inst_0/u_gw_jtag/tck_o
2.147	0.782	tNET	RR	1	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/CLK
2.379	0.232	tC2Q	RF	2	R25C35[1][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_3_s0/Q
3.266	0.887	tNET	FF	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/I3
3.728	0.462	tINS	FR	1	R24C35[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s12/F
3.900	0.172	tNET	RR	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/I2
4.417	0.517	tINS	RF	1	R24C36[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s8/F
4.664	0.247	tNET	FF	1	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/I2
5.117	0.453	tINS	FF	11	R22C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n379_s4/F
5.555	0.438	tNET	FF	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n382_s1/I2
5.926	0.371	tINS	FF	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n382_s1/F
5.926	0.000	tNET	FF	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
10.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
10.856	-0.035	tSu		1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.803, 47.705%; route: 1.744, 46.156%; tC2Q: 0.232, 6.138%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	4.935
Data Arrival Time	5.956
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_14_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.486	0.035	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/COUT
5.486	0.000	tNET	FF	2	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/CIN
5.956	0.470	tINS	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n19_s/SUM
5.956	0.000	tNET	FF	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_14_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_14_s0/CLK
10.891	-0.035	tSu		1	R35C22[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_14_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.392, 27.675%; route: 1.378, 27.393%; tC2Q: 2.260, 44.932%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	4.970
Data Arrival Time	5.920
Data Required Time	10.891
From	mem_data_mem_data_0_0_s
To	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.683	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.926	0.243	tNET	RR	9	BSRAM_R28[9]	mem_data_mem_data_0_0_s/CLK
3.186	2.260	tC2Q	RF	2	BSRAM_R28[9]	mem_data_mem_data_0_0_s/DO[3]
4.564	1.378	tNET	FF	2	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/I0
5.134	0.570	tINS	FR	1	R35C20[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n30_s/COUT
5.134	0.000	tNET	RR	2	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/CIN
5.169	0.035	tINS	RF	1	R35C20[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n29_s/COUT
5.169	0.000	tNET	FF	2	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/CIN
5.204	0.035	tINS	FF	1	R35C21[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n28_s/COUT
5.204	0.000	tNET	FF	2	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/CIN
5.239	0.035	tINS	FF	1	R35C21[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n27_s/COUT
5.239	0.000	tNET	FF	2	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/CIN
5.274	0.035	tINS	FF	1	R35C21[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n26_s/COUT
5.274	0.000	tNET	FF	2	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/CIN
5.310	0.035	tINS	FF	1	R35C21[1][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n25_s/COUT
5.310	0.000	tNET	FF	2	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/CIN
5.345	0.035	tINS	FF	1	R35C21[2][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n24_s/COUT
5.345	0.000	tNET	FF	2	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/CIN
5.380	0.035	tINS	FF	1	R35C21[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n23_s/COUT
5.380	0.000	tNET	FF	2	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/CIN
5.415	0.035	tINS	FF	1	R35C22[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n22_s/COUT
5.415	0.000	tNET	FF	2	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/CIN
5.450	0.035	tINS	FF	1	R35C22[0][B]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n21_s/COUT
5.450	0.000	tNET	FF	2	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/CIN
5.920	0.470	tINS	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/n20_s/SUM
5.920	0.000	tNET	FF	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_13_s0/CLK
10.891	-0.035	tSu		1	R35C22[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%
Arrival Data Path Delay	cell: 1.357, 27.165%; route: 1.378, 27.586%; tC2Q: 2.260, 45.248%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[9]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	11	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_46_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C31[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C31[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_40_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.319
Data Arrival Time	1.190
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0
To	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/CLK
1.062	0.202	tC2Q	RR	3	R31C23[2][B]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/out_valid_s0/Q
1.190	0.128	tNET	RR	1	R31C23[0][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R31C23[0][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0/CLK
0.871	0.011	tHld		1	R31C23[0][B]	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.128, 38.865%; tC2Q: 0.202, 61.135%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.334
Data Arrival Time	1.206
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/CLK
1.062	0.202	tC2Q	RR	19	R22C23[0][B]	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s4/Q
1.206	0.144	tNET	RR	1	R24C23	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C23	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31/CLK
0.872	0.012	tHld		1	R24C23	CIC_Fliter_tb/CIC_Filter/comb[2].comb_inst/buff_delay[0]_0_s31

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.144, 41.675%; tC2Q: 0.202, 58.325%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.337
Data Arrival Time	1.209
Data Required Time	0.872
From	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4
To	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s31
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R30C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/CLK
1.062	0.202	tC2Q	RR	19	R30C22[0][B]	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s4/Q
1.209	0.147	tNET	RR	1	R32C22	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s31/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R32C22	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s31/CLK
0.872	0.012	tHld		1	R32C22	CIC_Fliter_tb/CIC_Filter/comb[0].comb_inst/buff_delay[0]_0_s31

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 42.176%; tC2Q: 0.202, 57.824%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.339
Data Arrival Time	1.448
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/triger_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C35[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.062	0.202	tC2Q	RR	7	R25C35[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/Q
1.448	0.386	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.386, 65.650%; tC2Q: 0.202, 34.350%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	0.351
Data Arrival Time	1.460
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q
1.460	0.398	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.351
Data Arrival Time	1.460
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_36_s0/Q
1.460	0.398	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.398, 66.358%; tC2Q: 0.202, 33.642%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_45_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_45_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_45_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C32[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_39_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C32[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C32[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_38_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_37_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/CLK
1.062	0.202	tC2Q	RR	1	R21C32[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_44_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R28[8]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/Q
1.064	0.002	tNET	RR	2	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n32_s/I1
1.296	0.232	tINS	RF	1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n32_s/SUM
1.296	0.000	tNET	FF	1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0/CLK
0.871	0.011	tHld		1	R34C28[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/Q
1.064	0.002	tNET	RR	2	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n28_s/I1
1.296	0.232	tINS	RF	1	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n28_s/SUM
1.296	0.000	tNET	FF	1	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0/CLK
0.871	0.011	tHld		1	R34C29[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_5_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/Q
1.064	0.002	tNET	RR	2	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n26_s/I1
1.296	0.232	tINS	RF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n26_s/SUM
1.296	0.000	tNET	FF	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0/CLK
0.871	0.011	tHld		1	R34C29[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/Q
1.064	0.002	tNET	RR	2	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n22_s/I1
1.296	0.232	tINS	RF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n22_s/SUM
1.296	0.000	tNET	FF	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0/CLK
0.871	0.011	tHld		1	R34C30[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/Q
1.064	0.002	tNET	RR	2	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n20_s/I1
1.296	0.232	tINS	RF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n20_s/SUM
1.296	0.000	tNET	FF	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0/CLK
0.871	0.011	tHld		1	R34C30[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/Q
1.064	0.002	tNET	RR	2	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n16_s/I1
1.296	0.232	tINS	RF	1	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n16_s/SUM
1.296	0.000	tNET	FF	1	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0/CLK
0.871	0.011	tHld		1	R34C31[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_17_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/Q
1.064	0.002	tNET	RR	2	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n14_s/I1
1.296	0.232	tINS	RF	1	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n14_s/SUM
1.296	0.000	tNET	FF	1	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0/CLK
0.871	0.011	tHld		1	R34C31[1][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_19_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	1.296
Data Required Time	0.871
From	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0
To	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/CLK
1.062	0.202	tC2Q	RR	2	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/Q
1.064	0.002	tNET	RR	2	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n10_s/I1
1.296	0.232	tINS	RF	1	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/n10_s/SUM
1.296	0.000	tNET	FF	1	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0/CLK
0.871	0.011	tHld		1	R34C32[0][A]	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	3.732
Data Arrival Time	7.159
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.159	0.978	tNET	FF	1	R31C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R31C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
10.891	-0.035	tSu		1	R31C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.978, 80.831%; tC2Q: 0.232, 19.169%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	3.732
Data Arrival Time	7.159
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.159	0.978	tNET	FF	1	R31C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R31C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
10.891	-0.035	tSu		1	R31C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.978, 80.831%; tC2Q: 0.232, 19.169%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	3.732
Data Arrival Time	7.159
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.159	0.978	tNET	FF	1	R31C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R31C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
10.891	-0.035	tSu		1	R31C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.978, 80.831%; tC2Q: 0.232, 19.169%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	3.759
Data Arrival Time	7.132
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.132	0.951	tNET	FF	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
10.891	-0.035	tSu		1	R21C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 80.385%; tC2Q: 0.232, 19.615%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	3.759
Data Arrival Time	7.132
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.132	0.951	tNET	FF	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
10.891	-0.035	tSu		1	R21C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 80.385%; tC2Q: 0.232, 19.615%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	3.759
Data Arrival Time	7.132
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.132	0.951	tNET	FF	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0/CLK
10.891	-0.035	tSu		1	R21C34[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 80.385%; tC2Q: 0.232, 19.615%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	3.759
Data Arrival Time	7.132
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.132	0.951	tNET	FF	1	R21C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0/CLK
10.891	-0.035	tSu		1	R21C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_zero_flag_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.951, 80.385%; tC2Q: 0.232, 19.615%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	3.822
Data Arrival Time	7.068
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.068	0.887	tNET	FF	1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
10.891	-0.035	tSu		1	R27C28[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.887, 79.276%; tC2Q: 0.232, 20.724%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	3.822
Data Arrival Time	7.068
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.068	0.887	tNET	FF	1	R27C28[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C28[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
10.891	-0.035	tSu		1	R27C28[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.887, 79.276%; tC2Q: 0.232, 20.724%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	3.865
Data Arrival Time	7.026
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.026	0.845	tNET	FF	1	R22C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
10.891	-0.035	tSu		1	R22C34[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 78.464%; tC2Q: 0.232, 21.536%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	3.865
Data Arrival Time	7.026
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.026	0.845	tNET	FF	1	R22C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
10.891	-0.035	tSu		1	R22C34[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 78.464%; tC2Q: 0.232, 21.536%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	3.865
Data Arrival Time	7.026
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
7.026	0.845	tNET	FF	1	R22C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R22C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
10.891	-0.035	tSu		1	R22C34[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 78.464%; tC2Q: 0.232, 21.536%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	3.987
Data Arrival Time	6.904
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.904	0.723	tNET	FF	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
10.891	-0.035	tSu		1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.723, 75.703%; tC2Q: 0.232, 24.297%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	3.987
Data Arrival Time	6.904
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.904	0.723	tNET	FF	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
10.891	-0.035	tSu		1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.723, 75.703%; tC2Q: 0.232, 24.297%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	3.987
Data Arrival Time	6.904
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.904	0.723	tNET	FF	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
10.891	-0.035	tSu		1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.723, 75.703%; tC2Q: 0.232, 24.297%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	3.987
Data Arrival Time	6.904
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.904	0.723	tNET	FF	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
10.891	-0.035	tSu		1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.723, 75.703%; tC2Q: 0.232, 24.297%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	3.988
Data Arrival Time	6.902
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.902	0.721	tNET	FF	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
10.891	-0.035	tSu		1	R20C34[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.667%; tC2Q: 0.232, 24.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	3.988
Data Arrival Time	6.902
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.902	0.721	tNET	FF	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
10.891	-0.035	tSu		1	R20C34[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.667%; tC2Q: 0.232, 24.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	3.988
Data Arrival Time	6.902
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.902	0.721	tNET	FF	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
10.891	-0.035	tSu		1	R21C33[0][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.667%; tC2Q: 0.232, 24.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	3.988
Data Arrival Time	6.902
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.902	0.721	tNET	FF	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
10.891	-0.035	tSu		1	R21C33[1][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.721, 75.667%; tC2Q: 0.232, 24.333%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	3.995
Data Arrival Time	6.896
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.896	0.715	tNET	FF	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
10.891	-0.035	tSu		1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 75.507%; tC2Q: 0.232, 24.493%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	3.995
Data Arrival Time	6.896
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.896	0.715	tNET	FF	1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
10.891	-0.035	tSu		1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 75.507%; tC2Q: 0.232, 24.493%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	3.995
Data Arrival Time	6.896
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.896	0.715	tNET	FF	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
10.891	-0.035	tSu		1	R20C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 75.507%; tC2Q: 0.232, 24.493%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	3.995
Data Arrival Time	6.896
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.896	0.715	tNET	FF	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
10.891	-0.035	tSu		1	R20C36[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 75.507%; tC2Q: 0.232, 24.493%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	3.995
Data Arrival Time	6.896
Data Required Time	10.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.688	0.688	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.949	0.261	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.181	0.232	tC2Q	FF	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.896	0.715	tNET	FF	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
10.682	0.683	tINS	RR	408	IOT27[A]	clk_ibuf/O
10.926	0.243	tNET	RR	1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
10.891	-0.035	tSu		1	R20C36[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-0.023
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.715, 75.507%; tC2Q: 0.232, 24.493%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.468
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R22C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
0.871	0.011	tHld		1	R22C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.691%; tC2Q: 0.202, 43.309%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	5.468
Data Arrival Time	6.338
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.338	0.264	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
0.871	0.011	tHld		1	R24C35[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.264, 56.691%; tC2Q: 0.202, 43.309%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	5.477
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R21C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871	0.011	tHld		1	R21C37[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.543%; tC2Q: 0.202, 42.457%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	5.477
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
0.871	0.011	tHld		1	R23C35[2][A]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.543%; tC2Q: 0.202, 42.457%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	5.477
Data Arrival Time	6.348
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.348	0.274	tNET	RR	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0/CLK
0.871	0.011	tHld		1	R23C35[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.274, 57.543%; tC2Q: 0.202, 42.457%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	5.590
Data Arrival Time	6.460
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.460	0.386	tNET	RR	1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871	0.011	tHld		1	R20C37[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.386, 65.670%; tC2Q: 0.202, 34.330%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	5.590
Data Arrival Time	6.460
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.460	0.386	tNET	RR	1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871	0.011	tHld		1	R20C37[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.386, 65.670%; tC2Q: 0.202, 34.330%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R22C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
0.871	0.011	tHld		1	R22C35[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.241%; tC2Q: 0.202, 33.759%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
0.871	0.011	tHld		1	R22C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.241%; tC2Q: 0.202, 33.759%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
0.871	0.011	tHld		1	R22C35[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.241%; tC2Q: 0.202, 33.759%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	5.600
Data Arrival Time	6.470
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.470	0.396	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
0.871	0.011	tHld		1	R22C35[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.396, 66.241%; tC2Q: 0.202, 33.759%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	5.600
Data Arrival Time	6.471
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.471	0.397	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
0.871	0.011	tHld		1	R21C36[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.397, 66.274%; tC2Q: 0.202, 33.726%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	5.600
Data Arrival Time	6.471
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.471	0.397	tNET	RR	1	R25C34[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C34[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R25C34[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.397, 66.274%; tC2Q: 0.202, 33.726%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	5.603
Data Arrival Time	6.474
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.474	0.400	tNET	RR	1	R25C35[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C35[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
0.871	0.011	tHld		1	R25C35[2][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 66.431%; tC2Q: 0.202, 33.569%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	5.603
Data Arrival Time	6.474
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.474	0.400	tNET	RR	1	R25C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R25C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK
0.871	0.011	tHld		1	R25C35[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.400, 66.431%; tC2Q: 0.202, 33.569%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	5.605
Data Arrival Time	6.476
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.476	0.402	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3/CLK
0.871	0.011	tHld		1	R21C35[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.544%; tC2Q: 0.202, 33.456%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	5.605
Data Arrival Time	6.476
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.476	0.402	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
0.871	0.011	tHld		1	R21C35[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.544%; tC2Q: 0.202, 33.456%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	5.605
Data Arrival Time	6.476
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.476	0.402	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
0.871	0.011	tHld		1	R21C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.544%; tC2Q: 0.202, 33.456%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	5.605
Data Arrival Time	6.476
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.476	0.402	tNET	RR	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871	0.011	tHld		1	R21C35[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.402, 66.544%; tC2Q: 0.202, 33.456%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	5.609
Data Arrival Time	6.480
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.480	0.406	tNET	RR	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
0.871	0.011	tHld		1	R27C36[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.773%; tC2Q: 0.202, 33.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	5.609
Data Arrival Time	6.480
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.480	0.406	tNET	RR	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871	0.011	tHld		1	R27C36[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.773%; tC2Q: 0.202, 33.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	5.609
Data Arrival Time	6.480
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.480	0.406	tNET	RR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
0.871	0.011	tHld		1	R27C36[0][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.773%; tC2Q: 0.202, 33.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	5.609
Data Arrival Time	6.480
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.480	0.406	tNET	RR	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
0.871	0.011	tHld		1	R27C36[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.406, 66.773%; tC2Q: 0.202, 33.227%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	5.624
Data Arrival Time	6.495
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.495	0.421	tNET	RR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
0.871	0.011	tHld		1	R20C35[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.556%; tC2Q: 0.202, 32.444%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	5.624
Data Arrival Time	6.495
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOT27[A]	clk_ibuf/I
5.677	0.678	tINS	FF	408	IOT27[A]	clk_ibuf/O
5.872	0.195	tNET	FF	1	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
6.074	0.202	tC2Q	FR	49	R24C37[2][B]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
6.495	0.421	tNET	RR	1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOT27[A]	clk_ibuf/I
0.675	0.675	tINS	RR	408	IOT27[A]	clk_ibuf/O
0.860	0.184	tNET	RR	1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.871	0.011	tHld		1	R20C36[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.421, 67.556%; tC2Q: 0.202, 32.444%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_9_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_9_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_9_s0/CLK

MPW2

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_7_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_7_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_7_s0/CLK

MPW3

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	counter_3_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	counter_3_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	counter_3_s0/CLK

MPW4

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	i_data_7_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	i_data_7_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	i_data_7_s1/CLK

MPW5

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[0].integrator_inst/add_out_18_s0/CLK

MPW6

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[1].integrator_inst/add_out_11_s0/CLK

MPW7

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/down_sample_inst/cnt_1_s0/CLK

MPW8

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_19_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_19_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_19_s0/CLK

MPW9

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_20_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_20_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/comb[3].comb_inst/comb_out_20_s0/CLK

MPW10

MPW Summary:

Slack:	3.911
Actual Width:	4.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_24_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
5.949	0.261	tNET	FF	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_24_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
10.860	0.184	tNET	RR	CIC_Fliter_tb/CIC_Filter/integrator[3].integrator_inst/add_out_24_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
408	clk_d	3.732	0.261
296	control0[0]	2.009	0.912
102	in_valid	7.792	1.941
69	n20_3	46.565	1.423
65	n743_5	44.329	1.488
49	rst_ao	3.732	0.978
49	data_out_shift_reg_46_7	44.329	1.111
47	n743_11	44.995	1.334
45	op_reg_en	45.829	0.947
39	comb_vaild_1[2]	7.881	1.852

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R25C25	90.28%
R22C26	88.89%
R22C25	88.89%
R25C35	88.89%
R29C32	87.50%
R30C30	87.50%
R22C27	86.11%
R30C31	86.11%
R34C26	84.72%
R20C25	84.72%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]