rtl_dir:=		../../project/src
tb_dir:=		../../tb
tb_file:=		$(tb_dir)/tb_vcs.v								

vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog 			\
	-v $(tb_dir)/prim_sim.v 							\
	$(tb_file)											\
	$(rtl_dir)/bch_encoder/bch_encoder.vo								\
	$(rtl_dir)/BCH_exp.v								\
	 -cm line+cond+fsm+branch+tgl


vd:
	verdi -sverilog										\
	-v $(tb_dir)/prim_sim.v 							\
	$(tb_file)											\
	$(rtl_dir)/bch_encoder/bch_encoder.vo								\
	$(rtl_dir)/BCH_exp.v								\
	-ssf verilog.fsdb										\
	&
reVd:
	./repair.sh tb
	verdi -ssr wave.ses &
#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf csrc simv.daidir simv.vdb verdiLog cm.log novas.conf novas.rc *.log simv verilog.fsdb ucli.key wave.ses.png 	./repair.sh tb
