| Report Title |
Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\impl\gwsynthesis\fpga_project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\demo.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\BCH_Encoder\Gowin_BCH_Encoder_RefDesign\project\src\fpga_project.sdc |
| Version |
V1.9.8.07 |
| Part Number |
GW2A-LV18PG256C8/I7 |
| Device |
GW2A-18 |
| Created Time |
Wed Jul 06 11:08:40 2022
|
| Legal Announcement |
Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
180.698 |
| Quiescent Power (mW) |
161.800 |
| Dynamic Power (mW) |
18.898 |
| Junction Temperature |
30.786 |
| Theta JA |
32.020 |
| Max Allowed Ambient Temperature |
79.214 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
16.171 |
102.291 |
118.462 |
| VCCX |
2.500 |
0.639 |
23.366 |
60.010 |
| VCCO12 |
1.200 |
0.020 |
0.012 |
0.038 |
| VCCO18 |
1.800 |
0.615 |
0.601 |
2.188 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
0.228 |
NA |
4.058 |
| IO |
6.630
| 3.262
| 10.000
|
| BSRAM |
15.282
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| BCH_exp |
15.510 |
15.510(15.498) |
| BCH_exp/BCH_Encoder_Top/ |
0.059 |
0.059(0.059) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/ |
0.059 |
0.059(0.020) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[0].deconv_shift/ |
0.003 |
0.003(0.000) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[1].deconv_shift/ |
0.003 |
0.003(0.000) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[2].deconv_shift/ |
0.003 |
0.003(0.000) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[3].deconv_shift/ |
0.003 |
0.003(0.000) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[4].deconv_shift/ |
0.003 |
0.003(0.000) |
| BCH_exp/BCH_Encoder_Top/BCH_Encoder/deconv_shift[5].deconv_shift/ |
0.004 |
0.004(0.000) |
| BCH_exp/gw_gao_inst_0/ |
15.438 |
15.438(15.438) |
| BCH_exp/gw_gao_inst_0/u_icon_top/ |
0.005 |
0.005(0.000) |
| BCH_exp/gw_gao_inst_0/u_la0_top/ |
15.433 |
15.433(15.342) |
| BCH_exp/gw_gao_inst_0/u_la0_top/u_ao_crc32/ |
0.010 |
0.010(0.000) |
| BCH_exp/gw_gao_inst_0/u_la0_top/u_ao_match_0/ |
0.002 |
0.002(0.000) |
| BCH_exp/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ |
15.329 |
15.329(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| SYM_CLK |
50.000 |
11.094 |
| tck_pad_i |
20.000 |
4.435 |