Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ahb_def_slave.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\BusMatrix.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_define.vh D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_static_macro_define.vh D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\can_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_adder.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ahb.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_alu_dec.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_core.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_ctl_add3.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_decoder.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_defs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_dp.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_excpt.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fetch.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_fns.vh D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mem_ctl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiplier.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_multiply_shift.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_mux4.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_ahb_os.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_defs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_main.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_lvl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_pri_num.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_tree.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_nvic_undefs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_reg_bank.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_shifter.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undef_check.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cm1_undefs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_miim_wrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_buffer_to_ahb.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_to_buffer.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_rx_wrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_sdp_wrapper_32bit.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_tx_wrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_ethmac_wrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_gpio.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ahbif_ctrl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_arbiter.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_async_fifo_clr.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_config.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_const.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_ctrl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_eilmif_ctrl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_fifo.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_gck.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_pad_lib.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_reg.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_regif_ctrl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_spiif.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_l2l.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_spi_flash_sync_p2p.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_ahb_to_iop.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_defs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_dualtimers_frc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_spi.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_timer.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_autocorrelation.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_balancefilter.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_collector.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_crngt_to_trng.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_inv_chain.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dx_trng_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_ff.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_interrupt_low.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_mux_clk.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_dxm_sync.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_ehr.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_entropy_gen.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_gtech_models.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_lfsr_new.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_line.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_noise_gen.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_pmf_table.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_prng_top_wrap.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_reg_file.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_engine.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_misc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rng_top_wrap_unconnected.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rosc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_rst_logic.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sample_cntr.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_slave_bus_ifc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_sync.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_tests_misc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_trng_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_uart.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_defs.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_apb_watchdog_frc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\cmsdk_iop_gpio.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1Integration.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\CortexM1IntegrationWrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_1_4code.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_define.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_name.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\ddr3_to_ahb_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\DDR3_TOP.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\dtcm.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Gowin_EMPU_M1_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinAhbExt.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExt.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\GowinCM1AhbExtWrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_ahb_psram.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_i2c.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_int_wrapper.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_apb_sd.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\gw_gpio.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\InputStage.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\itcm.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS0.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS1.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\MatrixDecodeS2.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb1.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb2.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputArb3.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage1.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage2.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\OutputStage3.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_ahb_to_apb.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\p_sse050_interconnect_f0_apb_slave_mux.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_code.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\psram_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_addr_params.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_cc_params.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\rng_params.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\Rtc.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcApbif.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcControl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcCounter.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcInterrupt.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcParams.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcRevAnd.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcSynctoPCLK.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\RtcUpdate.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_int_apb_decoder.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sse050_integration_peripherals.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\sync_p2p.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\GOWIN_EMPU_M1\data\no_debug\triple_speed_mac_name.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\temp\gw_empu_m1\cm1_option_defs.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\temp\gw_empu_m1\ahb_option_defs.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\temp\gw_empu_m1\can_parameter.vh D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_param.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\temp\gw_empu_m1\triple_speed_mac_define.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jul 06 17:20:07 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | Gowin_EMPU_M1_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 101.223MB Running netlist conversion: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 101.223MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.639s, Elapsed time = 0h 0m 0.656s, Peak memory usage = 101.223MB Optimizing Phase 1: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.173s, Peak memory usage = 101.223MB Optimizing Phase 2: CPU time = 0h 0m 0.748s, Elapsed time = 0h 0m 0.747s, Peak memory usage = 101.223MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 101.223MB Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 101.223MB Inferring Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 101.223MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 101.223MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.452s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 101.223MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.13s, Peak memory usage = 101.223MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.243s, Peak memory usage = 101.223MB Tech-Mapping Phase 3: CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s, Peak memory usage = 115.238MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.826s, Elapsed time = 0h 0m 0.83s, Peak memory usage = 115.238MB Generate output files: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.422s, Peak memory usage = 115.238MB |
| Total Time and Memory Usage | CPU time = 0h 0m 30s, Elapsed time = 0h 0m 31s, Peak memory usage = 115.238MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 126 |
| I/O Buf | 125 |
| IBUF | 37 |
| OBUF | 88 |
| Register | 1304 |
| DFF | 9 |
| DFFSE | 1 |
| DFFR | 3 |
| DFFRE | 1 |
| DFFP | 21 |
| DFFPE | 71 |
| DFFC | 248 |
| DFFCE | 950 |
| LUT | 3256 |
| LUT2 | 257 |
| LUT3 | 976 |
| LUT4 | 2023 |
| ALU | 43 |
| ALU | 43 |
| SSRAM | 16 |
| RAM16SDP4 | 16 |
| INV | 2 |
| INV | 2 |
| DSP | 1 |
| MULT36X36 | 1 |
| BSRAM | 40 |
| SP | 40 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 3397(3258 LUTs, 43 ALUs, 16 SSRAMs) / 20736 | 16% |
| Register | 1304 / 16173 | 8% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 1304 / 16173 | 8% |
| BSRAM | 40 / 46 | 87% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | HCLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | HCLK | 100.0(MHz) | 104.6(MHz) | 14 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 0.437 |
| Data Arrival Time | 10.391 |
| Data Required Time | 10.828 |
| From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.992 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/SUM |
| 6.229 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I1 |
| 6.784 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
| 7.021 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I1 |
| 7.576 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 7.813 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I3 |
| 8.184 | 0.371 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F |
| 8.421 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/I0 |
| 8.938 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/F |
| 9.175 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I3 |
| 9.546 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
| 9.783 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
| 10.154 | 0.371 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
| 10.391 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.452, 67.716%; route: 2.844, 29.849%; tC2Q: 0.232, 2.435% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 1.401 |
| Data Arrival Time | 9.426 |
| Data Required Time | 10.828 |
| From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 5.803 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
| 5.803 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
| 6.273 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
| 6.510 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I1 |
| 7.065 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
| 7.302 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2 |
| 7.755 | 0.453 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F |
| 7.992 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/I0 |
| 8.509 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s8/F |
| 8.746 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/I0 |
| 8.849 | 0.103 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s6/O |
| 9.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/I0 |
| 9.189 | 0.103 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/nxt_z_flag_mux_s3/O |
| 9.426 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/z_flag_mux_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.725, 66.848%; route: 2.607, 30.443%; tC2Q: 0.232, 2.709% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 1.435 |
| Data Arrival Time | 9.392 |
| Data Required Time | 10.828 |
| From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 5.803 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
| 5.803 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
| 6.273 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
| 6.510 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I1 |
| 7.065 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
| 7.302 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2 |
| 7.755 | 0.453 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F |
| 7.992 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
| 8.363 | 0.371 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
| 8.600 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I1 |
| 9.155 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F |
| 9.392 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.928, 69.494%; route: 2.370, 27.786%; tC2Q: 0.232, 2.720% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 1.435 |
| Data Arrival Time | 9.392 |
| Data Required Time | 10.828 |
| From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 5.803 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
| 5.803 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
| 6.273 | 0.470 | tINS | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/SUM |
| 6.510 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/I1 |
| 7.065 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s4/F |
| 7.302 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I2 |
| 7.755 | 0.453 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F |
| 7.992 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3 |
| 8.363 | 0.371 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F |
| 8.600 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I1 |
| 9.155 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F |
| 9.392 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 13 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.928, 69.494%; route: 2.370, 27.786%; tC2Q: 0.232, 2.720% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 2.595 |
| Data Arrival Time | 8.232 |
| Data Required Time | 10.828 |
| From | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0 |
| Launch Clk | HCLK[R] |
| Latch Clk | HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.557 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT |
| 5.557 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN |
| 5.592 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT |
| 5.592 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN |
| 5.627 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT |
| 5.627 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN |
| 5.662 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT |
| 5.662 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN |
| 5.698 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT |
| 5.698 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN |
| 5.733 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/COUT |
| 5.733 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/CIN |
| 5.768 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_24_s/COUT |
| 5.768 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/CIN |
| 5.803 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_25_s/COUT |
| 5.803 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/CIN |
| 5.838 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_26_s/COUT |
| 5.838 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/CIN |
| 5.874 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_27_s/COUT |
| 5.874 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/CIN |
| 5.909 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_28_s/COUT |
| 5.909 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/CIN |
| 5.944 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_29_s/COUT |
| 5.944 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/CIN |
| 5.979 | 0.035 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_30_s/COUT |
| 5.979 | 0.000 | tNET | FF | 2 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/CIN |
| 6.449 | 0.470 | tINS | FF | 6 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_31_s/SUM |
| 6.686 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/I1 |
| 7.241 | 0.555 | tINS | FF | 3 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/biu_addr_31_s/F |
| 7.478 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/I0 |
| 7.995 | 0.517 | tINS | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pre_fetch_addr_31_s0/F |
| 8.232 | 0.237 | tNET | FF | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_31_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 5.242, 71.125%; route: 1.896, 25.727%; tC2Q: 0.232, 3.148% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |