Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\AHB_to_AXI_Bridge\data\ahb2axi_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\ipcore\AHB_to_AXI_Bridge\data\ahb2axi_encrypt.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jul 06 10:29:20 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | AHB_to_AXI_Bridge_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.296s, Peak memory usage = 52.930MB Running netlist conversion: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 52.930MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 52.930MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 52.930MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 52.930MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 52.930MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 52.930MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 52.930MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 52.930MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 52.930MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 52.930MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 52.930MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.655s, Elapsed time = 0h 0m 0.708s, Peak memory usage = 64.145MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 64.145MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 64.145MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 64.145MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 307 |
| I/O Buf | 305 |
| IBUF | 123 |
| OBUF | 182 |
| Register | 162 |
| DFFP | 3 |
| DFFC | 104 |
| DFFCE | 55 |
| LUT | 95 |
| LUT2 | 16 |
| LUT3 | 29 |
| LUT4 | 50 |
| ALU | 4 |
| ALU | 4 |
| SSRAM | 19 |
| RAM16SDP4 | 19 |
| INV | 8 |
| INV | 8 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 221(103 LUTs, 4 ALUs, 19 SSRAMs) / 20736 | 1% |
| Register | 162 / 16173 | 1% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 162 / 16173 | 1% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| AHB_HCLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AHB_HCLK_ibuf/I | ||
| AXI_ACLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | AXI_ACLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | AHB_HCLK | 100.0(MHz) | 204.2(MHz) | 8 | TOP |
| 2 | AXI_ACLK | 100.0(MHz) | 239.0(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.103 |
| Data Arrival Time | 5.725 |
| Data Required Time | 10.828 |
| From | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_d1_s0 |
| To | ahb2axi_inst/u_rdata_fifo/empty_s0 |
| Launch Clk | AHB_HCLK[R] |
| Latch Clk | AHB_HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_d1_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_drop_rdata_d1_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/n117_s0/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | ahb2axi_inst/u_ahb2axi_ahb2fifo/n117_s0/F |
| 2.124 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_0_s4/I3 |
| 2.495 | 0.371 | tINS | FF | 6 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_0_s4/F |
| 2.732 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_1_s3/I1 |
| 3.287 | 0.555 | tINS | FF | 2 | ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_1_s3/F |
| 3.524 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_0_s1/I2 |
| 3.977 | 0.453 | tINS | FF | 2 | ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_0_s1/F |
| 4.214 | 0.237 | tNET | FF | 2 | ahb2axi_inst/u_rdata_fifo/n146_s0/I0 |
| 4.763 | 0.549 | tINS | FR | 1 | ahb2axi_inst/u_rdata_fifo/n146_s0/COUT |
| 4.763 | 0.000 | tNET | RR | 2 | ahb2axi_inst/u_rdata_fifo/n147_s0/CIN |
| 4.798 | 0.035 | tINS | RF | 1 | ahb2axi_inst/u_rdata_fifo/n147_s0/COUT |
| 5.035 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_rdata_fifo/next_empty_s1/I2 |
| 5.488 | 0.453 | tINS | FF | 1 | ahb2axi_inst/u_rdata_fifo/next_empty_s1/F |
| 5.725 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | ahb2axi_inst/u_rdata_fifo/empty_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.971, 61.108%; route: 1.659, 34.120%; tC2Q: 0.232, 4.772% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 5.226 |
| Data Arrival Time | 5.602 |
| Data Required Time | 10.828 |
| From | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0 |
| To | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0 |
| Launch Clk | AHB_HCLK[R] |
| Latch Clk | AHB_HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 14 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/DO[1] |
| 2.086 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/I3 |
| 2.457 | 0.371 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/F |
| 2.694 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/I3 |
| 3.065 | 0.371 | tINS | FF | 2 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/F |
| 3.302 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/I0 |
| 3.819 | 0.517 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/F |
| 4.056 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/I1 |
| 4.610 | 0.555 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/F |
| 4.847 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_nx_s0/I0 |
| 5.365 | 0.517 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_nx_s0/F |
| 5.602 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hreadyout_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.848, 60.097%; route: 1.659, 35.007%; tC2Q: 0.232, 4.896% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 5.230 |
| Data Arrival Time | 5.597 |
| Data Required Time | 10.828 |
| From | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0 |
| To | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1 |
| Launch Clk | AHB_HCLK[R] |
| Latch Clk | AHB_HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 14 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/DO[1] |
| 2.086 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/I3 |
| 2.457 | 0.371 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/F |
| 2.694 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/I3 |
| 3.065 | 0.371 | tINS | FF | 2 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/F |
| 3.302 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/I0 |
| 3.819 | 0.517 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/F |
| 4.056 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/I1 |
| 4.610 | 0.555 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/F |
| 4.847 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s3/I1 |
| 5.418 | 0.570 | tINS | FR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s3/F |
| 5.597 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1/CE |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/last_beat_error_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.901, 61.267%; route: 1.602, 33.833%; tC2Q: 0.232, 4.900% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 5.290 |
| Data Arrival Time | 5.537 |
| Data Required Time | 10.828 |
| From | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0 |
| To | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0 |
| Launch Clk | AHB_HCLK[R] |
| Latch Clk | AHB_HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 14 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/DO[1] |
| 2.086 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/I3 |
| 2.457 | 0.371 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/F |
| 2.694 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/I3 |
| 3.065 | 0.371 | tINS | FF | 2 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/F |
| 3.302 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/I0 |
| 3.819 | 0.517 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/F |
| 4.056 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/I1 |
| 4.610 | 0.555 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/F |
| 4.847 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_2cycle_nx_s0/I2 |
| 5.300 | 0.453 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_2cycle_nx_s0/F |
| 5.537 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/hresp_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.784, 59.550%; route: 1.659, 35.487%; tC2Q: 0.232, 4.963% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 5.372 |
| Data Arrival Time | 5.455 |
| Data Required Time | 10.828 |
| From | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0 |
| To | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_s0 |
| Launch Clk | AHB_HCLK[R] |
| Latch Clk | AHB_HCLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | AHB_HCLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 14 | ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 1 | ahb2axi_inst/u_rdata_fifo/mem_mem_0_8_s/DO[1] |
| 2.086 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/I3 |
| 2.457 | 0.371 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s3/F |
| 2.694 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/I3 |
| 3.065 | 0.371 | tINS | FF | 2 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s1/F |
| 3.302 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/I0 |
| 3.819 | 0.517 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/pend_rlast_nx_s0/F |
| 4.056 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/I1 |
| 4.610 | 0.555 | tINS | FF | 4 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s1/F |
| 4.847 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/I3 |
| 5.218 | 0.371 | tINS | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_nx_s3/F |
| 5.455 | 0.237 | tNET | FF | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | AHB_HCLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | AHB_HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 141 | AHB_HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | ahb2axi_inst/u_ahb2axi_ahb2fifo/error_first_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.702, 58.829%; route: 1.659, 36.120%; tC2Q: 0.232, 5.051% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |