Timing Messages

Report Title	Timing Analysis Report
Design File	D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\impl\gwsynthesis\gw_ahb2axi_ref_design.vg
Physical Constraints File	D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gw_ahb2axi_ref_design.cst
Timing Constraint File	D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gw_ahb2axi_ref_design.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Wed Jul 06 17:49:00 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	20230
Numbers of Endpoints Analyzed	11875
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Fall	Source	Master	Objects
tck_pad_i	Base	50.000	20.000	25.000			tck_pad_i
HCLK	Base	20.000	50.000	10.000			HCLK
MCU_CLK	Generated	12.500	80.000	6.250	HCLK	HCLK	MCU_CLK
pll_inst/rpll_inst/CLKOUTP.default_gen_clk	Generated	12.500	80.000	6.250	HCLK_ibuf/I	HCLK	pll_inst/rpll_inst/CLKOUTP
pll_inst/rpll_inst/CLKOUTD.default_gen_clk	Generated	25.000	40.000	12.500	HCLK_ibuf/I	HCLK	pll_inst/rpll_inst/CLKOUTD
pll_inst/rpll_inst/CLKOUTD3.default_gen_clk	Generated	37.500	26.667	18.750	HCLK_ibuf/I	HCLK	pll_inst/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	tck_pad_i	20.000(MHz)	144.738(MHz)	6	TOP
2	MCU_CLK	80.000(MHz)	82.068(MHz)	13	TOP

No timing paths to get frequency of HCLK!

No timing paths to get frequency of pll_inst/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of pll_inst/rpll_inst/CLKOUTD.default_gen_clk!

No timing paths to get frequency of pll_inst/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0
HCLK	Setup	0.000	0
HCLK	Hold	0.000	0
MCU_CLK	Setup	0.000	0
MCU_CLK	Hold	0.000	0
pll_inst/rpll_inst/CLKOUTP.default_gen_clk	Setup	0.000	0
pll_inst/rpll_inst/CLKOUTP.default_gen_clk	Hold	0.000	0
pll_inst/rpll_inst/CLKOUTD.default_gen_clk	Setup	0.000	0
pll_inst/rpll_inst/CLKOUTD.default_gen_clk	Hold	0.000	0
pll_inst/rpll_inst/CLKOUTD3.default_gen_clk	Setup	0.000	0
pll_inst/rpll_inst/CLKOUTD3.default_gen_clk	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	0.315	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	12.500	12.150
2	1.628	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_3_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.837
3	1.738	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_3_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.727
4	1.741	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_0_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.724
5	1.752	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_2_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.714
6	1.771	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_7_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.694
7	1.778	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.687
8	1.821	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DI[0]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.644
9	1.870	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.595
10	1.876	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.589
11	1.898	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s/DI[0]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.568
12	1.979	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_6_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.486
13	1.994	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_1_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.471
14	2.011	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.454
15	2.028	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_7_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.438
16	2.033	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.432
17	2.133	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_6_s/AD[1]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.333
18	2.161	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_2_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.304
19	2.207	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_7_s/AD[1]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.258
20	2.211	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_4_s/AD[1]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.254
21	2.230	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/AD[1]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.236
22	2.277	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_2_s/AD[2]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.189
23	2.303	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_1_s/AD[3]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.162
24	2.363	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/mem2_mem2_0_0_s/AD[3]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.103
25	2.363	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_7_s/AD[1]	MCU_CLK:[R]	MCU_CLK:[R]	12.500	10.103

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	0.307	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_1_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_1_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.318
2	0.307	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_2_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_2_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.318
3	0.311	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[3]	MCU_CLK:[R]	MCU_CLK:[R]	0.323
4	0.311	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_2_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[2]	MCU_CLK:[R]	MCU_CLK:[R]	0.323
5	0.311	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_1_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[1]	MCU_CLK:[R]	MCU_CLK:[R]	0.323
6	0.311	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_0_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[0]	MCU_CLK:[R]	MCU_CLK:[R]	0.323
7	0.314	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_22_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/DI[2]	MCU_CLK:[R]	MCU_CLK:[R]	0.326
8	0.314	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_21_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/DI[1]	MCU_CLK:[R]	MCU_CLK:[R]	0.326
9	0.322	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.333
10	0.323	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.334
11	0.326	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.337
12	0.326	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.337
13	0.326	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.337
14	0.327	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CE	MCU_CLK:[R]	MCU_CLK:[R]	0.338
15	0.425	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
16	0.425	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
17	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
18	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
19	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
20	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
21	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
22	0.425	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
23	0.425	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
24	0.425	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436
25	0.425	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/D	MCU_CLK:[R]	MCU_CLK:[R]	0.436

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Data Delay
1	8.464	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/mult_102_s2/RESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
2	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
3	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
4	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
5	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
6	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
7	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
8	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
9	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
10	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
11	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
12	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
13	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
14	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
15	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
16	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
17	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
18	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
19	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
20	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
21	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
22	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_0_s1/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
23	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_1_s1/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
24	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_2_s1/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785
25	8.680	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_f_0_s1/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	12.500	3.785

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Data Delay
1	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/a_signal_sync1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
2	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/b_signal_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
3	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/a_signal_sync1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
4	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/b_signal_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
5	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_s2/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
6	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_s2/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
7	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/mem_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
8	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/PRESET	MCU_CLK:[R]	MCU_CLK:[R]	1.047
9	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
10	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
11	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_2_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
12	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
13	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
14	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_2_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
15	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
16	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
17	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
18	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
19	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_2_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
20	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/full_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
21	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
22	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
23	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_2_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
24	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_0_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047
25	1.036	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_1_s0/CLEAR	MCU_CLK:[R]	MCU_CLK:[R]	1.047

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_deUstb/in_reg1_s0
2	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_deUstb/cnt_18_s0
3	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_deUstb/cnt_14_s0
4	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_deUstb/cnt_6_s0
5	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/uhalf_instr_11_s0
6	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/held_instr0_5_s0
7	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/use_primask_ex_s0
8	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/dreq_rd_ex_s0
9	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_5_s0
10	5.173	6.173	1.000	Low Pulse Width	MCU_CLK	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdata_31_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.315
Data Arrival Time	12.393
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK
0.475	0.232	tC2Q	RF	8	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q
1.735	1.260	tNET	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/RAD[1]
2.252	0.517	tINS	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/DO[0]
3.201	0.949	tNET	FF	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/I0
3.663	0.462	tINS	FR	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/F
3.665	0.001	tNET	RR	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/I1
4.182	0.517	tINS	RF	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/F
4.671	0.490	tNET	FF	1	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/I1
5.188	0.517	tINS	FF	2	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/F
5.877	0.688	tNET	FF	2	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/I1
6.248	0.371	tINS	FF	1	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
6.248	0.000	tNET	FF	2	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
6.283	0.035	tINS	FF	1	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
6.283	0.000	tNET	FF	2	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
6.318	0.035	tINS	FF	1	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
6.318	0.000	tNET	FF	2	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
6.353	0.035	tINS	FF	1	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
6.353	0.000	tNET	FF	2	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
6.389	0.035	tINS	FF	1	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
6.389	0.000	tNET	FF	2	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
6.859	0.470	tINS	FF	4	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/SUM
7.276	0.418	tNET	FF	1	R33C41[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I2
7.793	0.517	tINS	FF	2	R33C41[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F
8.289	0.496	tNET	FF	1	R29C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I1
8.742	0.453	tINS	FF	2	R29C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F
9.402	0.660	tNET	FF	1	R29C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I3
9.855	0.453	tINS	FF	2	R29C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F
10.349	0.494	tNET	FF	1	R25C36[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/I0
10.919	0.570	tINS	FR	1	R25C36[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/F
10.921	0.001	tNET	RR	1	R25C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I3
11.292	0.371	tINS	RF	1	R25C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F
11.931	0.640	tNET	FF	1	R29C36[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3
12.393	0.462	tINS	FR	1	R29C36[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F
12.393	0.000	tNET	RR	1	R29C36[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C36[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK
12.708	-0.035	tSu		1	R29C36[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	13
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 5.821, 47.908%; route: 6.097, 50.183%; tC2Q: 0.232, 1.909%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	1.628
Data Arrival Time	11.081
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_3_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
11.081	3.472	tNET	FF	1	BSRAM_R10[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_3_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_3_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_3_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.073%; route: 7.021, 64.786%; tC2Q: 0.232, 2.141%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	1.738
Data Arrival Time	10.971
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_3_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.971	3.362	tNET	FF	1	BSRAM_R46[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_3_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_3_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_3_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.411%; route: 6.911, 64.426%; tC2Q: 0.232, 2.163%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	1.741
Data Arrival Time	10.967
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_0_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.967	3.359	tNET	FF	1	BSRAM_R28[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_0_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_0_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[0]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.422%; route: 6.908, 64.415%; tC2Q: 0.232, 2.163%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	1.752
Data Arrival Time	10.957
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_2_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.957	3.348	tNET	FF	1	BSRAM_R46[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_2_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_2_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_2_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.455%; route: 6.897, 64.380%; tC2Q: 0.232, 2.165%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	1.771
Data Arrival Time	10.938
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_7_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.938	3.329	tNET	FF	1	BSRAM_R10[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_7_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_7_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[5]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_7_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.515%; route: 6.878, 64.316%; tC2Q: 0.232, 2.169%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	1.778
Data Arrival Time	10.930
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK
0.475	0.232	tC2Q	RF	8	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q
1.735	1.260	tNET	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/RAD[1]
2.252	0.517	tINS	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/DO[0]
3.201	0.949	tNET	FF	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/I0
3.663	0.462	tINS	FR	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/F
3.665	0.001	tNET	RR	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/I1
4.182	0.517	tINS	RF	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/F
4.671	0.490	tNET	FF	1	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/I1
5.188	0.517	tINS	FF	2	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/F
5.877	0.688	tNET	FF	2	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/I1
6.248	0.371	tINS	FF	1	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
6.248	0.000	tNET	FF	2	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
6.283	0.035	tINS	FF	1	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
6.283	0.000	tNET	FF	2	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
6.318	0.035	tINS	FF	1	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
6.318	0.000	tNET	FF	2	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
6.353	0.035	tINS	FF	1	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
6.353	0.000	tNET	FF	2	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
6.389	0.035	tINS	FF	1	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
6.389	0.000	tNET	FF	2	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
6.424	0.035	tINS	FF	1	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
6.424	0.000	tNET	FF	2	R31C42[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
6.459	0.035	tINS	FF	1	R31C42[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
6.459	0.000	tNET	FF	2	R31C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
6.494	0.035	tINS	FF	1	R31C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
6.494	0.000	tNET	FF	2	R31C42[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
6.529	0.035	tINS	FF	1	R31C42[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
6.529	0.000	tNET	FF	2	R31C42[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
6.565	0.035	tINS	FF	1	R31C42[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
6.565	0.000	tNET	FF	2	R31C42[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
6.600	0.035	tINS	FF	1	R31C42[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
6.600	0.000	tNET	FF	2	R31C43[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
7.070	0.470	tINS	FF	4	R31C43[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/SUM
7.496	0.427	tNET	FF	1	R30C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I0
8.066	0.570	tINS	FR	1	R30C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F
8.239	0.172	tNET	RR	1	R30C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I3
8.756	0.517	tINS	RF	3	R30C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
9.554	0.798	tNET	FF	1	R23C35[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3
10.109	0.555	tINS	FF	2	R23C35[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F
10.360	0.252	tNET	FF	1	R25C35[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/I1
10.930	0.570	tINS	FR	1	R25C35[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s0/F
10.930	0.000	tNET	RR	1	R25C35[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R25C35[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0/CLK
12.708	-0.035	tSu		1	R25C35[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/itcm_sel_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 5.418, 50.698%; route: 5.037, 47.131%; tC2Q: 0.232, 2.171%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	1.821
Data Arrival Time	10.888
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[0]
2.957	1.064	tNET	FF	1	R27C45[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_0_s1/I1
3.328	0.371	tINS	FF	1	R27C45[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_0_s1/F
3.332	0.004	tNET	FF	1	R27C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_0_s0/I0
3.703	0.371	tINS	FF	2	R27C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_0_s0/F
4.635	0.931	tNET	FF	1	R30C39[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s18/I2
5.088	0.453	tINS	FF	2	R30C39[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s18/F
5.749	0.662	tNET	FF	1	R30C44[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s2/I1
6.304	0.555	tINS	FF	1	R30C44[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s2/F
7.231	0.927	tNET	FF	1	R24C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s0/I3
7.748	0.517	tINS	FF	1	R24C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s0/F
8.161	0.413	tNET	FF	1	R21C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s/I1
8.678	0.517	tINS	FF	3	R21C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s/F
9.343	0.665	tNET	FF	1	R18C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_0_s0/I1
9.714	0.371	tINS	FF	2	R18C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_0_s0/F
10.888	1.174	tNET	FF	1	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/CLK
12.709	-0.035	tSu		1	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.672, 34.497%; route: 6.740, 63.324%; tC2Q: 0.232, 2.180%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	1.870
Data Arrival Time	10.838
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R26C19[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/CLK
0.475	0.232	tC2Q	RF	85	R26C19[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uInputStage0/PendTranReg_s1/Q
1.430	0.955	tNET	FF	1	R27C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HADDR_d_31_s0/I2
1.985	0.555	tINS	FF	6	R27C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HADDR_d_31_s0/F
2.421	0.435	tNET	FF	1	R29C20[3][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/uOutputArb/NoPortNext_s3/I3
2.874	0.453	tINS	FF	5	R29C20[3][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage12/uOutputArb/NoPortNext_s3/F
3.300	0.426	tNET	FF	1	R26C20[0][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/NoPortNext_s2/I3
3.855	0.555	tINS	FF	3	R26C20[0][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/uOutputArb/NoPortNext_s2/F
4.112	0.257	tNET	FF	1	R26C18[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HSEL_d_s2/I1
4.667	0.555	tINS	FF	4	R26C18[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage11/AHB1HSEL_d_s2/F
5.741	1.074	tNET	FF	1	R40C10[3][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/valid_rd_ap_s0/I2
6.258	0.517	tINS	FF	7	R40C10[3][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/valid_rd_ap_s0/F
6.510	0.252	tNET	FF	1	R42C10[3][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_0_s4/I1
7.065	0.555	tINS	FF	6	R42C10[3][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_0_s4/F
7.659	0.595	tNET	FF	1	R40C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_2_s2/I2
8.176	0.517	tINS	FF	3	R40C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_bin_rd_ptr_2_s2/F
8.582	0.406	tNET	FF	1	R40C10[3][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_1_s1/I3
9.131	0.549	tINS	FR	2	R40C10[3][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_gray_rd_ptr_1_s1/F
9.276	0.146	tNET	RR	2	R40C10[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/n147_s0/I0
9.793	0.517	tINS	RF	1	R40C10[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/n147_s0/COUT
10.268	0.474	tNET	FF	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_empty_s1/I2
10.838	0.570	tINS	FR	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/next_empty_s1/F
10.838	0.000	tNET	RR	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/CLK
12.708	-0.035	tSu		1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	11
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 5.343, 50.432%; route: 5.020, 47.379%; tC2Q: 0.232, 2.190%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	1.876
Data Arrival Time	10.832
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.832	3.224	tNET	FF	1	BSRAM_R28[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[3]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_1_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 33.849%; route: 6.773, 63.960%; tC2Q: 0.232, 2.191%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	1.898
Data Arrival Time	10.811
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[0]
2.957	1.064	tNET	FF	1	R27C45[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_0_s1/I1
3.328	0.371	tINS	FF	1	R27C45[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_0_s1/F
3.332	0.004	tNET	FF	1	R27C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_0_s0/I0
3.703	0.371	tINS	FF	2	R27C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_0_s0/F
4.635	0.931	tNET	FF	1	R30C39[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s18/I2
5.088	0.453	tINS	FF	2	R30C39[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/n1629_s18/F
5.749	0.662	tNET	FF	1	R30C44[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s2/I1
6.304	0.555	tINS	FF	1	R30C44[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s2/F
7.231	0.927	tNET	FF	1	R24C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s0/I3
7.748	0.517	tINS	FF	1	R24C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s0/F
8.161	0.413	tNET	FF	1	R21C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s/I1
8.678	0.517	tINS	FF	3	R21C41[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_rf1_mux/dp_ipsr_0_s/F
9.343	0.665	tNET	FF	1	R18C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_0_s0/I1
9.714	0.371	tINS	FF	2	R18C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/rf_wdata_0_s0/F
10.811	1.097	tNET	FF	1	R23C40	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R23C40	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s/CLK
12.709	-0.035	tSu		1	R23C40	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	9
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.672, 34.747%; route: 6.664, 63.058%; tC2Q: 0.232, 2.195%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	1.979
Data Arrival Time	10.730
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_6_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.730	3.121	tNET	FF	1	BSRAM_R28[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_6_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_6_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_6_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 34.180%; route: 6.670, 63.608%; tC2Q: 0.232, 2.212%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	1.994
Data Arrival Time	10.715
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_1_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.715	3.106	tNET	FF	1	BSRAM_R28[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_1_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_1_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_1_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 34.229%; route: 6.655, 63.556%; tC2Q: 0.232, 2.216%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	2.011
Data Arrival Time	10.697
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.697	3.089	tNET	FF	1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 34.285%; route: 6.638, 63.496%; tC2Q: 0.232, 2.219%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	2.028
Data Arrival Time	10.681
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_7_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.681	3.073	tNET	FF	1	BSRAM_R10[15]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_7_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[15]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_7_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[15]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_7_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 34.339%; route: 6.622, 63.438%; tC2Q: 0.232, 2.223%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	2.033
Data Arrival Time	10.675
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK
0.475	0.232	tC2Q	RF	8	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q
1.735	1.260	tNET	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/RAD[1]
2.252	0.517	tINS	FF	4	R32C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_3_s0/DO[0]
3.201	0.949	tNET	FF	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/I0
3.663	0.462	tINS	FR	1	R26C36[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s2/F
3.665	0.001	tNET	RR	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/I1
4.182	0.517	tINS	RF	1	R26C36[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_12_s1/F
4.671	0.490	tNET	FF	1	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/I1
5.188	0.517	tINS	FF	2	R30C36[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_12_s0/F
5.877	0.688	tNET	FF	2	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/I1
6.248	0.371	tINS	FF	1	R31C41[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT
6.248	0.000	tNET	FF	2	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN
6.283	0.035	tINS	FF	1	R31C41[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT
6.283	0.000	tNET	FF	2	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN
6.318	0.035	tINS	FF	1	R31C41[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT
6.318	0.000	tNET	FF	2	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN
6.353	0.035	tINS	FF	1	R31C41[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT
6.353	0.000	tNET	FF	2	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN
6.389	0.035	tINS	FF	1	R31C41[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT
6.389	0.000	tNET	FF	2	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN
6.424	0.035	tINS	FF	1	R31C42[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT
6.424	0.000	tNET	FF	2	R31C42[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN
6.459	0.035	tINS	FF	1	R31C42[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/COUT
6.459	0.000	tNET	FF	2	R31C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/CIN
6.494	0.035	tINS	FF	1	R31C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_19_s/COUT
6.494	0.000	tNET	FF	2	R31C42[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/CIN
6.529	0.035	tINS	FF	1	R31C42[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_20_s/COUT
6.529	0.000	tNET	FF	2	R31C42[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/CIN
6.565	0.035	tINS	FF	1	R31C42[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_21_s/COUT
6.565	0.000	tNET	FF	2	R31C42[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/CIN
6.600	0.035	tINS	FF	1	R31C42[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_22_s/COUT
6.600	0.000	tNET	FF	2	R31C43[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/CIN
7.070	0.470	tINS	FF	4	R31C43[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_23_s/SUM
7.496	0.427	tNET	FF	1	R30C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/I0
8.066	0.570	tINS	FR	1	R30C42[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s5/F
8.239	0.172	tNET	RR	1	R30C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/I3
8.756	0.517	tINS	RF	3	R30C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s0/F
9.554	0.798	tNET	FF	1	R23C35[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/I3
10.124	0.570	tINS	FR	2	R23C35[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s2/F
10.126	0.003	tNET	RR	1	R23C35[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/I1
10.675	0.549	tINS	RR	1	R23C35[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_dtcm_sel_s0/F
10.675	0.000	tNET	RR	1	R23C35[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R23C35[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0/CLK
12.708	-0.035	tSu		1	R23C35[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/dtcm_sel_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	12
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 5.412, 51.879%; route: 4.788, 45.897%; tC2Q: 0.232, 2.224%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	2.133
Data Arrival Time	10.576
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_6_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.576	3.403	tNET	FF	1	BSRAM_R10[2]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_6_s/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[2]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_6_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[2]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_6_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 33.728%; route: 6.616, 64.027%; tC2Q: 0.232, 2.245%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	2.161
Data Arrival Time	10.547
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_2_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.547	2.939	tNET	FF	1	BSRAM_R10[12]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_2_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[12]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_2_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[12]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_2_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 34.785%; route: 6.488, 62.964%; tC2Q: 0.232, 2.252%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	2.207
Data Arrival Time	10.502
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_7_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.502	3.329	tNET	FF	1	BSRAM_R28[1]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_7_s/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[1]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_7_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[1]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem3_mem3_0_7_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 33.973%; route: 6.541, 63.766%; tC2Q: 0.232, 2.262%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	2.211
Data Arrival Time	10.497
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_4_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.497	3.325	tNET	FF	1	BSRAM_R46[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_4_s/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_4_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_4_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 33.986%; route: 6.537, 63.751%; tC2Q: 0.232, 2.263%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	2.230
Data Arrival Time	10.479
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.479	3.306	tNET	FF	1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s/CLK
12.709	-0.035	tSu		1	BSRAM_R10[6]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_4_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 34.047%; route: 6.519, 63.686%; tC2Q: 0.232, 2.267%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	2.277
Data Arrival Time	10.432
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_2_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
5.608	0.035	tINS	FF	1	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT
5.608	0.000	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN
6.078	0.470	tINS	FF	4	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/SUM
7.091	1.014	tNET	FF	1	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/I2
7.608	0.517	tINS	FF	42	R25C40[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_4_s/F
10.432	2.824	tNET	FF	1	BSRAM_R46[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_2_s/AD[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_2_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem1_mem1_0_2_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.584, 35.179%; route: 6.372, 62.544%; tC2Q: 0.232, 2.277%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	2.303
Data Arrival Time	10.405
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_1_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/CLK
0.475	0.232	tC2Q	RF	8	R11C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_1_s0/Q
1.436	0.961	tNET	FF	4	R24C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/RAD[1]
1.953	0.517	tINS	FF	8	R24C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_1_s0/DO[0]
2.632	0.678	tNET	FF	1	R24C44[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/I0
3.181	0.549	tINS	FR	1	R24C44[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s2/F
3.353	0.172	tNET	RR	1	R24C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/I1
3.870	0.517	tINS	RF	1	R24C45[3][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_4_s1/F
4.117	0.247	tNET	FF	1	R26C45[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/I1
4.488	0.371	tINS	FF	2	R26C45[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_4_s0/F
5.448	0.959	tNET	FF	2	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/I1
5.819	0.371	tINS	FF	1	R31C39[2][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT
5.819	0.000	tNET	FF	2	R31C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN
6.289	0.470	tINS	FF	4	R31C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/SUM
6.821	0.533	tNET	FF	1	R27C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_5_s/I1
7.192	0.371	tINS	FF	42	R27C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_5_s/F
10.405	3.213	tNET	FF	1	BSRAM_R46[9]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_1_s/AD[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[9]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_1_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[9]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem0_mem0_0_1_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.166, 31.156%; route: 6.764, 66.561%; tC2Q: 0.232, 2.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	2.363
Data Arrival Time	10.346
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/mem2_mem2_0_0_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.346	3.173	tNET	FF	1	BSRAM_R28[7]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/mem2_mem2_0_0_s/AD[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R28[7]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/mem2_mem2_0_0_s/CLK
12.709	-0.035	tSu		1	BSRAM_R28[7]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_dtcm/mem2_mem2_0_0_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 34.496%; route: 6.386, 63.208%; tC2Q: 0.232, 2.296%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	2.363
Data Arrival Time	10.346
Data Required Time	12.709
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_7_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK
0.475	0.232	tC2Q	RF	8	R17C37[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q
1.376	0.901	tNET	FF	4	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0]
1.893	0.517	tINS	FF	7	R23C39	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2]
2.582	0.689	tNET	FF	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0
3.152	0.570	tINS	FR	1	R21C43[3][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F
3.153	0.001	tNET	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1
3.702	0.549	tINS	RR	1	R21C43[0][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F
3.703	0.001	tNET	RR	1	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1
4.258	0.555	tINS	RF	2	R21C43[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F
5.202	0.943	tNET	FF	2	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1
5.573	0.371	tINS	FF	1	R31C39[1][B]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT
5.573	0.000	tNET	FF	2	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN
6.043	0.470	tINS	FF	4	R31C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/SUM
6.720	0.677	tNET	FF	1	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/I2
7.173	0.453	tINS	FF	42	R25C39[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/DTCMADDR_Z_3_s/F
10.346	3.173	tNET	FF	1	BSRAM_R46[8]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_7_s/AD[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	BSRAM_R46[8]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_7_s/CLK
12.709	-0.035	tSu		1	BSRAM_R46[8]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_itcm/mem2_mem2_0_7_s

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	8
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 3.485, 34.496%; route: 6.386, 63.208%; tC2Q: 0.232, 2.296%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.307
Data Arrival Time	0.502
Data Required Time	0.195
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_1_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R44C8[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_1_s0/CLK
0.385	0.201	tC2Q	RF	1	R44C8[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_1_s0/Q
0.502	0.117	tNET	FF	1	R44C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R44C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_1_s0/CLK
0.195	0.011	tHld		1	R44C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack	0.307
Data Arrival Time	0.502
Data Required Time	0.195
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_2_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_2_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R45C9[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_2_s0/CLK
0.385	0.201	tC2Q	RF	1	R45C9[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync1_2_s0/Q
0.502	0.117	tNET	FF	1	R45C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R45C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_2_s0/CLK
0.195	0.011	tHld		1	R45C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/gray_wr_ptr_sync2_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 36.787%; tC2Q: 0.201, 63.213%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack	0.311
Data Arrival Time	0.507
Data Required Time	0.196
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R43C12[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_3_s0/CLK
0.385	0.201	tC2Q	RF	1	R43C12[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_3_s0/Q
0.507	0.122	tNET	FF	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/CLK
0.196	0.012	tHld		1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack	0.311
Data Arrival Time	0.507
Data Required Time	0.196
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_2_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R43C12[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_2_s0/CLK
0.385	0.201	tC2Q	RF	1	R43C12[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_2_s0/Q
0.507	0.122	tNET	FF	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/CLK
0.196	0.012	tHld		1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack	0.311
Data Arrival Time	0.507
Data Required Time	0.196
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_1_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R43C12[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_1_s0/CLK
0.385	0.201	tC2Q	RF	1	R43C12[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_1_s0/Q
0.507	0.122	tNET	FF	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/CLK
0.196	0.012	tHld		1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack	0.311
Data Arrival Time	0.507
Data Required Time	0.196
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_0_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R43C12[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_0_s0/CLK
0.385	0.201	tC2Q	RF	1	R43C12[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_ahb2axi_ahb2fifo/wstrb_0_s0/Q
0.507	0.122	tNET	FF	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s/CLK
0.196	0.012	tHld		1	R42C12	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wdata_fifo/mem_mem_0_8_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack	0.314
Data Arrival Time	0.510
Data Required Time	0.196
From	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_22_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R41C11[2][A]	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_22_s0/CLK
0.385	0.201	tC2Q	RF	2	R41C11[2][A]	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_22_s0/Q
0.510	0.125	tNET	FF	1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/CLK
0.196	0.012	tHld		1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack	0.314
Data Arrival Time	0.510
Data Required Time	0.196
From	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_21_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R41C11[2][B]	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_21_s0/CLK
0.385	0.201	tC2Q	RF	2	R41C11[2][B]	u_axi4_lite_slave_top/axi_ip_slave_v1_0_S00_AXI_inst/axi_rdata_21_s0/Q
0.510	0.125	tNET	FF	1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14/CLK
0.196	0.012	tHld		1	R41C10	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s14

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.125, 38.377%; tC2Q: 0.201, 61.623%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack	0.322
Data Arrival Time	0.517
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R29C22[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/CLK
0.386	0.202	tC2Q	RR	6	R29C22[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/Q
0.517	0.131	tNET	RR	1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CLK
0.195	0.011	tHld		1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.131, 39.314%; tC2Q: 0.202, 60.686%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack	0.323
Data Arrival Time	0.518
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R27C30[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/CLK
0.386	0.202	tC2Q	RR	2	R27C30[2][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/haddr_en_reg_s0/Q
0.518	0.132	tNET	RR	1	R27C30[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R27C30[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0/CLK
0.195	0.011	tHld		1	R27C30[1][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/asel_ppb_reg_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.132, 39.550%; tC2Q: 0.202, 60.450%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack	0.326
Data Arrival Time	0.521
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R30C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/CLK
0.386	0.202	tC2Q	RR	4	R30C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/Q
0.521	0.135	tNET	RR	1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CLK
0.195	0.011	tHld		1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 39.989%; tC2Q: 0.202, 60.011%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack	0.326
Data Arrival Time	0.521
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R29C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/CLK
0.386	0.202	tC2Q	RR	4	R29C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/Q
0.521	0.135	tNET	RR	1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CLK
0.195	0.011	tHld		1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 39.989%; tC2Q: 0.202, 60.011%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack	0.326
Data Arrival Time	0.521
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R30C22[0][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/CLK
0.386	0.202	tC2Q	RR	5	R30C22[0][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HREADYOUT_s0/Q
0.521	0.135	tNET	RR	1	R30C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R30C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0/CLK
0.195	0.011	tHld		1	R30C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_can/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 39.989%; tC2Q: 0.202, 60.011%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack	0.327
Data Arrival Time	0.522
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R34C22[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/CLK
0.386	0.202	tC2Q	RR	5	R34C22[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/Q
0.522	0.136	tNET	RR	1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CLK
0.195	0.011	tHld		1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.136, 40.206%; tC2Q: 0.202, 59.794%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/CLK
0.386	0.202	tC2Q	RR	4	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/Q
0.389	0.002	tNET	RR	1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/n157_s2/I0
0.621	0.232	tINS	RF	1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/n157_s2/F
0.621	0.000	tNET	FF	1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1/CLK
0.195	0.011	tHld		1	R39C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/rd_ptr_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/CLK
0.386	0.202	tC2Q	RR	3	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/Q
0.389	0.002	tNET	RR	1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/n101_s2/I0
0.621	0.232	tINS	RF	1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/n101_s2/F
0.621	0.000	tNET	FF	1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1/CLK
0.195	0.011	tHld		1	R39C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_cmd_buff/wr_ptr_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/CLK
0.386	0.202	tC2Q	RR	3	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/Q
0.389	0.002	tNET	RR	1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_tx_tick_cnt_1_s1/I3
0.621	0.232	tINS	RF	1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_tx_tick_cnt_1_s1/F
0.621	0.000	tNET	FF	1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0/CLK
0.195	0.011	tHld		1	R13C23[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/CLK
0.386	0.202	tC2Q	RR	2	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/Q
0.389	0.002	tNET	RR	1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_tx_tick_cnt_3_s1/I1
0.621	0.232	tINS	RF	1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_tx_tick_cnt_3_s1/F
0.621	0.000	tNET	FF	1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0/CLK
0.195	0.011	tHld		1	R13C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/tx_tick_cnt_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/CLK
0.386	0.202	tC2Q	RR	5	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/Q
0.389	0.002	tNET	RR	1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_baud_cntr_i_3_s0/I1
0.621	0.232	tINS	RF	1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_baud_cntr_i_3_s0/F
0.621	0.000	tNET	FF	1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0/CLK
0.195	0.011	tHld		1	R9C21[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/CLK
0.386	0.202	tC2Q	RR	5	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/Q
0.389	0.002	tNET	RR	1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_baud_cntr_i_7_s0/I1
0.621	0.232	tINS	RF	1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/nxt_baud_cntr_i_7_s0/F
0.621	0.000	tNET	FF	1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0/CLK
0.195	0.011	tHld		1	R7C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_i_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/CLK
0.386	0.202	tC2Q	RR	2	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/Q
0.389	0.002	tNET	RR	1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/n48_s3/I0
0.621	0.232	tINS	RF	1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/n48_s3/F
0.621	0.000	tNET	FF	1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3/CLK
0.195	0.011	tHld		1	R34C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage10/uOutputArb/iNoPort_s3

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/CLK
0.386	0.202	tC2Q	RR	2	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/Q
0.389	0.002	tNET	RR	1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/AHB6HSEL_s1/I0
0.621	0.232	tINS	RF	1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/AHB6HSEL_s1/F
0.621	0.000	tNET	FF	1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1/CLK
0.195	0.011	tHld		1	R31C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gowinahbext/u_bus_matrix/uOutputstage9/SlaveSel_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/CLK
0.386	0.202	tC2Q	RR	3	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/Q
0.389	0.002	tNET	RR	1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/nxt_tck_count_23_s1/I2
0.621	0.232	tINS	RF	1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/nxt_tck_count_23_s1/F
0.621	0.000	tNET	FF	1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0/CLK
0.195	0.011	tHld		1	R9C26[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_nvic/u_ahb_os/tck_count_23_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/CLK
0.386	0.202	tC2Q	RR	2	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/Q
0.389	0.002	tNET	RR	1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex2_6_s1/I0
0.621	0.232	tINS	RF	1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex2_6_s1/F
0.621	0.000	tNET	FF	1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0/CLK
0.195	0.011	tHld		1	R8C40[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack	0.425
Data Arrival Time	0.621
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/CLK
0.386	0.202	tC2Q	RR	2	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/Q
0.389	0.002	tNET	RR	1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex2_9_s1/I0
0.621	0.232	tINS	RF	1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex2_9_s1/F
0.621	0.000	tNET	FF	1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0/CLK
0.195	0.011	tHld		1	R13C45[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/imm_ex_9_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.464
Data Arrival Time	4.028
Data Required Time	12.492
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/mult_102_s2
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	72	DSP_R19[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/mult_102_s2/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	DSP_R19[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/mult_102_s2/CLK
12.492	-0.251	tSu		1	DSP_R19[4]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mul_shft/u_mul/mult_102_s2

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path2

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R34C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R34C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R34C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path3

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R33C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R33C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R33C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb5/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path4

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R30C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R30C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R30C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path5

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R30C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb12/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path6

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C17[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C17[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R29C17[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path7

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C19[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C19[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R29C19[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb11/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path8

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R29C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path9

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R29C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb10/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path10

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R34C22[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R34C22[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R34C22[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path11

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R34C22[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb9/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path12

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R32C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R32C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R32C21[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path13

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R31C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R31C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R31C20[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb4/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path14

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R30C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R30C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R30C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path15

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R29C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb6/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path16

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R31C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R31C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R31C20[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path17

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R29C20[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_internet/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path18

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R32C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R32C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R32C21[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path19

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R31C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R31C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R31C21[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_spi_flash/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path20

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C22[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C22[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0/CLK
12.708	-0.035	tSu		1	R29C22[2][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HREADYOUT_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path21

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0/CLK
12.708	-0.035	tSu		1	R29C22[0][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_ahb_apb2/HRESP_0_s0

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path22

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_0_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R12C18[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R12C18[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_0_s1/CLK
12.708	-0.035	tSu		1	R12C18[2][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path23

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_1_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R12C18[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R12C18[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_1_s1/CLK
12.708	-0.035	tSu		1	R12C18[1][B]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path24

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_2_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R12C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R12C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_2_s1/CLK
12.708	-0.035	tSu		1	R12C18[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/rx_tick_cnt_2_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Path25

Path Summary:

Slack	8.680
Data Arrival Time	4.028
Data Required Time	12.708
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_f_0_s1
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.243	0.243	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.475	0.232	tC2Q	RF	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
2.029	1.554	tNET	FF	1	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/I0
2.400	0.371	tINS	FF	1291	R17C6[0][A]	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/n74_s2/F
4.028	1.628	tNET	FF	1	R8C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_f_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
12.500	12.500					active clock edge time
12.500	0.000					MCU_CLK
12.500	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
12.743	0.243	tNET	RR	1	R8C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_f_0_s1/CLK
12.708	-0.035	tSu		1	R8C22[1][A]	u_Gowin_EMPU_M1_Top/u_GowinCM1AhbExtWrapper/u_GowinCM1AhbExt/u_gw_apb_int_wrapper/u_integration_peripherals/u_cmsdk_apb_uart_0/reg_baud_cntr_f_0_s1

Path Statistics:

Clock Skew	0.000
Setup Relationship	12.500
Logic Level	2
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%
Arrival Data Path Delay	cell: 0.371, 9.803%; route: 3.182, 84.067%; tC2Q: 0.232, 6.130%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.243, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/a_signal_sync1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C10[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/a_signal_sync1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C10[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/a_signal_sync1_s0/CLK
0.195	0.011	tHld		1	R39C10[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/a_signal_sync1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path2

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/b_signal_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C10[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/b_signal_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C10[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/b_signal_s0/CLK
0.195	0.011	tHld		1	R39C10[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_sync/b_signal_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path3

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/a_signal_sync1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C10[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/a_signal_sync1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C10[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/a_signal_sync1_s0/CLK
0.195	0.011	tHld		1	R39C10[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/a_signal_sync1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path4

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/b_signal_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C10[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/b_signal_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C10[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/b_signal_s0/CLK
0.195	0.011	tHld		1	R39C10[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_sync/b_signal_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path5

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_s2
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_s2/CLK
0.195	0.011	tHld		1	R39C9[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/rd_ptr_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path6

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_s2
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C10[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_s2/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C10[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_s2/CLK
0.195	0.011	tHld		1	R39C10[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/wr_ptr_s2

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path7

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/mem_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C11[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/mem_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C11[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/mem_0_s0/CLK
0.195	0.011	tHld		1	R40C11[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_wresp_buff/mem_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path8

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0/CLK
0.195	0.011	tHld		1	R40C10[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/empty_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path9

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C7[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C7[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_0_s0/CLK
0.195	0.011	tHld		1	R39C7[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path10

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C7[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C7[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_1_s0/CLK
0.195	0.011	tHld		1	R39C7[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path11

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_2_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C11[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C11[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_2_s0/CLK
0.195	0.011	tHld		1	R40C11[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync2_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path12

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C7[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C7[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_0_s0/CLK
0.195	0.011	tHld		1	R39C7[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path13

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C7[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C7[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_1_s0/CLK
0.195	0.011	tHld		1	R39C7[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path14

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_2_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C11[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C11[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_2_s0/CLK
0.195	0.011	tHld		1	R40C11[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_wr_ptr_sync1_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path15

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C9[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C9[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_0_s0/CLK
0.195	0.011	tHld		1	R40C9[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path16

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C8[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C8[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_1_s0/CLK
0.195	0.011	tHld		1	R40C8[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path17

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0/CLK
0.195	0.011	tHld		1	R40C9[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path18

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C9[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C9[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_1_s0/CLK
0.195	0.011	tHld		1	R40C9[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path19

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_2_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_2_s0/CLK
0.195	0.011	tHld		1	R40C9[0][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/bin_rd_ptr_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path20

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/full_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C8[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/full_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C8[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/full_s0/CLK
0.195	0.011	tHld		1	R39C8[0][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/full_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path21

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C8[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C8[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_0_s0/CLK
0.195	0.011	tHld		1	R40C8[2][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path22

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_1_s0/CLK
0.195	0.011	tHld		1	R40C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path23

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_2_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R39C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R39C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_2_s0/CLK
0.195	0.011	tHld		1	R39C8[1][A]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync2_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path24

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_0_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C8[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C8[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_0_s0/CLK
0.195	0.011	tHld		1	R40C8[2][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Path25

Path Summary:

Slack	1.036
Data Arrival Time	1.231
Data Required Time	0.195
From	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0
To	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_1_s0
Launch Clk	MCU_CLK:[R]
Latch Clk	MCU_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK
0.386	0.202	tC2Q	RR	1200	R17C32[1][A]	u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/Q
1.231	0.845	tNET	RR	1	R40C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					MCU_CLK
0.000	0.000	tCL	RR	3034	PLL_L[0]	pll_inst/rpll_inst/CLKOUT
0.184	0.184	tNET	RR	1	R40C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_1_s0/CLK
0.195	0.011	tHld		1	R40C8[1][B]	u1_AHB_to_AXI_Bridge_Top/ahb2axi_inst/u_rdata_fifo/gray_rd_ptr_sync1_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.845, 80.698%; tC2Q: 0.202, 19.302%
Required Clock Path Delay	cell: 0.000, 0.000%; route: 0.184, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_deUstb/in_reg1_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_deUstb/in_reg1_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_deUstb/in_reg1_s0/CLK

MPW2

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_deUstb/cnt_18_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_deUstb/cnt_18_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_deUstb/cnt_18_s0/CLK

MPW3

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_deUstb/cnt_14_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_deUstb/cnt_14_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_deUstb/cnt_14_s0/CLK

MPW4

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_deUstb/cnt_6_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_deUstb/cnt_6_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_deUstb/cnt_6_s0/CLK

MPW5

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/uhalf_instr_11_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/uhalf_instr_11_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_fetch/uhalf_instr_11_s0/CLK

MPW6

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/held_instr0_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/held_instr0_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/held_instr0_5_s0/CLK

MPW7

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/use_primask_ex_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/use_primask_ex_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/use_primask_ex_s0/CLK

MPW8

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/dreq_rd_ex_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/dreq_rd_ex_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_ctrl/dreq_rd_ex_s0/CLK

MPW9

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/pc_5_s0/CLK

MPW10

MPW Summary:

Slack:	5.173
Actual Width:	6.173
Required Width:	1.000
Type:	Low Pulse Width
Clock:	MCU_CLK
Objects:	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdata_31_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
6.250	0.000			active clock edge time
6.250	0.000			MCU_CLK
6.250	0.000	tCL	FF	pll_inst/rpll_inst/CLKOUT
6.511	0.261	tNET	FF	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdata_31_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
12.500	0.000			active clock edge time
12.500	0.000			MCU_CLK
12.500	0.000	tCL	RR	pll_inst/rpll_inst/CLKOUT
12.684	0.184	tNET	RR	u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_ahb/biu_rdata_31_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
3034	MCU_CLK	0.315	0.261
1291	n74_6	8.464	1.628
1200	AHB1HRESET_d	8.464	1.554
671	control0[0]	22.741	0.912
512	axi_araddr[2]	7.961	1.918
276	capture_mem_wr	9.912	2.874
256	axi_araddr[3]	7.709	2.327
236	n20_3	46.520	1.611
216	data_out_shift_reg_213_7	45.120	1.777
214	n1584_5	43.091	2.422

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R39C28	94.44%
R12C33	91.67%
R25C39	90.28%
R47C10	88.89%
R48C43	88.89%
R40C21	88.89%
R40C31	88.89%
R36C32	88.89%
R38C25	88.89%
R38C29	88.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_CLOCK	Actived	create_clock -name HCLK -period 20 -waveform {0 10} [get_ports {HCLK}]
TC_GENERATED_CLOCK	Actived	create_generated_clock -name MCU_CLK -source [get_ports {HCLK}] -master_clock HCLK -divide_by 5 -multiply_by 8 [get_nets {MCU_CLK}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {tck_pad_i}] -group [get_clocks {HCLK}] -group [get_clocks {MCU_CLK}]