Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\ahb_to_axi_bridge\ahb_to_axi_bridge.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\axi4_lite_slave.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\axi4_lite_slave_top.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\deUstb.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_empu_m1\gowin_empu_m1.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\gowin_rpll\gowin_rpll.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\src\top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v D:\GOWIN SW\v198_07_test\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v D:\IP release\ahb2axi\Gowin_AHB2AXI_bridge_refDesign\project\FPGA\gw_ahb2axi_ref_design_gao\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Wed Jul 06 17:41:03 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | top |
| Synthesis Process | Running parser: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 250.551MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 254.199MB Optimizing Phase 1: CPU time = 0h 0m 0.249s, Elapsed time = 0h 0m 0.25s, Peak memory usage = 254.199MB Optimizing Phase 2: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.543s, Peak memory usage = 254.199MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.124s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 254.199MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 254.199MB Inferring Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 254.199MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 254.199MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.469s, Peak memory usage = 254.199MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.116s, Peak memory usage = 254.199MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 254.199MB Tech-Mapping Phase 3: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 271.000MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.374s, Elapsed time = 0h 0m 0.377s, Peak memory usage = 271.000MB Generate output files: CPU time = 0h 0m 0.483s, Elapsed time = 0h 0m 0.497s, Peak memory usage = 271.000MB |
| Total Time and Memory Usage | CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s, Peak memory usage = 271.000MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 9 |
| I/O Buf | 126 |
| IBUF | 42 |
| OBUF | 84 |
| Register | 3259 |
| DFF | 74 |
| DFFSE | 2 |
| DFFR | 27 |
| DFFRE | 1068 |
| DFFP | 25 |
| DFFPE | 104 |
| DFFC | 388 |
| DFFCE | 1565 |
| DFFNP | 2 |
| DFFNC | 4 |
| LUT | 4601 |
| LUT2 | 345 |
| LUT3 | 1629 |
| LUT4 | 2627 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 76 |
| ALU | 76 |
| SSRAM | 76 |
| RAM16S4 | 42 |
| RAM16SDP4 | 34 |
| INV | 14 |
| INV | 14 |
| DSP | 1 |
| MULT36X36 | 1 |
| BSRAM | 46 |
| SP | 40 |
| SDPX9B | 6 |
| CLOCK | 1 |
| rPLL | 1 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 5155(4623 LUTs, 76 ALUs, 76 SSRAMs) / 20736 | 25% |
| Register | 3259 / 16173 | 20% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 3259 / 16173 | 20% |
| BSRAM | 46 / 46 | 100% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| HCLK | Base | 20.000 | 50.0 | 0.000 | 10.000 | HCLK_ibuf/I | ||
| u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | Base | 10.000 | 100.0 | 0.000 | 5.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | ||
| pll_inst/rpll_inst/CLKOUT.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | HCLK_ibuf/I | HCLK | pll_inst/rpll_inst/CLKOUT |
| pll_inst/rpll_inst/CLKOUTP.default_gen_clk | Generated | 12.500 | 80.0 | 0.000 | 6.250 | HCLK_ibuf/I | HCLK | pll_inst/rpll_inst/CLKOUTP |
| pll_inst/rpll_inst/CLKOUTD.default_gen_clk | Generated | 25.000 | 40.0 | 0.000 | 12.500 | HCLK_ibuf/I | HCLK | pll_inst/rpll_inst/CLKOUTD |
| pll_inst/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 37.500 | 26.7 | 0.000 | 18.750 | HCLK_ibuf/I | HCLK | pll_inst/rpll_inst/CLKOUTD3 |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | 100.0(MHz) | 104.6(MHz) | 14 | TOP |
| 2 | pll_inst/rpll_inst/CLKOUT.default_gen_clk | 80.0(MHz) | 355.0(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | -0.102 |
| Data Arrival Time | 40.895 |
| Data Required Time | 40.792 |
| From | u_deUstb/out_s0 |
| To | u_Gowin_EMPU_M1_Top/sysRstGen_0_s0 |
| Launch Clk | pll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 37.500 | 0.000 | pll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 38.529 | 1.029 | tCL | RR | 24 | pll_inst/rpll_inst/CLKOUT |
| 38.709 | 0.180 | tNET | RR | 1 | u_deUstb/out_s0/CLK |
| 38.941 | 0.232 | tC2Q | RF | 1 | u_deUstb/out_s0/Q |
| 39.178 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/I |
| 39.866 | 0.688 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/O |
| 40.103 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/n13_s1/I1 |
| 40.658 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/n13_s1/F |
| 40.895 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 40.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 40.682 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 40.862 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_0_s0/CLK |
| 40.827 | -0.035 | tUnc | u_Gowin_EMPU_M1_Top/sysRstGen_0_s0 | ||
| 40.792 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_0_s0 |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.500 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 1.243, 56.852%; route: 0.711, 32.533%; tC2Q: 0.232, 10.615% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 2
Path Summary:| Slack | -0.060 |
| Data Arrival Time | 40.853 |
| Data Required Time | 40.792 |
| From | u_deUstb/out_s0 |
| To | u_Gowin_EMPU_M1_Top/sysRstGen_3_s0 |
| Launch Clk | pll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 37.500 | 0.000 | pll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 38.529 | 1.029 | tCL | RR | 24 | pll_inst/rpll_inst/CLKOUT |
| 38.709 | 0.180 | tNET | RR | 1 | u_deUstb/out_s0/CLK |
| 38.941 | 0.232 | tC2Q | RF | 1 | u_deUstb/out_s0/Q |
| 39.178 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/I |
| 39.866 | 0.688 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/O |
| 40.103 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/n8_s1/I1 |
| 40.673 | 0.570 | tINS | FR | 3 | u_Gowin_EMPU_M1_Top/n8_s1/F |
| 40.853 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 40.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 40.682 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 40.862 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_3_s0/CLK |
| 40.827 | -0.035 | tUnc | u_Gowin_EMPU_M1_Top/sysRstGen_3_s0 | ||
| 40.792 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_3_s0 |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.500 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 1.257, 58.666%; route: 0.654, 30.511%; tC2Q: 0.232, 10.823% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 3
Path Summary:| Slack | -0.060 |
| Data Arrival Time | 40.853 |
| Data Required Time | 40.792 |
| From | u_deUstb/out_s0 |
| To | u_Gowin_EMPU_M1_Top/sysRstGen_1_s0 |
| Launch Clk | pll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 37.500 | 0.000 | pll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 38.529 | 1.029 | tCL | RR | 24 | pll_inst/rpll_inst/CLKOUT |
| 38.709 | 0.180 | tNET | RR | 1 | u_deUstb/out_s0/CLK |
| 38.941 | 0.232 | tC2Q | RF | 1 | u_deUstb/out_s0/Q |
| 39.178 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/I |
| 39.866 | 0.688 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/O |
| 40.103 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/n8_s1/I1 |
| 40.673 | 0.570 | tINS | FR | 3 | u_Gowin_EMPU_M1_Top/n8_s1/F |
| 40.853 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_1_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 40.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 40.682 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 40.862 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_1_s0/CLK |
| 40.827 | -0.035 | tUnc | u_Gowin_EMPU_M1_Top/sysRstGen_1_s0 | ||
| 40.792 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_1_s0 |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.500 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 1.257, 58.666%; route: 0.654, 30.511%; tC2Q: 0.232, 10.823% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 4
Path Summary:| Slack | -0.060 |
| Data Arrival Time | 40.853 |
| Data Required Time | 40.792 |
| From | u_deUstb/out_s0 |
| To | u_Gowin_EMPU_M1_Top/sysRstGen_2_s0 |
| Launch Clk | pll_inst/rpll_inst/CLKOUT.default_gen_clk[R] |
| Latch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 37.500 | 0.000 | pll_inst/rpll_inst/CLKOUT.default_gen_clk | |||
| 38.529 | 1.029 | tCL | RR | 24 | pll_inst/rpll_inst/CLKOUT |
| 38.709 | 0.180 | tNET | RR | 1 | u_deUstb/out_s0/CLK |
| 38.941 | 0.232 | tC2Q | RF | 1 | u_deUstb/out_s0/Q |
| 39.178 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/I |
| 39.866 | 0.688 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/hwRstn_ibuf/O |
| 40.103 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/n8_s1/I1 |
| 40.673 | 0.570 | tINS | FR | 3 | u_Gowin_EMPU_M1_Top/n8_s1/F |
| 40.853 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_2_s0/RESET |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 40.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 40.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 40.682 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 40.862 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_2_s0/CLK |
| 40.827 | -0.035 | tUnc | u_Gowin_EMPU_M1_Top/sysRstGen_2_s0 | ||
| 40.792 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_Top/sysRstGen_2_s0 |
| Clock Skew: | -0.347 |
| Setup Relationship: | 2.500 |
| Logic Level: | 3 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
| Arrival Data Path Delay: | cell: 1.257, 58.666%; route: 0.654, 30.511%; tC2Q: 0.232, 10.823% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.180, 100.000% |
Path 5
Path Summary:| Slack | 0.437 |
| Data Arrival Time | 10.391 |
| Data Required Time | 10.828 |
| From | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0 |
| To | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Launch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| Latch Clk | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 0.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 8 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/rptr_b_ex_0_s0/Q |
| 1.332 | 0.237 | tNET | FF | 4 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/RAD[0] |
| 1.849 | 0.517 | tINS | FF | 7 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_r_bank/reg_file_b_reg_file_b_0_0_s0/DO[2] |
| 2.086 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/I0 |
| 2.602 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s2/F |
| 2.839 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/I1 |
| 3.395 | 0.555 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/au_b_int_2_s1/F |
| 3.632 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/I1 |
| 4.187 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_in_b_2_s0/F |
| 4.424 | 0.237 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/I1 |
| 4.994 | 0.570 | tINS | FR | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_2_s/COUT |
| 4.994 | 0.000 | tNET | RR | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/CIN |
| 5.029 | 0.035 | tINS | RF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_3_s/COUT |
| 5.029 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/CIN |
| 5.064 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_4_s/COUT |
| 5.064 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/CIN |
| 5.099 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_5_s/COUT |
| 5.099 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/CIN |
| 5.134 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_6_s/COUT |
| 5.134 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/CIN |
| 5.170 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_7_s/COUT |
| 5.170 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/CIN |
| 5.205 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_8_s/COUT |
| 5.205 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/CIN |
| 5.240 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_9_s/COUT |
| 5.240 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/CIN |
| 5.275 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_10_s/COUT |
| 5.275 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/CIN |
| 5.310 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_11_s/COUT |
| 5.310 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/CIN |
| 5.346 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_12_s/COUT |
| 5.346 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/CIN |
| 5.381 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_13_s/COUT |
| 5.381 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/CIN |
| 5.416 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_14_s/COUT |
| 5.416 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/CIN |
| 5.451 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_15_s/COUT |
| 5.451 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/CIN |
| 5.486 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_16_s/COUT |
| 5.486 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/CIN |
| 5.522 | 0.035 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_17_s/COUT |
| 5.522 | 0.000 | tNET | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/CIN |
| 5.992 | 0.470 | tINS | FF | 4 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/u_adder/au_out_18_s/SUM |
| 6.229 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/I1 |
| 6.784 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s6/F |
| 7.021 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/I1 |
| 7.576 | 0.555 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/au_zero_Z_s1/F |
| 7.813 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/I3 |
| 8.184 | 0.371 | tINS | FF | 2 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/nxt_itcm_sel_s1/F |
| 8.421 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/I0 |
| 8.938 | 0.517 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s10/F |
| 9.175 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/I3 |
| 9.546 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s3/F |
| 9.783 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/I3 |
| 10.154 | 0.371 | tINS | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_alu_dec/biu_commit_Z_s/F |
| 10.391 | 0.237 | tNET | FF | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I | |||
| 10.000 | 0.000 | tCL | RR | 1 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 1362 | u_Gowin_EMPU_M1_Top/HCLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | u_Gowin_EMPU_M1_Top/M1_inst/u_CortexM1Integration/u_cortexm1/u_core/u_dp/u_mem_ctl/biu_commit_reg_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 14 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 6.452, 67.716%; route: 2.844, 29.849%; tC2Q: 0.232, 2.435% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |