Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\impl\gwsynthesis\XCORR.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\src\XCORR.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\src\XCORR.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Jun 10 15:32:44 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	3068
Numbers of Endpoints Analyzed	4305
Numbers of Falling Endpoints	10
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk	Base	10.000	100.000	0.000	5.000			clk
2	tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	100.000(MHz)	107.035(MHz)	6	TOP
2	tck_pad_i	20.000(MHz)	80.478(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk	Setup	0.000	0
clk	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.657	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_36_s0/D	clk:[R]	clk:[R]	10.000	0.024	9.255
2	0.837	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_38_s0/D	clk:[R]	clk:[R]	10.000	0.028	9.071
3	0.885	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_39_s0/D	clk:[R]	clk:[R]	10.000	0.024	9.027
4	0.987	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_43_s0/D	clk:[R]	clk:[R]	10.000	0.026	8.923
5	1.033	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_34_s0/D	clk:[R]	clk:[R]	10.000	0.024	8.879
6	1.116	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_35_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.788
7	1.176	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_37_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.732
8	1.230	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_31_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.673
9	1.236	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_41_s0/D	clk:[R]	clk:[R]	10.000	0.026	8.674
10	1.248	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_32_s0/D	clk:[R]	clk:[R]	10.000	0.024	8.664
11	1.265	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_42_s0/D	clk:[R]	clk:[R]	10.000	0.029	8.642
12	1.305	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_33_s0/D	clk:[R]	clk:[R]	10.000	0.024	8.608
13	1.308	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_40_s0/D	clk:[R]	clk:[R]	10.000	0.020	8.608
14	1.334	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_24_s0/D	clk:[R]	clk:[R]	10.000	0.047	8.555
15	1.381	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_23_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.528
16	1.398	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_29_s0/D	clk:[R]	clk:[R]	10.000	0.024	8.515
17	1.460	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_26_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.443
18	1.504	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_25_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.399
19	1.517	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_27_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.386
20	1.519	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_21_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.389
21	1.536	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_30_s0/D	clk:[R]	clk:[R]	10.000	0.033	8.367
22	1.654	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_22_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.254
23	1.751	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_19_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.157
24	1.784	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_20_s0/D	clk:[R]	clk:[R]	10.000	0.028	8.125
25	1.784	uut/u_xcorr/cnt_5_s1/Q	uut/u_xcorr/result_16_s0/D	clk:[R]	clk:[R]	10.000	0.037	8.114

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.186	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/DI[1]	clk:[R]	clk:[R]	0.000	-0.002	0.225
2	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]	clk:[R]	clk:[R]	0.000	-0.005	0.235
3	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[0]	clk:[R]	clk:[R]	0.000	-0.005	0.235
4	0.193	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]	clk:[R]	clk:[R]	0.000	-0.005	0.235
5	0.215	ad_0_s1/Q	b_d_0_s2/AD[4]	clk:[R]	clk:[R]	0.000	0.005	0.245
6	0.216	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[2]	clk:[R]	clk:[R]	0.000	-0.005	0.258
7	0.216	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	clk:[R]	clk:[R]	0.000	-0.005	0.258
8	0.221	ad_1_s0/Q	b_d_0_s2/AD[5]	clk:[R]	clk:[R]	0.000	0.005	0.251
9	0.237	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_63_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[3]	clk:[R]	clk:[R]	0.000	-0.010	0.284
10	0.251	uut/u_xcorr/cnt_6_s1/Q	uut/u_xcorr/memy_memy_0_0_s/ADA[10]	clk:[R]	clk:[R]	0.000	0.020	0.268
11	0.257	ad_2_s0/Q	b_d_0_s2/AD[6]	clk:[R]	clk:[R]	0.000	0.005	0.287
12	0.258	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/ADA[5]	clk:[R]	clk:[R]	0.000	0.004	0.291
13	0.259	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[12]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.002	0.292
14	0.259	ad_6_s0/Q	b_d_0_s3/AD[10]	clk:[R]	clk:[R]	0.000	-0.003	0.297
15	0.262	ad_4_s0/Q	b_d_0_s2/AD[8]	clk:[R]	clk:[R]	0.000	0.001	0.296
16	0.264	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[6]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.005	0.294
17	0.270	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[10]	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.005	0.300
18	0.275	gw_gao_inst_0/u_la0_top/address_counter_11_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_11_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
19	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_91_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/D	clk:[R]	clk:[R]	0.000	0.000	0.222
20	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
21	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
22	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
23	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/D	clk:[R]	clk:[R]	0.000	0.000	0.300
24	0.275	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300
25	0.275	gw_gao_inst_0/u_la0_top/word_count_6_s0/Q	gw_gao_inst_0/u_la0_top/word_count_6_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.300

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	2.860	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.014	1.778
2	2.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR	clk:[F]	clk:[R]	5.000	-0.001	1.789
3	2.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.001	1.789
4	2.864	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.002	1.786
5	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.001	1.784
6	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	1.778
7	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.001	1.784
8	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	1.778
9	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	1.778
10	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR	clk:[F]	clk:[R]	5.000	0.005	1.778
11	2.870	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk:[F]	clk:[R]	5.000	0.011	1.772
12	2.872	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.025	1.805
13	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.007	1.786
14	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.007	1.786
15	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.011	1.789
16	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.011	1.789
17	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.011	1.789
18	2.874	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.009	1.788
19	2.877	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.037	1.813
20	2.877	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.037	1.813
21	2.877	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.037	1.813
22	2.877	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR	clk:[F]	clk:[R]	5.000	-0.037	1.813
23	2.879	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk:[F]	clk:[R]	5.000	-0.004	1.778
24	2.879	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.010	1.784
25	2.879	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk:[F]	clk:[R]	5.000	-0.004	1.778

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
2	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
3	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
4	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
5	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
6	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
7	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
8	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
9	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
10	5.683	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.001	0.631
11	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.016	0.650
12	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
13	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
14	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
15	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
16	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
17	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR	clk:[F]	clk:[R]	-5.000	-0.021	0.655
18	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
19	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
20	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
21	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
22	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
23	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
24	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631
25	5.687	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR	clk:[F]	clk:[R]	-5.000	0.003	0.631

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.751	3.751	1.000	Low Pulse Width	clk	b_d_0_s3
2	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
3	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
4	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
5	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s
6	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s
7	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
8	2.751	3.751	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s
9	2.751	3.751	1.000	Low Pulse Width	clk	uut/u_xcorr/memx_memx_0_0_s
10	2.757	3.757	1.000	Low Pulse Width	clk	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_32_s

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.657
Data Arrival Time	11.889
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_36_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.620	3.841	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[36]
11.373	0.752	tNET	RR	1	R16C56[0][B]	uut/u_xcorr/n882_s2/I0
11.889	0.516	tINS	RR	1	R16C56[0][B]	uut/u_xcorr/n882_s2/F
11.889	0.000	tNET	RR	1	R16C56[0][B]	uut/u_xcorr/result_36_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C56[0][B]	uut/u_xcorr/result_36_s0/CLK
12.546	-0.064	tSu		1	R16C56[0][B]	uut/u_xcorr/result_36_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.898, 63.723%; route: 2.975, 32.144%; tC2Q: 0.382, 4.133%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path2

Path Summary:

Slack	0.837
Data Arrival Time	11.705
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_38_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.604	3.825	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[38]
11.207	0.604	tNET	FF	1	R13C53[3][A]	uut/u_xcorr/n880_s2/I0
11.705	0.498	tINS	FR	1	R13C53[3][A]	uut/u_xcorr/n880_s2/F
11.705	0.000	tNET	RR	1	R13C53[3][A]	uut/u_xcorr/result_38_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[3][A]	uut/u_xcorr/result_38_s0/CLK
12.542	-0.064	tSu		1	R13C53[3][A]	uut/u_xcorr/result_38_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.862, 64.626%; route: 2.826, 31.157%; tC2Q: 0.382, 4.217%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path3

Path Summary:

Slack	0.885
Data Arrival Time	11.661
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_39_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.610	3.831	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[39]
11.145	0.535	tNET	FF	1	R16C56[1][A]	uut/u_xcorr/n879_s2/I0
11.661	0.516	tINS	FR	1	R16C56[1][A]	uut/u_xcorr/n879_s2/F
11.661	0.000	tNET	RR	1	R16C56[1][A]	uut/u_xcorr/result_39_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C56[1][A]	uut/u_xcorr/result_39_s0/CLK
12.546	-0.064	tSu		1	R16C56[1][A]	uut/u_xcorr/result_39_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.887, 65.216%; route: 2.758, 30.547%; tC2Q: 0.382, 4.237%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path4

Path Summary:

Slack	0.987
Data Arrival Time	11.557
Data Required Time	12.544
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_43_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.658	3.880	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[43]
11.031	0.373	tNET	FF	1	R15C54[0][B]	uut/u_xcorr/n875_s2/I0
11.557	0.526	tINS	FR	1	R15C54[0][B]	uut/u_xcorr/n875_s2/F
11.557	0.000	tNET	RR	1	R15C54[0][B]	uut/u_xcorr/result_43_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.608	1.926	tNET	RR	1	R15C54[0][B]	uut/u_xcorr/result_43_s0/CLK
12.544	-0.064	tSu		1	R15C54[0][B]	uut/u_xcorr/result_43_s0

Path Statistics:

Clock Skew	-0.026
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.946, 66.632%; route: 2.595, 29.081%; tC2Q: 0.382, 4.287%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path5

Path Summary:

Slack	1.033
Data Arrival Time	11.513
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_34_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.452	3.673	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[34]
10.987	0.535	tNET	FF	1	R16C56[2][B]	uut/u_xcorr/n884_s2/I0
11.513	0.526	tINS	FR	1	R16C56[2][B]	uut/u_xcorr/n884_s2/F
11.513	0.000	tNET	RR	1	R16C56[2][B]	uut/u_xcorr/result_34_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C56[2][B]	uut/u_xcorr/result_34_s0/CLK
12.546	-0.064	tSu		1	R16C56[2][B]	uut/u_xcorr/result_34_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.739, 64.636%; route: 2.758, 31.056%; tC2Q: 0.382, 4.308%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path6

Path Summary:

Slack	1.116
Data Arrival Time	11.421
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_35_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.528	3.749	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[35]
10.900	0.373	tNET	FF	1	R16C55[3][A]	uut/u_xcorr/n883_s2/I0
11.421	0.521	tINS	FR	1	R16C55[3][A]	uut/u_xcorr/n883_s2/F
11.421	0.000	tNET	RR	1	R16C55[3][A]	uut/u_xcorr/result_35_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[3][A]	uut/u_xcorr/result_35_s0/CLK
12.537	-0.064	tSu		1	R16C55[3][A]	uut/u_xcorr/result_35_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.810, 66.117%; route: 2.595, 29.530%; tC2Q: 0.382, 4.353%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path7

Path Summary:

Slack	1.176
Data Arrival Time	11.366
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_37_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.547	3.768	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[37]
11.103	0.556	tNET	FF	1	R13C53[2][B]	uut/u_xcorr/n881_s2/I0
11.366	0.262	tINS	FR	1	R13C53[2][B]	uut/u_xcorr/n881_s2/F
11.366	0.000	tNET	RR	1	R13C53[2][B]	uut/u_xcorr/result_37_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[2][B]	uut/u_xcorr/result_37_s0/CLK
12.542	-0.064	tSu		1	R13C53[2][B]	uut/u_xcorr/result_37_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.571, 63.797%; route: 2.779, 31.823%; tC2Q: 0.382, 4.380%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path8

Path Summary:

Slack	1.230
Data Arrival Time	11.307
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_31_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.408	3.630	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[31]
10.781	0.373	tNET	FF	1	R16C55[2][A]	uut/u_xcorr/n887_s2/I0
11.307	0.526	tINS	FR	1	R16C55[2][A]	uut/u_xcorr/n887_s2/F
11.307	0.000	tNET	RR	1	R16C55[2][A]	uut/u_xcorr/result_31_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[2][A]	uut/u_xcorr/result_31_s0/CLK
12.537	-0.064	tSu		1	R16C55[2][A]	uut/u_xcorr/result_31_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.696, 65.671%; route: 2.595, 29.919%; tC2Q: 0.382, 4.410%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path9

Path Summary:

Slack	1.236
Data Arrival Time	11.308
Data Required Time	12.544
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_41_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.673	3.894	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[41]
11.045	0.373	tNET	FF	1	R15C54[1][A]	uut/u_xcorr/n877_s2/I0
11.308	0.262	tINS	FR	1	R15C54[1][A]	uut/u_xcorr/n877_s2/F
11.308	0.000	tNET	RR	1	R15C54[1][A]	uut/u_xcorr/result_41_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.608	1.926	tNET	RR	1	R15C54[1][A]	uut/u_xcorr/result_41_s0/CLK
12.544	-0.064	tSu		1	R15C54[1][A]	uut/u_xcorr/result_41_s0

Path Statistics:

Clock Skew	-0.026
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.697, 65.674%; route: 2.595, 29.916%; tC2Q: 0.382, 4.410%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path10

Path Summary:

Slack	1.248
Data Arrival Time	11.298
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_32_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.409	3.630	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[32]
10.782	0.373	tNET	FF	1	R16C54[2][A]	uut/u_xcorr/n886_s2/I0
11.298	0.516	tINS	FR	1	R16C54[2][A]	uut/u_xcorr/n886_s2/F
11.298	0.000	tNET	RR	1	R16C54[2][A]	uut/u_xcorr/result_32_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C54[2][A]	uut/u_xcorr/result_32_s0/CLK
12.546	-0.064	tSu		1	R16C54[2][A]	uut/u_xcorr/result_32_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.687, 65.634%; route: 2.595, 29.951%; tC2Q: 0.382, 4.415%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path11

Path Summary:

Slack	1.265
Data Arrival Time	11.276
Data Required Time	12.541
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_42_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.672	3.893	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[42]
10.814	0.142	tNET	FF	1	R18C55[1][A]	uut/u_xcorr/n876_s2/I0
11.276	0.461	tINS	FR	1	R18C55[1][A]	uut/u_xcorr/n876_s2/F
11.276	0.000	tNET	RR	1	R18C55[1][A]	uut/u_xcorr/result_42_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.604	1.922	tNET	RR	1	R18C55[1][A]	uut/u_xcorr/result_42_s0/CLK
12.541	-0.064	tSu		1	R18C55[1][A]	uut/u_xcorr/result_42_s0

Path Statistics:

Clock Skew	-0.029
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.894, 68.207%; route: 2.365, 27.367%; tC2Q: 0.382, 4.426%
Required Clock Path Delay	cell: 0.683, 26.206%; route: 1.922, 73.794%

Path12

Path Summary:

Slack	1.305
Data Arrival Time	11.242
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_33_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.444	3.665	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[33]
10.979	0.535	tNET	FF	1	R16C56[2][A]	uut/u_xcorr/n885_s2/I0
11.242	0.262	tINS	FR	1	R16C56[2][A]	uut/u_xcorr/n885_s2/F
11.242	0.000	tNET	RR	1	R16C56[2][A]	uut/u_xcorr/result_33_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C56[2][A]	uut/u_xcorr/result_33_s0/CLK
12.546	-0.064	tSu		1	R16C56[2][A]	uut/u_xcorr/result_33_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.468, 63.522%; route: 2.758, 32.035%; tC2Q: 0.382, 4.444%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path13

Path Summary:

Slack	1.308
Data Arrival Time	11.242
Data Required Time	12.550
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_40_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.638	3.860	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[40]
10.781	0.142	tNET	FF	1	R18C54[0][A]	uut/u_xcorr/n878_s2/I0
11.242	0.461	tINS	FR	1	R18C54[0][A]	uut/u_xcorr/n878_s2/F
11.242	0.000	tNET	RR	1	R18C54[0][A]	uut/u_xcorr/result_40_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.614	1.931	tNET	RR	1	R18C54[0][A]	uut/u_xcorr/result_40_s0/CLK
12.550	-0.064	tSu		1	R18C54[0][A]	uut/u_xcorr/result_40_s0

Path Statistics:

Clock Skew	-0.020
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.861, 68.084%; route: 2.365, 27.473%; tC2Q: 0.382, 4.443%
Required Clock Path Delay	cell: 0.683, 26.112%; route: 1.931, 73.888%

Path14

Path Summary:

Slack	1.334
Data Arrival Time	11.189
Data Required Time	12.523
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_24_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.261	3.483	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[24]
10.728	0.466	tNET	FF	1	R13C55[1][A]	uut/u_xcorr/n894_s2/I0
11.189	0.461	tINS	FR	1	R13C55[1][A]	uut/u_xcorr/n894_s2/F
11.189	0.000	tNET	RR	1	R13C55[1][A]	uut/u_xcorr/result_24_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C55[1][A]	uut/u_xcorr/result_24_s0/CLK
12.523	-0.064	tSu		1	R13C55[1][A]	uut/u_xcorr/result_24_s0

Path Statistics:

Clock Skew	-0.047
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.484, 64.100%; route: 2.689, 31.429%; tC2Q: 0.382, 4.471%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path15

Path Summary:

Slack	1.381
Data Arrival Time	11.161
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_23_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.031	3.253	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[23]
10.635	0.604	tNET	FF	1	R13C53[2][A]	uut/u_xcorr/n895_s2/I0
11.161	0.526	tINS	FR	1	R13C53[2][A]	uut/u_xcorr/n895_s2/F
11.161	0.000	tNET	RR	1	R13C53[2][A]	uut/u_xcorr/result_23_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[2][A]	uut/u_xcorr/result_23_s0/CLK
12.542	-0.064	tSu		1	R13C53[2][A]	uut/u_xcorr/result_23_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.319, 62.372%; route: 2.826, 33.142%; tC2Q: 0.382, 4.485%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path16

Path Summary:

Slack	1.398
Data Arrival Time	11.148
Data Required Time	12.546
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_29_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.315	3.536	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[29]
10.687	0.373	tNET	FF	1	R16C54[1][B]	uut/u_xcorr/n889_s2/I0
11.148	0.461	tINS	FR	1	R16C54[1][B]	uut/u_xcorr/n889_s2/F
11.148	0.000	tNET	RR	1	R16C54[1][B]	uut/u_xcorr/result_29_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C54[1][B]	uut/u_xcorr/result_29_s0/CLK
12.546	-0.064	tSu		1	R16C54[1][B]	uut/u_xcorr/result_29_s0

Path Statistics:

Clock Skew	-0.024
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.537, 65.031%; route: 2.595, 30.477%; tC2Q: 0.382, 4.492%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path17

Path Summary:

Slack	1.460
Data Arrival Time	11.077
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_26_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.178	3.399	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[26]
10.550	0.373	tNET	FF	1	R16C55[1][A]	uut/u_xcorr/n892_s2/I0
11.077	0.526	tINS	FR	1	R16C55[1][A]	uut/u_xcorr/n892_s2/F
11.077	0.000	tNET	RR	1	R16C55[1][A]	uut/u_xcorr/result_26_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[1][A]	uut/u_xcorr/result_26_s0/CLK
12.537	-0.064	tSu		1	R16C55[1][A]	uut/u_xcorr/result_26_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.465, 64.733%; route: 2.595, 30.736%; tC2Q: 0.382, 4.530%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path18

Path Summary:

Slack	1.504
Data Arrival Time	11.032
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_25_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.144	3.365	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[25]
10.516	0.373	tNET	FF	1	R16C55[0][A]	uut/u_xcorr/n893_s2/I0
11.032	0.516	tINS	FR	1	R16C55[0][A]	uut/u_xcorr/n893_s2/F
11.032	0.000	tNET	RR	1	R16C55[0][A]	uut/u_xcorr/result_25_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[0][A]	uut/u_xcorr/result_25_s0/CLK
12.537	-0.064	tSu		1	R16C55[0][A]	uut/u_xcorr/result_25_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.421, 64.548%; route: 2.595, 30.898%; tC2Q: 0.382, 4.554%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path19

Path Summary:

Slack	1.517
Data Arrival Time	11.020
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_27_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.186	3.407	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[27]
10.558	0.373	tNET	FF	1	R16C55[0][B]	uut/u_xcorr/n891_s2/I0
11.020	0.461	tINS	FR	1	R16C55[0][B]	uut/u_xcorr/n891_s2/F
11.020	0.000	tNET	RR	1	R16C55[0][B]	uut/u_xcorr/result_27_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[0][B]	uut/u_xcorr/result_27_s0/CLK
12.537	-0.064	tSu		1	R16C55[0][B]	uut/u_xcorr/result_27_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.408, 64.494%; route: 2.595, 30.945%; tC2Q: 0.382, 4.561%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path20

Path Summary:

Slack	1.519
Data Arrival Time	11.023
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_21_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
9.942	3.163	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[21]
10.562	0.620	tNET	RR	1	R13C53[1][B]	uut/u_xcorr/n897_s2/I0
11.023	0.461	tINS	RR	1	R13C53[1][B]	uut/u_xcorr/n897_s2/F
11.023	0.000	tNET	RR	1	R13C53[1][B]	uut/u_xcorr/result_21_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[1][B]	uut/u_xcorr/result_21_s0/CLK
12.542	-0.064	tSu		1	R13C53[1][B]	uut/u_xcorr/result_21_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.164, 61.558%; route: 2.843, 33.883%; tC2Q: 0.382, 4.559%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path21

Path Summary:

Slack	1.536
Data Arrival Time	11.001
Data Required Time	12.537
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_30_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
10.366	3.587	tINS	RF	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[30]
10.739	0.373	tNET	FF	1	R16C55[1][B]	uut/u_xcorr/n888_s2/I0
11.001	0.262	tINS	FR	1	R16C55[1][B]	uut/u_xcorr/n888_s2/F
11.001	0.000	tNET	RR	1	R16C55[1][B]	uut/u_xcorr/result_30_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.601	1.918	tNET	RR	1	R16C55[1][B]	uut/u_xcorr/result_30_s0/CLK
12.537	-0.064	tSu		1	R16C55[1][B]	uut/u_xcorr/result_30_s0

Path Statistics:

Clock Skew	-0.033
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.390, 64.416%; route: 2.595, 31.013%; tC2Q: 0.382, 4.571%
Required Clock Path Delay	cell: 0.683, 26.244%; route: 1.918, 73.756%

Path22

Path Summary:

Slack	1.654
Data Arrival Time	10.888
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_22_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][A]	uut/u_xcorr/r_5_s3/F
6.779	0.347	tNET	RR	86	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[5]
9.913	3.134	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[22]
10.362	0.449	tNET	RR	1	R13C53[1][A]	uut/u_xcorr/n896_s2/I0
10.888	0.526	tINS	RR	1	R13C53[1][A]	uut/u_xcorr/n896_s2/F
10.888	0.000	tNET	RR	1	R13C53[1][A]	uut/u_xcorr/result_22_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[1][A]	uut/u_xcorr/result_22_s0/CLK
12.542	-0.064	tSu		1	R13C53[1][A]	uut/u_xcorr/result_22_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.200, 63.004%; route: 2.671, 32.362%; tC2Q: 0.382, 4.634%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path23

Path Summary:

Slack	1.751
Data Arrival Time	10.791
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_19_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/F
6.779	0.347	tNET	RR	92	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[2]
9.799	3.021	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[19]
10.264	0.465	tNET	RR	1	R13C53[0][A]	uut/u_xcorr/n899_s2/I0
10.791	0.526	tINS	RR	1	R13C53[0][A]	uut/u_xcorr/n899_s2/F
10.791	0.000	tNET	RR	1	R13C53[0][A]	uut/u_xcorr/result_19_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[0][A]	uut/u_xcorr/result_19_s0/CLK
12.542	-0.064	tSu		1	R13C53[0][A]	uut/u_xcorr/result_19_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.087, 62.363%; route: 2.688, 32.948%; tC2Q: 0.382, 4.689%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path24

Path Summary:

Slack	1.784
Data Arrival Time	10.758
Data Required Time	12.542
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_20_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/F
6.779	0.347	tNET	RR	92	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[2]
9.848	3.070	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[20]
10.297	0.449	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/n898_s2/I0
10.758	0.461	tINS	RR	1	R13C53[0][B]	uut/u_xcorr/n898_s2/F
10.758	0.000	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/result_20_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C53[0][B]	uut/u_xcorr/result_20_s0/CLK
12.542	-0.064	tSu		1	R13C53[0][B]	uut/u_xcorr/result_20_s0

Path Statistics:

Clock Skew	-0.028
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 5.071, 62.413%; route: 2.671, 32.879%; tC2Q: 0.382, 4.708%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path25

Path Summary:

Slack	1.784
Data Arrival Time	10.748
Data Required Time	12.533
From	uut/u_xcorr/cnt_5_s1
To	uut/u_xcorr/result_16_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
2.634	1.951	tNET	RR	1	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/CLK
3.016	0.382	tC2Q	RR	17	R22C55[1][A]	uut/u_xcorr/cnt_5_s1/Q
4.156	1.140	tNET	RR	1	R15C54[3][B]	uut/u_xcorr/n21_s5/I2
4.654	0.498	tINS	RR	5	R15C54[3][B]	uut/u_xcorr/n21_s5/F
4.661	0.008	tNET	RR	1	R15C54[2][A]	uut/u_xcorr/n212_s3/I0
5.188	0.526	tINS	RR	49	R15C54[2][A]	uut/u_xcorr/n212_s3/F
5.915	0.728	tNET	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/I1
6.431	0.516	tINS	RR	1	R18C52[2][B]	uut/u_xcorr/r_2_s3/F
6.779	0.347	tNET	RR	92	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/C[2]
9.612	2.833	tINS	RR	1	DSP_R19[17]	uut/u_xcorr/m1/n4_s0/DOUT[16]
10.232	0.620	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/n902_s2/I0
10.748	0.516	tINS	RR	1	R13C54[2][A]	uut/u_xcorr/n902_s2/F
10.748	0.000	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/result_16_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C54[2][A]	uut/u_xcorr/result_16_s0/CLK
12.533	-0.064	tSu		1	R13C54[2][A]	uut/u_xcorr/result_16_s0

Path Statistics:

Clock Skew	-0.037
Setup Relationship	10.000
Logic Level	6
Arrival Clock Path Delay	cell: 0.683, 25.914%; route: 1.951, 74.086%
Arrival Data Path Delay	cell: 4.889, 60.256%; route: 2.843, 35.030%; tC2Q: 0.382, 4.714%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.186
Data Arrival Time	1.597
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/CLK
1.513	0.141	tC2Q	RF	1	R15C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q
1.597	0.084	tNET	FF	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[13]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_18_s

Path Statistics:

Clock Skew	0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.084, 37.333%; tC2Q: 0.141, 62.667%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path2

Path Summary:

Slack	0.193
Data Arrival Time	1.600
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.365	0.690	tNET	RR	1	R11C23[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.507	0.141	tC2Q	RF	1	R11C23[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.600	0.094	tNET	FF	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.469%; route: 0.690, 50.531%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path3

Path Summary:

Slack	0.193
Data Arrival Time	1.609
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C41[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_60_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path4

Path Summary:

Slack	0.193
Data Arrival Time	1.609
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C17[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_6_s0/Q
1.609	0.094	tNET	FF	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.094, 40.000%; tC2Q: 0.141, 60.000%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path5

Path Summary:

Slack	0.215
Data Arrival Time	1.624
Data Required Time	1.410
From	ad_0_s1
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[2][A]	ad_0_s1/CLK
1.523	0.144	tC2Q	RR	8	R27C54[2][A]	ad_0_s1/Q
1.624	0.101	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/AD[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R28[16]	b_d_0_s2

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path6

Path Summary:

Slack	0.216
Data Arrival Time	1.632
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C41[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_62_s0/Q
1.632	0.117	tNET	FF	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path7

Path Summary:

Slack	0.216
Data Arrival Time	1.632
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C17[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/CLK
1.515	0.141	tC2Q	RF	1	R11C17[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_7_s0/Q
1.632	0.117	tNET	FF	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[4]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.117, 45.349%; tC2Q: 0.141, 54.651%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path8

Path Summary:

Slack	0.221
Data Arrival Time	1.630
Data Required Time	1.410
From	ad_1_s0
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[1][A]	ad_1_s0/CLK
1.520	0.141	tC2Q	RF	7	R27C54[1][A]	ad_1_s0/Q
1.630	0.110	tNET	FF	1	BSRAM_R28[16]	b_d_0_s2/AD[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R28[16]	b_d_0_s2

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.110, 43.825%; tC2Q: 0.141, 56.175%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path9

Path Summary:

Slack	0.237
Data Arrival Time	1.653
Data Required Time	1.415
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_63_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_63_s0/CLK
1.513	0.144	tC2Q	RR	1	R14C40[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_63_s0/Q
1.653	0.140	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA
1.415	0.037	tHld		1	BSRAM_R10[12]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Path Statistics:

Clock Skew	0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.140, 49.296%; tC2Q: 0.144, 50.704%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path10

Path Summary:

Slack	0.251
Data Arrival Time	1.663
Data Required Time	1.411
From	uut/u_xcorr/cnt_6_s1
To	uut/u_xcorr/memy_memy_0_0_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.395	0.719	tNET	RR	1	R22C54[1][B]	uut/u_xcorr/cnt_6_s1/CLK
1.536	0.141	tC2Q	RF	14	R22C54[1][B]	uut/u_xcorr/cnt_6_s1/Q
1.663	0.127	tNET	FF	1	BSRAM_R28[15]	uut/u_xcorr/memy_memy_0_0_s/ADA[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[15]	uut/u_xcorr/memy_memy_0_0_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[15]	uut/u_xcorr/memy_memy_0_0_s

Path Statistics:

Clock Skew	-0.020
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.432%; route: 0.719, 51.568%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.127, 47.388%; tC2Q: 0.141, 52.612%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path11

Path Summary:

Slack	0.257
Data Arrival Time	1.666
Data Required Time	1.410
From	ad_2_s0
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C54[0][B]	ad_2_s0/CLK
1.523	0.144	tC2Q	RR	6	R27C54[0][B]	ad_2_s0/Q
1.666	0.143	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/AD[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R28[16]	b_d_0_s2

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.143, 49.826%; tC2Q: 0.144, 50.174%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path12

Path Summary:

Slack	0.258
Data Arrival Time	1.666
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.519	0.144	tC2Q	RR	36	R17C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/Q
1.666	0.147	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/ADA[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s/CLKA
1.408	0.037	tHld		1	BSRAM_R10[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_19_s

Path Statistics:

Clock Skew	-0.004
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.147, 50.515%; tC2Q: 0.144, 49.485%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path13

Path Summary:

Slack	0.259
Data Arrival Time	2.711
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.419	1.068	tNET	RR	1	R18C48[3][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.563	0.144	tC2Q	RR	35	R18C48[3][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.711	0.148	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKB
2.452	0.035	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Path Statistics:

Clock Skew	-0.002
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.855%; route: 1.068, 44.145%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.148, 50.685%; tC2Q: 0.144, 49.315%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path14

Path Summary:

Slack	0.259
Data Arrival Time	1.673
Data Required Time	1.413
From	ad_6_s0
To	b_d_0_s3
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[1][B]	ad_6_s0/CLK
1.520	0.144	tC2Q	RR	5	R27C55[1][B]	ad_6_s0/Q
1.673	0.153	tNET	RR	1	BSRAM_R28[17]	b_d_0_s3/AD[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.378	0.703	tNET	RR	1	BSRAM_R28[17]	b_d_0_s3/CLK
1.413	0.035	tHld		1	BSRAM_R28[17]	b_d_0_s3

Path Statistics:

Clock Skew	0.003
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.153, 51.515%; tC2Q: 0.144, 48.485%
Required Clock Path Delay	cell: 0.675, 49.003%; route: 0.703, 50.997%

Path15

Path Summary:

Slack	0.262
Data Arrival Time	1.671
Data Required Time	1.410
From	ad_4_s0
To	b_d_0_s2
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R27C55[2][B]	ad_4_s0/CLK
1.520	0.144	tC2Q	RR	7	R27C55[2][B]	ad_4_s0/Q
1.671	0.152	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/AD[8]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[16]	b_d_0_s2/CLK
1.410	0.035	tHld		1	BSRAM_R28[16]	b_d_0_s2

Path Statistics:

Clock Skew	-0.001
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.109%; route: 0.700, 50.891%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.152, 51.351%; tC2Q: 0.144, 48.649%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path16

Path Summary:

Slack	0.264
Data Arrival Time	2.716
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_4_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R18C47[2][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/CLK
2.566	0.144	tC2Q	RR	38	R18C47[2][A]	gw_gao_inst_0/u_la0_top/address_counter_4_s0/Q
2.716	0.150	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKB
2.452	0.035	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.775%; route: 1.071, 44.225%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.150, 51.020%; tC2Q: 0.144, 48.980%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path17

Path Summary:

Slack	0.270
Data Arrival Time	2.722
Data Required Time	2.452
From	gw_gao_inst_0/u_la0_top/address_counter_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R18C47[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.566	0.144	tC2Q	RR	37	R18C47[0][A]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q
2.722	0.156	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/ADB[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.417	1.066	tNET	RR	1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s/CLKB
2.452	0.035	tHld		1	BSRAM_R28[14]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_20_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.775%; route: 1.071, 44.225%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.156, 52.000%; tC2Q: 0.144, 48.000%
Required Clock Path Delay	cell: 1.351, 55.896%; route: 1.066, 44.104%

Path18

Path Summary:

Slack	0.275
Data Arrival Time	2.722
Data Required Time	2.447
From	gw_gao_inst_0/u_la0_top/address_counter_11_s0
To	gw_gao_inst_0/u_la0_top/address_counter_11_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/address_counter_11_s0/CLK
2.563	0.141	tC2Q	RF	34	R18C47[1][A]	gw_gao_inst_0/u_la0_top/address_counter_11_s0/Q
2.569	0.006	tNET	FF	1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_11_s0/I2
2.722	0.153	tINS	FF	1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_11_s0/F
2.722	0.000	tNET	FF	1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/address_counter_11_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.422	1.071	tNET	RR	1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/address_counter_11_s0/CLK
2.447	0.025	tHld		1	R18C47[1][A]	gw_gao_inst_0/u_la0_top/address_counter_11_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.775%; route: 1.071, 44.225%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.775%; route: 1.071, 44.225%

Path19

Path Summary:

Slack	0.275
Data Arrival Time	1.599
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_91_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.377	0.702	tNET	RR	1	R11C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_91_s0/CLK
1.521	0.144	tC2Q	RR	1	R11C46[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_91_s0/Q
1.599	0.078	tNET	RR	1	R11C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.377	0.702	tNET	RR	1	R11C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0/CLK
1.324	-0.053	tHld		1	R11C46[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_91_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.056%; route: 0.702, 50.944%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.056%; route: 0.702, 50.944%

Path20

Path Summary:

Slack	0.275
Data Arrival Time	1.674
Data Required Time	1.399
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.515	0.141	tC2Q	RF	36	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/Q
1.521	0.006	tNET	FF	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n892_s1/I2
1.674	0.153	tINS	FF	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n892_s1/F
1.674	0.000	tNET	FF	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
1.399	0.025	tHld		1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%

Path21

Path Summary:

Slack	0.275
Data Arrival Time	1.669
Data Required Time	1.393
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.510	0.141	tC2Q	RF	38	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/Q
1.516	0.006	tNET	FF	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n891_s1/I1
1.669	0.153	tINS	FF	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n891_s1/F
1.669	0.000	tNET	FF	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
1.393	0.025	tHld		1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path22

Path Summary:

Slack	0.275
Data Arrival Time	1.677
Data Required Time	1.402
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
1.518	0.141	tC2Q	RF	35	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/Q
1.524	0.006	tNET	FF	1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n888_s2/I2
1.677	0.153	tINS	FF	1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n888_s2/F
1.677	0.000	tNET	FF	1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1/CLK
1.402	0.025	tHld		1	R15C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path23

Path Summary:

Slack	0.275
Data Arrival Time	1.665
Data Required Time	1.390
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk:[R]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
1.506	0.141	tC2Q	RF	2	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/Q
1.512	0.006	tNET	FF	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n775_s0/I2
1.665	0.153	tINS	FF	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n775_s0/F
1.665	0.000	tNET	FF	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
1.390	0.025	tHld		1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path24

Path Summary:

Slack	0.275
Data Arrival Time	2.728
Data Required Time	2.453
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.569	0.141	tC2Q	RF	5	R25C37[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.575	0.006	tNET	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/I1
2.728	0.153	tINS	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s1/F
2.728	0.000	tNET	FF	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.428	1.077	tNET	RR	1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.453	0.025	tHld		1	R25C37[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.643%; route: 1.077, 44.357%

Path25

Path Summary:

Slack	0.275
Data Arrival Time	2.731
Data Required Time	2.456
From	gw_gao_inst_0/u_la0_top/word_count_6_s0
To	gw_gao_inst_0/u_la0_top/word_count_6_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.080	tNET	RR	1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CLK
2.572	0.141	tC2Q	RF	3	R26C47[1][A]	gw_gao_inst_0/u_la0_top/word_count_6_s0/Q
2.578	0.006	tNET	FF	1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_6_s0/I2
2.731	0.153	tINS	FF	1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_6_s0/F
2.731	0.000	tNET	FF	1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/word_count_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	493	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.080	tNET	RR	1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/word_count_6_s0/CLK
2.456	0.025	tHld		1	R26C47[1][A]	gw_gao_inst_0/u_la0_top/word_count_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.585%; route: 1.080, 44.415%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 1.351, 55.585%; route: 1.080, 44.415%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	2.860
Data Arrival Time	9.379
Data Required Time	12.239
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.587	1.904	tNET	RR	1	R13C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
12.239	-0.347	tSu		1	R13C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	-0.014
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.383%; route: 1.904, 73.617%

Path2

Path Summary:

Slack	2.864
Data Arrival Time	9.391
Data Required Time	12.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.391	1.347	tNET	FF	1	R17C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.602	1.920	tNET	RR	1	R17C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5/CLK
12.255	-0.347	tSu		1	R17C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s5

Path Statistics:

Clock Skew	0.001
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.347, 75.271%; tC2Q: 0.442, 24.729%
Required Clock Path Delay	cell: 0.683, 26.225%; route: 1.920, 73.775%

Path3

Path Summary:

Slack	2.864
Data Arrival Time	9.391
Data Required Time	12.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.391	1.347	tNET	FF	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.602	1.920	tNET	RR	1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
12.255	-0.347	tSu		1	R17C51[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.347, 75.271%; tC2Q: 0.442, 24.729%
Required Clock Path Delay	cell: 0.683, 26.225%; route: 1.920, 73.775%

Path4

Path Summary:

Slack	2.864
Data Arrival Time	9.387
Data Required Time	12.251
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.387	1.343	tNET	FF	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.599	1.916	tNET	RR	1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
12.251	-0.347	tSu		1	R15C51[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.343, 75.219%; tC2Q: 0.442, 24.781%
Required Clock Path Delay	cell: 0.683, 26.263%; route: 1.916, 73.737%

Path5

Path Summary:

Slack	2.870
Data Arrival Time	9.385
Data Required Time	12.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.385	1.341	tNET	FF	1	R14C50[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.602	1.920	tNET	RR	1	R14C50[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
12.255	-0.347	tSu		1	R14C50[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.341, 75.193%; tC2Q: 0.442, 24.807%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path6

Path Summary:

Slack	2.870
Data Arrival Time	9.379
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
12.249	-0.347	tSu		1	R13C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path7

Path Summary:

Slack	2.870
Data Arrival Time	9.385
Data Required Time	12.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.385	1.341	tNET	FF	1	R14C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.602	1.920	tNET	RR	1	R14C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
12.255	-0.347	tSu		1	R14C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.341, 75.193%; tC2Q: 0.442, 24.807%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path8

Path Summary:

Slack	2.870
Data Arrival Time	9.379
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
12.249	-0.347	tSu		1	R13C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path9

Path Summary:

Slack	2.870
Data Arrival Time	9.379
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK
12.249	-0.347	tSu		1	R13C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path10

Path Summary:

Slack	2.870
Data Arrival Time	9.379
Data Required Time	12.249
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.596	1.914	tNET	RR	1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1/CLK
12.249	-0.347	tSu		1	R13C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_11_s1

Path Statistics:

Clock Skew	-0.005
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.288%; route: 1.914, 73.712%

Path11

Path Summary:

Slack	2.870
Data Arrival Time	9.373
Data Required Time	12.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.373	1.329	tNET	FF	1	R12C50[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.590	1.908	tNET	RR	1	R12C50[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
12.243	-0.347	tSu		1	R12C50[2][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.329, 75.026%; tC2Q: 0.442, 24.974%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path12

Path Summary:

Slack	2.872
Data Arrival Time	9.407
Data Required Time	12.279
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.407	1.363	tNET	FF	1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.626	1.944	tNET	RR	1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLK
12.279	-0.347	tSu		1	R25C51[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0

Path Statistics:

Clock Skew	0.025
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.363, 75.489%; tC2Q: 0.442, 24.511%
Required Clock Path Delay	cell: 0.683, 25.988%; route: 1.944, 74.012%

Path13

Path Summary:

Slack	2.874
Data Arrival Time	9.387
Data Required Time	12.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.387	1.343	tNET	FF	1	R15C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.608	1.926	tNET	RR	1	R15C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
12.261	-0.347	tSu		1	R15C48[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.343, 75.219%; tC2Q: 0.442, 24.781%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path14

Path Summary:

Slack	2.874
Data Arrival Time	9.387
Data Required Time	12.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.387	1.343	tNET	FF	1	R15C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.608	1.926	tNET	RR	1	R15C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
12.261	-0.347	tSu		1	R15C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	0.007
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.343, 75.219%; tC2Q: 0.442, 24.781%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path15

Path Summary:

Slack	2.874
Data Arrival Time	9.391
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.391	1.347	tNET	FF	1	R17C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R17C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
12.264	-0.347	tSu		1	R17C48[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.347, 75.271%; tC2Q: 0.442, 24.729%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path16

Path Summary:

Slack	2.874
Data Arrival Time	9.391
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.391	1.347	tNET	FF	1	R17C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R17C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
12.264	-0.347	tSu		1	R17C50[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.347, 75.271%; tC2Q: 0.442, 24.729%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path17

Path Summary:

Slack	2.874
Data Arrival Time	9.391
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.391	1.347	tNET	FF	1	R17C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R17C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
12.264	-0.347	tSu		1	R17C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	0.011
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.347, 75.271%; tC2Q: 0.442, 24.729%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path18

Path Summary:

Slack	2.874
Data Arrival Time	9.389
Data Required Time	12.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.389	1.345	tNET	FF	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.610	1.928	tNET	RR	1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
12.263	-0.347	tSu		1	R16C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	0.009
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.345, 75.245%; tC2Q: 0.442, 24.755%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path19

Path Summary:

Slack	2.877
Data Arrival Time	9.414
Data Required Time	12.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.414	1.370	tNET	FF	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.638	1.956	tNET	RR	1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
12.291	-0.347	tSu		1	R24C50[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	0.037
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 75.586%; tC2Q: 0.442, 24.414%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path20

Path Summary:

Slack	2.877
Data Arrival Time	9.414
Data Required Time	12.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.414	1.370	tNET	FF	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.638	1.956	tNET	RR	1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
12.291	-0.347	tSu		1	R24C50[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	0.037
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 75.586%; tC2Q: 0.442, 24.414%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path21

Path Summary:

Slack	2.877
Data Arrival Time	9.414
Data Required Time	12.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.414	1.370	tNET	FF	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.638	1.956	tNET	RR	1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLK
12.291	-0.347	tSu		1	R24C50[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0

Path Statistics:

Clock Skew	0.037
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 75.586%; tC2Q: 0.442, 24.414%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path22

Path Summary:

Slack	2.877
Data Arrival Time	9.414
Data Required Time	12.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.414	1.370	tNET	FF	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.638	1.956	tNET	RR	1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLK
12.291	-0.347	tSu		1	R24C50[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0

Path Statistics:

Clock Skew	0.037
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.370, 75.586%; tC2Q: 0.442, 24.414%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path23

Path Summary:

Slack	2.879
Data Arrival Time	9.379
Data Required Time	12.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
12.258	-0.347	tSu		1	R13C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Path24

Path Summary:

Slack	2.879
Data Arrival Time	9.385
Data Required Time	12.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.385	1.341	tNET	FF	1	R14C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.612	1.929	tNET	RR	1	R14C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
12.264	-0.347	tSu		1	R14C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	0.010
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.341, 75.193%; tC2Q: 0.442, 24.807%
Required Clock Path Delay	cell: 0.683, 26.134%; route: 1.929, 73.866%

Path25

Path Summary:

Slack	2.879
Data Arrival Time	9.379
Data Required Time	12.258
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.688	0.688	tINS	FF	526	IOB29[A]	clk_ibuf/O
7.601	1.914	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
8.044	0.442	tC2Q	FF	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
9.379	1.335	tNET	FF	1	R13C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk
10.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
10.682	0.683	tINS	RR	526	IOB29[A]	clk_ibuf/O
12.606	1.923	tNET	RR	1	R13C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
12.258	-0.347	tSu		1	R13C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.004
Setup Relationship	5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.430%; route: 1.914, 73.570%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.335, 75.110%; tC2Q: 0.442, 24.890%
Required Clock Path Delay	cell: 0.683, 26.193%; route: 1.923, 73.807%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C45[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C45[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
1.321	-0.053	tHld		1	R11C45[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path2

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
1.321	-0.053	tHld		1	R11C37[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path3

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
1.321	-0.053	tHld		1	R11C37[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path4

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
1.321	-0.053	tHld		1	R11C37[3][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path5

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.321	-0.053	tHld		1	R11C37[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path6

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
1.321	-0.053	tHld		1	R11C37[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path7

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1/CLK
1.321	-0.053	tHld		1	R11C37[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_11_s1

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path8

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C49[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C49[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
1.321	-0.053	tHld		1	R11C49[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path9

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C49[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C49[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0/CLK
1.321	-0.053	tHld		1	R11C49[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_0_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path10

Path Summary:

Slack	5.683
Data Arrival Time	7.003
Data Required Time	1.320
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0/CLK
1.321	-0.053	tHld		1	R11C49[2][A]	gw_gao_inst_0/u_la0_top/internal_reg_force_triger_syn_1_s0

Path Statistics:

Clock Skew	0.001
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path11

Path Summary:

Slack	5.687
Data Arrival Time	7.023
Data Required Time	1.336
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.023	0.492	tNET	RR	1	R26C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.388	0.713	tNET	RR	1	R26C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.336	-0.053	tHld		1	R26C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	0.016
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.492, 75.692%; tC2Q: 0.158, 24.308%
Required Clock Path Delay	cell: 0.675, 48.650%; route: 0.713, 51.350%

Path12

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
1.341	-0.053	tHld		1	R25C49[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path13

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
1.341	-0.053	tHld		1	R25C49[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path14

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK
1.341	-0.053	tHld		1	R25C49[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path15

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
1.341	-0.053	tHld		1	R25C49[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path16

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
1.341	-0.053	tHld		1	R25C49[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path17

Path Summary:

Slack	5.687
Data Arrival Time	7.028
Data Required Time	1.341
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.028	0.497	tNET	RR	1	R25C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.394	0.718	tNET	RR	1	R25C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK
1.341	-0.053	tHld		1	R25C49[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Path Statistics:

Clock Skew	0.021
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.497, 75.878%; tC2Q: 0.158, 24.122%
Required Clock Path Delay	cell: 0.675, 48.475%; route: 0.718, 51.525%

Path18

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C48[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C48[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
1.316	-0.053	tHld		1	R11C48[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path19

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.316	-0.053	tHld		1	R11C38[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path20

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1/CLK
1.316	-0.053	tHld		1	R11C38[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_10_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path21

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C48[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C48[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.316	-0.053	tHld		1	R11C48[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path22

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C48[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C48[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
1.316	-0.053	tHld		1	R11C48[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path23

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C48[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C48[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
1.316	-0.053	tHld		1	R11C48[2][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path24

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C50[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C50[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
1.316	-0.053	tHld		1	R11C50[0][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path25

Path Summary:

Slack	5.687
Data Arrival Time	7.003
Data Required Time	1.317
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	clk:[F]
Latch Clk	clk:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
5.000	5.000					active clock edge time
5.000	0.000					clk
5.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
5.677	0.678	tINS	FF	526	IOB29[A]	clk_ibuf/O
6.372	0.695	tNET	FF	1	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
6.530	0.158	tC2Q	FR	75	R11C51[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
7.003	0.473	tNET	RR	1	R11C50[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	526	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C50[2][B]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
1.316	-0.053	tHld		1	R11C50[2][B]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-0.003
Hold Relationship	-5.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.362%; route: 0.695, 50.638%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.473, 74.960%; tC2Q: 0.158, 25.040%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	b_d_0_s3

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	b_d_0_s3/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	b_d_0_s3/CLK

MPW2

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA

MPW3

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA

MPW4

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA

MPW5

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_27_s/CLKA

MPW6

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_28_s/CLKA

MPW7

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_15_s/CLKA

MPW8

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_16_s/CLKA

MPW9

MPW Summary:

Slack:	2.751
Actual Width:	3.751
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	uut/u_xcorr/memx_memx_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.627	1.940	tNET	FF	uut/u_xcorr/memx_memx_0_0_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.378	0.703	tNET	RR	uut/u_xcorr/memx_memx_0_0_s/CLKA

MPW10

MPW Summary:

Slack:	2.757
Actual Width:	3.757
Required Width:	1.000
Type:	Low Pulse Width
Clock:	clk
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_32_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk
5.000	0.000	tCL	FF	clk_ibuf/I
5.688	0.688	tINS	FF	clk_ibuf/O
7.618	1.930	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_32_s/CLKA

Early clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			clk
10.000	0.000	tCL	RR	clk_ibuf/I
10.675	0.675	tINS	RR	clk_ibuf/O
11.375	0.699	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_32_s/CLKA

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
526	clk_d	0.657	1.970
493	gw_gao_inst_0/control0[0]	3.780	2.754
153	gw_gao_inst_0/u_la0_top/n20_3	46.217	1.619
133	gw_gao_inst_0/u_la0_top/data_out_shift_reg_130_7	43.192	1.858
131	gw_gao_inst_0/u_la0_top/n1192_5	43.516	1.981
121	gw_gao_inst_0/u_la0_top/n1192_4	43.192	1.658
75	gw_gao_inst_0/u_la0_top/rst_ao	2.860	1.465
58	uut/u_xcorr/cnt[0]	2.746	1.883
49	uut/u_xcorr/n212_7	0.657	0.864
47	complete_d	6.990	3.306

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C7	100.00%
R2C9	100.00%
R2C10	100.00%
R2C42	100.00%
R3C15	100.00%
R4C52	100.00%
R7C37	100.00%
R13C21	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk -period 10 -waveform {0 5} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {clk}] -to [get_clocks {tck_pad_i}]