Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\src\top.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\src\xcorr\xcorr.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_XCORR_RefDesign\XCORR_17_1024_16_case\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Jun 10 15:32:31 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.64s, Elapsed time = 0h 0m 0.663s, Peak memory usage = 640.105MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 640.105MB
    Optimizing Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.048s, Peak memory usage = 640.105MB
    Optimizing Phase 2: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.509s, Peak memory usage = 640.105MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.071s, Peak memory usage = 640.105MB
    Inferring Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 640.105MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 640.105MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 640.105MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.12s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.22s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.133s, Peak memory usage = 640.105MB
Generate output files:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.153s, Peak memory usage = 640.105MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 640.105MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 91
I/O Buf 91
    IBUF 5
    OBUF 86
Register 947
    DFFRE 75
    DFFPE 37
    DFFCE 835
LUT 872
    LUT2 152
    LUT3 174
    LUT4 546
MUX 1
    MUX16 1
ALU 33
    ALU 33
INV 24
    INV 24
DSP
    MULTALU27X18 1
BSRAM 37
    SDPB 33
    SDPX9B 2
    pROMX9 2
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 937(904 LUT, 33 ALU) / 23040 5%
Register 947 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 947 / 23685 4%
BSRAM 37 / 56 67%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 115.467(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.340
Data Arrival Time 8.972
Data Required Time 10.311
From uut/u_xcorr/cnt_7_s1
To uut/u_xcorr/result_41_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 526 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_7_s1/CLK
0.757 0.382 tC2Q RR 13 uut/u_xcorr/cnt_7_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n21_s5/I0
1.659 0.526 tINS RR 5 uut/u_xcorr/n21_s5/F
2.034 0.375 tNET RR 1 uut/u_xcorr/n212_s3/I0
2.560 0.526 tINS RR 49 uut/u_xcorr/n212_s3/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I1
3.451 0.516 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.826 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.720 3.894 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[41]
8.070 0.350 tNET FF 1 uut/u_xcorr/n877_s2/I0
8.597 0.526 tINS FR 1 uut/u_xcorr/n877_s2/F
8.972 0.375 tNET RR 1 uut/u_xcorr/result_41_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 526 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_41_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_41_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.989, 69.669%; route: 2.225, 25.882%; tC2Q: 0.382, 4.449%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 1.341
Data Arrival Time 8.971
Data Required Time 10.311
From uut/u_xcorr/cnt_7_s1
To uut/u_xcorr/result_42_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 526 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_7_s1/CLK
0.757 0.382 tC2Q RR 13 uut/u_xcorr/cnt_7_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n21_s5/I0
1.659 0.526 tINS RR 5 uut/u_xcorr/n21_s5/F
2.034 0.375 tNET RR 1 uut/u_xcorr/n212_s3/I0
2.560 0.526 tINS RR 49 uut/u_xcorr/n212_s3/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I1
3.451 0.516 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.826 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.719 3.893 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[42]
8.069 0.350 tNET FF 1 uut/u_xcorr/n876_s2/I0
8.596 0.526 tINS FR 1 uut/u_xcorr/n876_s2/F
8.971 0.375 tNET RR 1 uut/u_xcorr/result_42_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 526 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_42_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_42_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.988, 69.665%; route: 2.225, 25.885%; tC2Q: 0.382, 4.450%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 1.354
Data Arrival Time 8.957
Data Required Time 10.311
From uut/u_xcorr/cnt_7_s1
To uut/u_xcorr/result_43_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 526 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_7_s1/CLK
0.757 0.382 tC2Q RR 13 uut/u_xcorr/cnt_7_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n21_s5/I0
1.659 0.526 tINS RR 5 uut/u_xcorr/n21_s5/F
2.034 0.375 tNET RR 1 uut/u_xcorr/n212_s3/I0
2.560 0.526 tINS RR 49 uut/u_xcorr/n212_s3/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I1
3.451 0.516 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.826 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.706 3.880 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[43]
8.056 0.350 tNET FF 1 uut/u_xcorr/n875_s2/I0
8.582 0.526 tINS FR 1 uut/u_xcorr/n875_s2/F
8.957 0.375 tNET RR 1 uut/u_xcorr/result_43_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 526 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_43_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_43_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.975, 69.617%; route: 2.225, 25.926%; tC2Q: 0.382, 4.457%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 1.364
Data Arrival Time 8.947
Data Required Time 10.311
From uut/u_xcorr/cnt_7_s1
To uut/u_xcorr/result_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 526 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_7_s1/CLK
0.757 0.382 tC2Q RR 13 uut/u_xcorr/cnt_7_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n21_s5/I0
1.659 0.526 tINS RR 5 uut/u_xcorr/n21_s5/F
2.034 0.375 tNET RR 1 uut/u_xcorr/n212_s3/I0
2.560 0.526 tINS RR 49 uut/u_xcorr/n212_s3/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I1
3.451 0.516 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.826 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.696 3.870 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[36]
8.046 0.350 tNET FF 1 uut/u_xcorr/n882_s2/I0
8.572 0.526 tINS FR 1 uut/u_xcorr/n882_s2/F
8.947 0.375 tNET RR 1 uut/u_xcorr/result_36_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 526 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_36_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.965, 69.582%; route: 2.225, 25.956%; tC2Q: 0.382, 4.462%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 1.374
Data Arrival Time 8.937
Data Required Time 10.311
From uut/u_xcorr/cnt_7_s1
To uut/u_xcorr/result_40_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 526 clk_ibuf/O
0.375 0.375 tNET RR 1 uut/u_xcorr/cnt_7_s1/CLK
0.757 0.382 tC2Q RR 13 uut/u_xcorr/cnt_7_s1/Q
1.132 0.375 tNET RR 1 uut/u_xcorr/n21_s5/I0
1.659 0.526 tINS RR 5 uut/u_xcorr/n21_s5/F
2.034 0.375 tNET RR 1 uut/u_xcorr/n212_s3/I0
2.560 0.526 tINS RR 49 uut/u_xcorr/n212_s3/F
2.935 0.375 tNET RR 1 uut/u_xcorr/r_5_s3/I1
3.451 0.516 tINS RR 1 uut/u_xcorr/r_5_s3/F
3.826 0.375 tNET RR 86 uut/u_xcorr/m1/n4_s0/C[5]
7.686 3.860 tINS RF 1 uut/u_xcorr/m1/n4_s0/DOUT[40]
8.036 0.350 tNET FF 1 uut/u_xcorr/n878_s2/I0
8.562 0.526 tINS FR 1 uut/u_xcorr/n878_s2/F
8.937 0.375 tNET RR 1 uut/u_xcorr/result_40_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 526 clk_ibuf/O
10.375 0.375 tNET RR 1 uut/u_xcorr/result_40_s0/CLK
10.311 -0.064 tSu 1 uut/u_xcorr/result_40_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.955, 69.547%; route: 2.225, 25.986%; tC2Q: 0.382, 4.467%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%