rtl_dir:=				../../project/src
tb_dir:=				../../tb
inc_dir:=				$(rtl_dir)/data
vo_dir:=				$(rtl_dir)/nlms_adaptive_filter
vo_file:=				$(vo_dir)/nlms_adaptive_filter.vo
tb_file:=				$(tb_dir)/tb.v
prim_sim_file:=			$(tb_dir)/prim_sim.v
rtl_file:=				$(rtl_dir)/nlms_example_top.v						\
						$(rtl_dir)/deUstb.v									\
						$(rtl_dir)/gw_pll_100M.v			
data_dir:= 				./data

vcs:	
	vcs -debug_all -R -full64 -fsdb -sverilog 								\
	-v $(prim_sim_file) 													\
	$(tb_file)																\
	$(vo_file)																\
	$(rtl_file)																\
	+incdir+$(inc_dir)														\
    -cm line+cond+fsm+branch+tgl	

vd:
	verdi -sverilog															\
	-v $(prim_sim_file) 													\
	$(tb_file)																\
	$(vo_file)																\
	$(rtl_file)																\
	+incdir+$(inc_dir)														\
	-ssf tb.fsdb															\
	&
#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf csrc simv.daidir simv.vdb verdiLog cm.log novas.conf novas.rc novas_dump.log simv tb.fsdb ucli.key wave.ses.png 