Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\FOC_TDM\data\foc_current_loop_control_tdm.v C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\FOC_TDM\data\foc_current_loop_control_tdm_wrap.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.01 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Mon Nov 01 09:26:46 2021 |
| Legal Announcement | Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | FOC_Current_Loop_Control_TDM_Top |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.399s, Peak memory usage = 55.098MB Running netlist conversion: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 55.098MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.171s, Elapsed time = 0h 0m 0.166s, Peak memory usage = 55.098MB Optimizing Phase 1: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.084s, Peak memory usage = 55.098MB Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.215s, Peak memory usage = 55.098MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.047s, Peak memory usage = 55.098MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 55.098MB Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.023s, Peak memory usage = 55.098MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 55.098MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.164s, Peak memory usage = 55.098MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.053s, Peak memory usage = 55.098MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 55.098MB Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 68.148MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.273s, Peak memory usage = 68.148MB Generate output files: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 68.148MB |
| Total Time and Memory Usage | CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 68.148MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 263 |
| I/O Buf | 257 |
| IBUF | 238 |
| OBUF | 19 |
| Register | 2195 |
| DFF | 154 |
| DFFE | 698 |
| DFFS | 3 |
| DFFSE | 62 |
| DFFRE | 66 |
| DFFPE | 8 |
| DFFC | 219 |
| DFFCE | 985 |
| LUT | 1510 |
| LUT2 | 150 |
| LUT3 | 771 |
| LUT4 | 589 |
| ALU | 613 |
| ALU | 613 |
| SSRAM | 48 |
| RAM16SDP4 | 48 |
| INV | 37 |
| INV | 37 |
| DSP | 6 |
| MULT18X18 | 6 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 2448(1547 LUTs, 613 ALUs, 48 SSRAMs) / 20736 | 12% |
| Register | 2195 / 16173 | 14% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 2195 / 16173 | 14% |
| BSRAM | 0 / 46 | 0% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| clk | Base | 10.000 | 100.0 | 0.000 | 5.000 | clk_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 100.0(MHz) | 171.4(MHz) | 8 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 4.164 |
| Data Arrival Time | 6.663 |
| Data Required Time | 10.828 |
| From | foc_current_loop_control/svpwm_inst/ict_inst/out_Ub_3_s0 |
| To | foc_current_loop_control/svpwm_inst/tmp_x_14_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/ict_inst/out_Ub_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 4 | foc_current_loop_control/svpwm_inst/ict_inst/out_Ub_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n348_s24/I1 |
| 1.887 | 0.555 | tINS | FF | 5 | foc_current_loop_control/svpwm_inst/n348_s24/F |
| 2.124 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n345_s24/I3 |
| 2.495 | 0.371 | tINS | FF | 5 | foc_current_loop_control/svpwm_inst/n345_s24/F |
| 2.732 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n342_s24/I3 |
| 3.103 | 0.371 | tINS | FF | 6 | foc_current_loop_control/svpwm_inst/n342_s24/F |
| 3.340 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n339_s24/I3 |
| 3.711 | 0.371 | tINS | FF | 6 | foc_current_loop_control/svpwm_inst/n339_s24/F |
| 3.948 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s24/I1 |
| 4.503 | 0.555 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s24/F |
| 4.740 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s30/I1 |
| 5.294 | 0.555 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s30/F |
| 5.531 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s18/I1 |
| 5.635 | 0.103 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s18/O |
| 5.872 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s27/I1 |
| 6.426 | 0.555 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s27/F |
| 6.663 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/tmp_x_14_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/tmp_x_14_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | foc_current_loop_control/svpwm_inst/tmp_x_14_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.436, 59.231%; route: 2.133, 36.770%; tC2Q: 0.232, 3.999% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 4.368 |
| Data Arrival Time | 6.460 |
| Data Required Time | 10.828 |
| From | foc_current_loop_control/svpwm_inst/ict_inst/out_Uc_2_s0 |
| To | foc_current_loop_control/svpwm_inst/tmp_y_14_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/ict_inst/out_Uc_2_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | foc_current_loop_control/svpwm_inst/ict_inst/out_Uc_2_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n365_s24/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | foc_current_loop_control/svpwm_inst/n365_s24/F |
| 2.124 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n362_s24/I3 |
| 2.495 | 0.371 | tINS | FF | 5 | foc_current_loop_control/svpwm_inst/n362_s24/F |
| 2.732 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n359_s24/I3 |
| 3.103 | 0.371 | tINS | FF | 5 | foc_current_loop_control/svpwm_inst/n359_s24/F |
| 3.340 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n356_s24/I3 |
| 3.711 | 0.371 | tINS | FF | 5 | foc_current_loop_control/svpwm_inst/n356_s24/F |
| 3.948 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n338_s22/I1 |
| 4.503 | 0.555 | tINS | FF | 2 | foc_current_loop_control/svpwm_inst/n338_s22/F |
| 4.740 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s29/I2 |
| 5.193 | 0.453 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s29/F |
| 5.430 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s18/I1 |
| 5.533 | 0.103 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s18/O |
| 5.770 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s26/I2 |
| 6.223 | 0.453 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n355_s26/F |
| 6.460 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/tmp_y_14_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/tmp_y_14_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | foc_current_loop_control/svpwm_inst/tmp_y_14_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.232, 57.745%; route: 2.133, 38.110%; tC2Q: 0.232, 4.145% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 4.460 |
| Data Arrival Time | 6.368 |
| Data Required Time | 10.828 |
| From | foc_current_loop_control/svpwm_inst/ict_inst/out_Ua_2_s0 |
| To | foc_current_loop_control/svpwm_inst/tmp_x_11_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/ict_inst/out_Ua_2_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | foc_current_loop_control/svpwm_inst/ict_inst/out_Ua_2_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n348_s25/I1 |
| 1.887 | 0.555 | tINS | FF | 6 | foc_current_loop_control/svpwm_inst/n348_s25/F |
| 2.124 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n345_s25/I3 |
| 2.495 | 0.371 | tINS | FF | 6 | foc_current_loop_control/svpwm_inst/n345_s25/F |
| 2.732 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n342_s26/I3 |
| 3.103 | 0.371 | tINS | FF | 8 | foc_current_loop_control/svpwm_inst/n342_s26/F |
| 3.340 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n358_s22/I1 |
| 3.895 | 0.555 | tINS | FF | 2 | foc_current_loop_control/svpwm_inst/n358_s22/F |
| 4.132 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s21/I2 |
| 4.585 | 0.453 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s21/F |
| 4.822 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s27/I1 |
| 5.377 | 0.555 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s27/F |
| 5.614 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s26/I0 |
| 6.131 | 0.517 | tINS | FF | 1 | foc_current_loop_control/svpwm_inst/n341_s26/F |
| 6.368 | 0.237 | tNET | FF | 1 | foc_current_loop_control/svpwm_inst/tmp_x_11_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/svpwm_inst/tmp_x_11_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | foc_current_loop_control/svpwm_inst/tmp_x_11_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.377, 61.345%; route: 1.896, 34.441%; tC2Q: 0.232, 4.214% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 4.896 |
| Data Arrival Time | 5.932 |
| Data Required Time | 10.828 |
| From | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_c_1_s0 |
| To | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_c_p_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_c_1_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 7 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_c_1_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s42/I1 |
| 1.887 | 0.555 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s42/F |
| 2.124 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s35/I0 |
| 2.641 | 0.517 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s35/F |
| 2.878 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s18/I1 |
| 3.433 | 0.555 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s18/F |
| 3.670 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s6/I0 |
| 4.187 | 0.517 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s6/F |
| 4.424 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s2/I0 |
| 4.941 | 0.517 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s2/F |
| 5.178 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s1/I0 |
| 5.695 | 0.517 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n665_s1/F |
| 5.932 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_c_p_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_c_p_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_c_p_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.178, 62.695%; route: 1.659, 32.728%; tC2Q: 0.232, 4.577% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 4.922 |
| Data Arrival Time | 5.906 |
| Data Required Time | 10.828 |
| From | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_a_3_s0 |
| To | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_a_p_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_a_3_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/duty_cycle_a_3_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s38/I1 |
| 1.887 | 0.555 | tINS | FF | 7 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s38/F |
| 2.124 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s25/I1 |
| 2.679 | 0.555 | tINS | FF | 3 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s25/F |
| 2.916 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s22/I0 |
| 3.433 | 0.517 | tINS | FF | 2 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s22/F |
| 3.670 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s8/I1 |
| 4.225 | 0.555 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s8/F |
| 4.462 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s2/I2 |
| 4.915 | 0.453 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s2/F |
| 5.152 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s1/I0 |
| 5.669 | 0.517 | tINS | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/n661_s1/F |
| 5.906 | 0.237 | tNET | FF | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_a_p_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clk | |||
| 10.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 2245 | clk_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_a_p_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | foc_current_loop_control/pwm_chn_gen[1].pwm_gen_inst/pwm_a_p_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 3.152, 62.503%; route: 1.659, 32.897%; tC2Q: 0.232, 4.600% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |