Project Settings
Project Name ao_0 Device Name rev_1: GOWIN-GW2A : GW2A_55
Implementation Name rev_1 Top Module [auto]
Pipelining 1 Retiming 0
Resource Sharing 1 Fanout Guide 10000
Disable I/O Insertion 0 Disable Sequential Optimizations 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 28 0 - 00m:02s - 2018/9/28
13:59:45
(premap)Complete 14 0 0 0m:01s 0m:02s 194MB 2018/9/28
13:59:49
(fpga_mapper)Complete 11 2 0 0m:09s 0m:09s 229MB 2018/9/28
13:59:58
Multi-srs Generator Complete2018/9/28
13:59:46

Area Summary
I/O ports (io_port) 91 Non I/O Register bits (non_io_reg) 486 (1%)
I/O Register bits (total_io_reg) 0 Block Rams (v_ram) 5 (140)
Block Multipliers (dsp_used) 0 (20) LUTs (total_luts) 494 (0%)

Timing Summary
Clock NameReq FreqEst FreqSlack
ao_top_0|clk_i212.2 MHz180.3 MHz-0.832
ao_top_0|control[0]154.5 MHz131.3 MHz-1.143
System150.0 MHz244.2 MHz2.571

Optimizations Summary
Combined Clock Conversion 2 / 0