Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\Complex_Multiplier\complex_multiplier.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\src\top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_9\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Jun 10 15:51:38 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.478s, Peak memory usage = 640.105MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 640.105MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 640.105MB
    Optimizing Phase 2: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.238s, Peak memory usage = 640.105MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 640.105MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 640.105MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 640.105MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 640.105MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.045s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.108s, Peak memory usage = 640.105MB
Generate output files:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.087s, Peak memory usage = 640.105MB
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 640.105MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 46
I/O Buf 46
    IBUF 5
    OBUF 41
Register 622
    DFFRE 1
    DFFPE 38
    DFFCE 583
LUT 520
    LUT2 56
    LUT3 115
    LUT4 349
MUX 1
    MUX16 1
ALU 100
    ALU 100
INV 5
    INV 5
DSP
    MULT12X12 3
BSRAM 7
    SDPB 5
    pROMX9 2
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 633(533 LUT, 100 ALU) / 23040 3%
Register 622 / 23685 3%
  --Register as Latch 0 / 23685 0%
  --Register as FF 622 / 23685 3%
BSRAM 7 / 56 13%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 123.253(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 1.887
Data Arrival Time 8.425
Data Required Time 10.311
From memreal1_memreal1_0_0_s
To u_complex_mult/comp_mult_inst/realo_18_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 286 clk_ibuf/O
0.375 0.375 tNET RR 36 memreal1_memreal1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memreal1_memreal1_0_0_s/DO[27]
2.765 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/sum3_0_s/I1
3.327 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/sum3_0_s/COUT
3.327 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/sum3_1_s/CIN
3.571 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/sum3_1_s/SUM
3.946 0.375 tNET RR 23 u_complex_mult/comp_mult_inst/prod3_18_s0/B[1]
6.818 2.872 tINS RR 1 u_complex_mult/comp_mult_inst/prod3_18_s0/DOUT[16]
7.193 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/n129_s/I1
7.756 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/n129_s/COUT
7.756 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/n128_s/CIN
7.806 0.050 tINS FR 1 u_complex_mult/comp_mult_inst/n128_s/COUT
7.806 0.000 tNET RR 2 u_complex_mult/comp_mult_inst/n127_s/CIN
8.050 0.244 tINS RR 1 u_complex_mult/comp_mult_inst/n127_s/SUM
8.425 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_18_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 286 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_18_s0/CLK
10.311 -0.064 tSu 1 u_complex_mult/comp_mult_inst/realo_18_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.535, 56.334%; route: 1.500, 18.634%; tC2Q: 2.015, 25.032%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 1.937
Data Arrival Time 8.375
Data Required Time 10.311
From memreal1_memreal1_0_0_s
To u_complex_mult/comp_mult_inst/realo_17_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 286 clk_ibuf/O
0.375 0.375 tNET RR 36 memreal1_memreal1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memreal1_memreal1_0_0_s/DO[27]
2.765 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/sum3_0_s/I1
3.327 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/sum3_0_s/COUT
3.327 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/sum3_1_s/CIN
3.571 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/sum3_1_s/SUM
3.946 0.375 tNET RR 23 u_complex_mult/comp_mult_inst/prod3_18_s0/B[1]
6.818 2.872 tINS RR 1 u_complex_mult/comp_mult_inst/prod3_18_s0/DOUT[16]
7.193 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/n129_s/I1
7.756 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/n129_s/COUT
7.756 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/n128_s/CIN
8.000 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/n128_s/SUM
8.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_17_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 286 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_17_s0/CLK
10.311 -0.064 tSu 1 u_complex_mult/comp_mult_inst/realo_17_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.485, 56.060%; route: 1.500, 18.751%; tC2Q: 2.015, 25.189%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 1.997
Data Arrival Time 8.314
Data Required Time 10.311
From memreal1_memreal1_0_0_s
To u_complex_mult/comp_mult_inst/realo_16_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 286 clk_ibuf/O
0.375 0.375 tNET RR 36 memreal1_memreal1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memreal1_memreal1_0_0_s/DO[27]
2.765 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/sum3_0_s/I1
3.327 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/sum3_0_s/COUT
3.327 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/sum3_1_s/CIN
3.571 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/sum3_1_s/SUM
3.946 0.375 tNET RR 23 u_complex_mult/comp_mult_inst/prod3_18_s0/B[1]
6.758 2.812 tINS RR 1 u_complex_mult/comp_mult_inst/prod3_18_s0/DOUT[15]
7.133 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/n130_s/I1
7.695 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/n130_s/COUT
7.695 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/n129_s/CIN
7.939 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/n129_s/SUM
8.314 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_16_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 286 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_16_s0/CLK
10.311 -0.064 tSu 1 u_complex_mult/comp_mult_inst/realo_16_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.424, 55.725%; route: 1.500, 18.894%; tC2Q: 2.015, 25.381%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 2.072
Data Arrival Time 8.239
Data Required Time 10.311
From memreal1_memreal1_0_0_s
To u_complex_mult/comp_mult_inst/realo_15_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 286 clk_ibuf/O
0.375 0.375 tNET RR 36 memreal1_memreal1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memreal1_memreal1_0_0_s/DO[18]
2.765 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/sum1_0_s/I1
3.327 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/sum1_0_s/COUT
3.327 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/sum1_1_s/CIN
3.571 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/sum1_1_s/SUM
3.946 0.375 tNET RR 23 u_complex_mult/comp_mult_inst/prod1_18_s0/B[1]
6.758 2.812 tINS RR 2 u_complex_mult/comp_mult_inst/prod1_18_s0/DOUT[15]
7.133 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/n130_s/I0
7.864 0.731 tINS RR 1 u_complex_mult/comp_mult_inst/n130_s/SUM
8.239 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_15_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 286 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_15_s0/CLK
10.311 -0.064 tSu 1 u_complex_mult/comp_mult_inst/realo_15_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.349, 55.303%; route: 1.500, 19.074%; tC2Q: 2.015, 25.623%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 2.157
Data Arrival Time 8.154
Data Required Time 10.311
From memreal1_memreal1_0_0_s
To u_complex_mult/comp_mult_inst/realo_14_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 286 clk_ibuf/O
0.375 0.375 tNET RR 36 memreal1_memreal1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memreal1_memreal1_0_0_s/DO[27]
2.765 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/sum3_0_s/I1
3.327 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/sum3_0_s/COUT
3.327 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/sum3_1_s/CIN
3.571 0.244 tINS FR 1 u_complex_mult/comp_mult_inst/sum3_1_s/SUM
3.946 0.375 tNET RR 23 u_complex_mult/comp_mult_inst/prod3_18_s0/B[1]
6.448 2.502 tINS RR 1 u_complex_mult/comp_mult_inst/prod3_18_s0/DOUT[10]
6.823 0.375 tNET RR 2 u_complex_mult/comp_mult_inst/n135_s/I1
7.386 0.563 tINS RF 1 u_complex_mult/comp_mult_inst/n135_s/COUT
7.386 0.000 tNET FF 2 u_complex_mult/comp_mult_inst/n134_s/CIN
7.436 0.050 tINS FR 1 u_complex_mult/comp_mult_inst/n134_s/COUT
7.436 0.000 tNET RR 2 u_complex_mult/comp_mult_inst/n133_s/CIN
7.486 0.050 tINS RR 1 u_complex_mult/comp_mult_inst/n133_s/COUT
7.486 0.000 tNET RR 2 u_complex_mult/comp_mult_inst/n132_s/CIN
7.536 0.050 tINS RR 1 u_complex_mult/comp_mult_inst/n132_s/COUT
7.536 0.000 tNET RR 2 u_complex_mult/comp_mult_inst/n131_s/CIN
7.779 0.244 tINS RR 1 u_complex_mult/comp_mult_inst/n131_s/SUM
8.154 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 286 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/realo_14_s0/CLK
10.311 -0.064 tSu 1 u_complex_mult/comp_mult_inst/realo_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 4.264, 54.816%; route: 1.500, 19.282%; tC2Q: 2.015, 25.902%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%