#Build: Synplify Pro (R) O-2018.09G-Beta1, Build 019R, Sep 3 2018 #install: D:\Gowin\1.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: GW-SW-042 # Fri Sep 28 14:04:54 2018 #Implementation: rev_1 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys HDL Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Verilog Compiler, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @N:CG1350 : | Running Verilog Compiler in Multiple File Compilation Unit mode @I::"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v" (library work) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\gw_ao_parameter.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\gw_ao_top_define.v" (library work) @I::"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\gw_ao_expression.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_define.v" (library work) @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v" (library work) @W:CG1337 : gw_ao_match.v(109) | Net match_m0_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(110) | Net match_m1_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(111) | Net match_m2_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(112) | Net match_ctl_en_reg_wr is not declared. @W:CG1337 : gw_ao_match.v(113) | Net match_cnt_reg_wr is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v" (library work) @W:CG1337 : gw_ao_mem_ctrl.v(122) | Net capture_length_zero is not declared. @I::"D:\Gowin\1.8\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v" (library work) @W:CG1337 : gw_ao_top.v(500) | Net start_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(503) | Net trig_level_max_reg_wr is not declared. @W:CG1337 : gw_ao_top.v(504) | Net capture_mem_addr_max_wr is not declared. @W:CG1337 : gw_ao_top.v(505) | Net capture_mem_addr_rem_wr is not declared. @W:CG1337 : gw_ao_top.v(506) | Net capture_windows_num_wr is not declared. @W:CG1337 : gw_ao_top.v(1717) | Net match_en_0 is not declared. @W:CG1337 : gw_ao_top.v(1718) | Net match_en_1 is not declared. @W:CG1337 : gw_ao_top.v(1719) | Net match_en_2 is not declared. @W:CG1337 : gw_ao_top.v(1720) | Net match_en_3 is not declared. @W:CG1337 : gw_ao_top.v(1721) | Net match_en_4 is not declared. @W:CG1337 : gw_ao_top.v(1722) | Net match_en_5 is not declared. @W:CG1337 : gw_ao_top.v(1723) | Net match_en_6 is not declared. @W:CG1337 : gw_ao_top.v(1724) | Net match_en_7 is not declared. @W:CG1337 : gw_ao_top.v(1725) | Net match_en_8 is not declared. @W:CG1337 : gw_ao_top.v(1726) | Net match_en_9 is not declared. @W:CG1337 : gw_ao_top.v(1727) | Net match_en_10 is not declared. @W:CG1337 : gw_ao_top.v(1728) | Net match_en_11 is not declared. @W:CG1337 : gw_ao_top.v(1729) | Net match_en_12 is not declared. @W:CG1337 : gw_ao_top.v(1730) | Net match_en_13 is not declared. @W:CG1337 : gw_ao_top.v(1731) | Net match_en_14 is not declared. @W:CG1337 : gw_ao_top.v(1732) | Net match_en_15 is not declared. @W:CG1337 : gw_ao_top.v(2213) | Net stop_reg is not declared. Verilog syntax check successful! @N:CG364 : gw_ao_parameter.v(1) | Synthesizing module work_E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\gw_ao_parameter.v_unit in library work. Selecting top level module ao_top_0 Running optimization stage 1 on ao_mem_ctrl_0_1024s_149s_10s ....... Running optimization stage 1 on ao_crc32_0 ....... Running optimization stage 1 on ao_match_0_0s_4s_149s_1_1_0_1_2_3_4 ....... Running optimization stage 1 on ao_top_0 ....... Running optimization stage 2 on ao_match_0_0s_4s_149s_1_1_0_1_2_3_4 ....... Running optimization stage 2 on ao_top_0 ....... Extracted state machine for register module_state State machine has 11 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1001 1010 1011 Running optimization stage 2 on ao_crc32_0 ....... Running optimization stage 2 on ao_mem_ctrl_0_1024s_149s_10s ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 94MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 14:04:55 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 14:04:55 2018 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 14:04:55 2018 ###########################################################] ###########################################################[ Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Database state : E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\rev_1\synwork\|rev_1 Synopsys Synopsys Netlist Linker, Version comp2018q3p1, Build 019R, Built Sep 3 2018 10:06:59 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Sep 28 14:04:57 2018 ###########################################################] Premap Report # Fri Sep 28 14:04:57 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. @N:MF284 : | Setting synthesis effort to medium for the design Linked File: ao_0_scck.rpt Printing clock summary report in "E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\rev_1\ao_0_scck.rpt" file @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB) @N:BN133 : | Ignoring syn_hier=hard property on top-level design. Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 115MB peak: 118MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MH105 : | UMR3 is only supported for HAPS-80. @N:MH105 : | UMR3 is only supported for HAPS-80. Beginning opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Finished opaque latch marking step (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Rerun analysis in 0 latches Finished opaque latch detection step 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) @N:MF974 : | Total number of latches (multibit) processed = 0 @N:MF975 : | Total number of latches (bit blasted) processed = 0 @N:MF976 : | Total number of (multibit) opaque latches found = 0 @N:MF977 : | Total number of (bit blasted) opaque latches found = 0 Finished opaque latch detection (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Detailed report for transparent and observable latches in design: Linked File: ao_0_prem_latch_transparency_report.log Encoding state machine module_state[10:0] (in view: work.ao_top_0(verilog)) original code -> new code 0000 -> 00000000001 0001 -> 00000000010 0010 -> 00000000100 0011 -> 00000001000 0100 -> 00000010000 0101 -> 00000100000 0110 -> 00001000000 0111 -> 00010000000 1001 -> 00100000000 1010 -> 01000000000 1011 -> 10000000000 Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB) Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB) Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 194MB peak: 194MB) syn_allowed_resources : blockrams=140 set on top level netlist ao_top_0 Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------- 0 - ao_top_0|control[0] 186.5 MHz 5.362 inferred Autoconstr_clkgroup_1 661 0 - ao_top_0|clk_i 224.1 MHz 4.461 inferred Autoconstr_clkgroup_0 343 ========================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------- ao_top_0|control[0] 661 control[0](port) data_register[169:0].C - - ao_top_0|clk_i 343 clk_i(port) internal_reg_force_triger_syn[1:0].C - clk_ao.I[0](keepbuf) ====================================================================================================================================== ICG Latch Removal Summary: Number of ICG latches removed: 0 Number of ICG latches not removed: 0 @S |Clock Optimization Summary #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ 2 non-gated/non-generated clock tree(s) driving 856 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks ============================= Non-Gated/Non-Generated Clocks ============================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------ ClockId_0_0 ENCRYPTED Unconstrained_port 195 ENCRYPTED ClockId_0_1 ENCRYPTED Unconstrained_io_port 661 ENCRYPTED ========================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ###### @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\rev_1\ao_0.sap. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 192MB peak: 194MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 194MB) None None Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 193MB peak: 195MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 109MB peak: 195MB) Process took 0h:00m:02s realtime, 0h:00m:01s cputime # Fri Sep 28 14:04:59 2018 ###########################################################] Map & Optimize Report # Fri Sep 28 14:05:00 2018 Copyright (C) 1994-2018 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: O-2018.09G-Beta1 Install: D:\Gowin\1.8\SynplifyPro OS: Windows 6.1 Hostname: GW-SW-042 Implementation : rev_1 Synopsys Generic Technology Mapper, Version mapgw, Build 1167R, Built Sep 4 2018 10:03:38 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF284 : | Setting synthesis effort to medium for the design @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF666 : | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 102MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 113MB peak: 115MB) @N:MF284 : | Setting synthesis effort to medium for the design Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 191MB peak: 193MB) Available hyper_sources - for debug and ip models None Found @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 195MB) Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 195MB peak: 198MB) Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 203MB peak: 204MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 200MB peak: 204MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 201MB peak: 204MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 201MB peak: 204MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 204MB) Finished preparing to map (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 200MB peak: 204MB) Finished technology mapping (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 218MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:04s -2.87ns 586 / 700 2 0h:00m:04s -2.45ns 589 / 700 3 0h:00m:04s -2.45ns 590 / 700 4 0h:00m:04s -2.45ns 589 / 700 5 0h:00m:04s -2.45ns 590 / 700 6 0h:00m:04s -2.45ns 589 / 700 Timing driven replication report Added 3 Registers via timing driven replication Added 3 LUTs via timing driven replication 7 0h:00m:05s -2.32ns 609 / 703 8 0h:00m:05s -2.45ns 611 / 703 9 0h:00m:05s -2.45ns 610 / 703 10 0h:00m:05s -2.32ns 611 / 703 11 0h:00m:05s -2.32ns 611 / 703 12 0h:00m:05s -2.32ns 612 / 703 13 0h:00m:05s -2.18ns 612 / 703 Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 218MB peak: 219MB) @N:FX164 : | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 218MB peak: 220MB) Start Writing Netlists (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 147MB peak: 221MB) Writing Analyst data base E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\temp\gao\ao_0\rev_1\synwork\ao_0_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 216MB peak: 221MB) Writing Verilog Simulation files Writing scf file... (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 218MB peak: 221MB) @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 216MB peak: 221MB) Start final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 216MB peak: 221MB) @W:MT420 : | Found inferred clock ao_top_0|clk_i with period 4.33ns. Please declare a user-defined clock on port clk_i. @W:MT420 : | Found inferred clock ao_top_0|control[0] with period 6.19ns. Please declare a user-defined clock on port control[0]. ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Sep 28 14:05:10 2018 # Top view: ao_top_0 Requested Frequency: 161.6 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.092 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------- ao_top_0|clk_i 231.0 MHz 196.3 MHz 4.329 5.093 -0.764 inferred Autoconstr_clkgroup_0 ao_top_0|control[0] 161.6 MHz 137.3 MHz 6.189 7.281 -1.092 inferred Autoconstr_clkgroup_1 System 150.0 MHz 223.2 MHz 6.667 4.480 2.187 system system_clkgroup ============================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise --------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack --------------------------------------------------------------------------------------------------------------------------------- System ao_top_0|clk_i | 4.329 2.187 | No paths - | No paths - | No paths - System ao_top_0|control[0] | 6.189 4.273 | No paths - | No paths - | No paths - ao_top_0|clk_i System | 4.329 3.490 | No paths - | No paths - | No paths - ao_top_0|clk_i ao_top_0|clk_i | 4.329 -0.764 | 4.329 3.490 | No paths - | 2.165 1.326 ao_top_0|clk_i ao_top_0|control[0] | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] System | 6.189 5.411 | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|clk_i | Diff grp - | No paths - | No paths - | No paths - ao_top_0|control[0] ao_top_0|control[0] | 6.189 -1.092 | No paths - | No paths - | No paths - ================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: ao_top_0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] ao_top_0|clk_i DFFC Q capture_length[0] 0.243 -0.764 u_ao_mem_ctrl.capture_length[1] ao_top_0|clk_i DFFC Q capture_length[1] 0.243 -0.729 u_ao_mem_ctrl.capture_length[2] ao_top_0|clk_i DFFC Q capture_length[2] 0.243 -0.694 u_ao_mem_ctrl.capture_length[3] ao_top_0|clk_i DFFP Q capture_length[3] 0.243 -0.659 internal_reg_force_triger_syn[1] ao_top_0|clk_i DFFC Q internal_reg_force_triger_syn[1] 0.243 -0.633 u_ao_mem_ctrl.capture_length[4] ao_top_0|clk_i DFFC Q capture_length[4] 0.243 -0.624 genblk1\.u_ao_match_0.match_sep ao_top_0|clk_i DFFC Q match 0.243 -0.612 u_ao_mem_ctrl.capture_length[5] ao_top_0|clk_i DFFC Q capture_length[5] 0.243 -0.589 u_ao_mem_ctrl.capture_length[6] ao_top_0|clk_i DFFC Q capture_length[6] 0.243 -0.554 triger_level_cnt[2] ao_top_0|clk_i DFFC Q triger_level_cnt[2] 0.243 -0.525 ================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.mem_addr_inc_en ao_top_0|clk_i DFFCE CE mem_addr_inc_en_RNO 4.268 -0.764 u_ao_mem_ctrl.capture_mem_wr ao_top_0|clk_i DFFCE CE capture_mem_wr_RNO 4.268 -0.633 u_ao_mem_ctrl.capture_loop ao_top_0|clk_i DFFCE CE un1_mem_addr_inc_en6 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[0] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[0] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[1] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[1] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[2] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[2] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[3] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[3] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[4] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[4] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[5] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[5] 4.268 -0.083 u_ao_mem_ctrl.capture_mem_addr[6] ao_top_0|clk_i DFFCE D capture_mem_addr_lm[6] 4.268 -0.083 ========================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.mem_addr_inc_en_RNO_2 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_2 LUT4 F Out 0.570 4.287 - g0_3_0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 I0 In - 4.287 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 O Out 0.105 4.392 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 I0 In - 4.392 - u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 O Out 0.105 4.497 - mem_addr_inc_en_RNO Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.mem_addr_inc_en_RNO_3 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_3 LUT4 F Out 0.570 4.287 - g0_3_0_1 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 I1 In - 4.287 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 O Out 0.105 4.392 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 I0 In - 4.392 - u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 O Out 0.105 4.497 - mem_addr_inc_en_RNO Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.mem_addr_inc_en_RNO_5 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_5 LUT4 F Out 0.570 4.287 - g0_3_1_1 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO_1 MUX2_LUT5 I1 In - 4.287 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_1 MUX2_LUT5 O Out 0.105 4.392 - g0_3_1 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 I1 In - 4.392 - u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 O Out 0.105 4.497 - mem_addr_inc_en_RNO Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 5.032 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.764 Number of logic level(s): 14 Starting point: u_ao_mem_ctrl.capture_length[0] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[0] DFFC Q Out 0.243 0.243 - capture_length[0] Net - - 0.535 - 4 u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_0_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_0 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.607 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.607 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.077 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.612 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.182 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.mem_addr_inc_en_RNO_4 LUT4 I1 In - 3.717 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_4 LUT4 F Out 0.570 4.287 - g0_3_1_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO_1 MUX2_LUT5 I0 In - 4.287 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_1 MUX2_LUT5 O Out 0.105 4.392 - g0_3_1 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 I1 In - 4.392 - u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 O Out 0.105 4.497 - mem_addr_inc_en_RNO Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 5.032 - =================================================================================================================== Total path delay (propagation time + setup) of 5.093 is 2.953(58.0%) logic and 2.140(42.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 4.997 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.729 Number of logic level(s): 13 Starting point: u_ao_mem_ctrl.capture_length[1] / Q Ending point: u_ao_mem_ctrl.mem_addr_inc_en / CE The start point is clocked by ao_top_0|clk_i [rising] on pin CLK The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_length[1] DFFC Q Out 0.243 0.243 - capture_length[1] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU I0 In - 0.778 - u_ao_mem_ctrl.capture_length_zero_cry_1_0 ALU COUT Out 0.549 1.327 - capture_length_zero_cry_1 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU CIN In - 1.327 - u_ao_mem_ctrl.capture_length_zero_cry_2_0 ALU COUT Out 0.035 1.362 - capture_length_zero_cry_2 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU CIN In - 1.362 - u_ao_mem_ctrl.capture_length_zero_cry_3_0 ALU COUT Out 0.035 1.397 - capture_length_zero_cry_3 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU CIN In - 1.397 - u_ao_mem_ctrl.capture_length_zero_cry_4_0 ALU COUT Out 0.035 1.432 - capture_length_zero_cry_4 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU CIN In - 1.432 - u_ao_mem_ctrl.capture_length_zero_cry_5_0 ALU COUT Out 0.035 1.467 - capture_length_zero_cry_5 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU CIN In - 1.467 - u_ao_mem_ctrl.capture_length_zero_cry_6_0 ALU COUT Out 0.035 1.502 - capture_length_zero_cry_6 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU CIN In - 1.502 - u_ao_mem_ctrl.capture_length_zero_cry_7_0 ALU COUT Out 0.035 1.537 - capture_length_zero_cry_7 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU CIN In - 1.537 - u_ao_mem_ctrl.capture_length_zero_cry_8_0 ALU COUT Out 0.035 1.572 - capture_length_zero_cry_8 Net - - 0.000 - 1 u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU CIN In - 1.572 - u_ao_mem_ctrl.capture_length_zero_s_9_0 ALU SUM Out 0.470 2.042 - capture_length_zero[9] Net - - 0.535 - 2 u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 I1 In - 2.577 - u_ao_mem_ctrl.capture_length_zero_s_9_0_RNIK79M LUT2 F Out 0.570 3.147 - g3_4_0 Net - - 0.535 - 4 u_ao_mem_ctrl.mem_addr_inc_en_RNO_2 LUT4 I1 In - 3.682 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_2 LUT4 F Out 0.570 4.252 - g0_3_0_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 I0 In - 4.252 - u_ao_mem_ctrl.mem_addr_inc_en_RNO_0 MUX2_LUT5 O Out 0.105 4.357 - g0_3_0 Net - - 0.000 - 1 u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 I0 In - 4.357 - u_ao_mem_ctrl.mem_addr_inc_en_RNO MUX2_LUT6 O Out 0.105 4.462 - mem_addr_inc_en_RNO Net - - 0.535 - 1 u_ao_mem_ctrl.mem_addr_inc_en DFFCE CE In - 4.997 - =================================================================================================================== Total path delay (propagation time + setup) of 5.058 is 2.918(57.7%) logic and 2.140(42.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: ao_top_0|control[0] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------ internal_register_select[15] ao_top_0|control[0] DFFCE Q internal_register_select[15] 0.243 -1.092 internal_register_select[14] ao_top_0|control[0] DFFCE Q internal_register_select[14] 0.243 -1.071 internal_register_select[9] ao_top_0|control[0] DFFCE Q internal_register_select[9] 0.243 -1.001 internal_register_select[7] ao_top_0|control[0] DFFCE Q internal_register_select[7] 0.243 -0.980 internal_register_select[10] ao_top_0|control[0] DFFCE Q internal_register_select[10] 0.243 -0.893 internal_register_select[11] ao_top_0|control[0] DFFCE Q internal_register_select[11] 0.243 -0.802 word_count[3] ao_top_0|control[0] DFFCE Q word_count[3] 0.243 -0.769 word_count[2] ao_top_0|control[0] DFFCE Q word_count[2] 0.243 -0.748 word_count[7] ao_top_0|control[0] DFFCE Q word_count[7] 0.243 -0.748 word_count[6] ao_top_0|control[0] DFFCE Q word_count[6] 0.243 -0.727 ============================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------- data_out_shift_reg[0] ao_top_0|control[0] DFFCE D data_out_shift_reg_4[0] 6.128 -1.092 address_counter[0] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[1] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[2] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[3] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[4] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[5] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[6] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[7] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 address_counter[8] ao_top_0|control[0] DFFCE CE addr_ct_en 6.128 -0.769 =================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.189 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.128 - Propagation time: 7.220 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.092 Number of logic level(s): 7 Starting point: internal_register_select[15] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- internal_register_select[15] DFFCE Q Out 0.243 0.243 - internal_register_select[15] Net - - 0.535 - 1 match_unit_rd_en_2_3[0] LUT2 I1 In - 0.778 - match_unit_rd_en_2_3[0] LUT2 F Out 0.570 1.348 - match_unit_rd_en_2_3[0] Net - - 0.401 - 1 match_unit_rd_en_2[0] LUT4 I2 In - 1.749 - match_unit_rd_en_2[0] LUT4 F Out 0.462 2.211 - internal_reg_start_m_14 Net - - 0.596 - 12 data_from_internal_reg99 LUT3 I2 In - 2.807 - data_from_internal_reg99 LUT3 F Out 0.462 3.269 - data_from_internal_reg99 Net - - 0.596 - 16 data_from_ao_reg_3[0] LUT4 I2 In - 3.865 - data_from_ao_reg_3[0] LUT4 F Out 0.462 4.327 - data_from_ao_reg_3[0] Net - - 0.401 - 1 data_from_ao_reg_5[0] LUT4 I0 In - 4.728 - data_from_ao_reg_5[0] LUT4 F Out 0.549 5.277 - data_from_ao_reg_5[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 5.679 - data_from_ao_reg_6[0] LUT4 F Out 0.570 6.249 - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I1 In - 6.650 - data_out_shift_reg_4[0] LUT4 F Out 0.570 7.220 - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 7.220 - ============================================================================================ Total path delay (propagation time + setup) of 7.281 is 3.949(54.2%) logic and 3.332(45.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 6.189 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.128 - Propagation time: 7.199 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.071 Number of logic level(s): 7 Starting point: internal_register_select[14] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- internal_register_select[14] DFFCE Q Out 0.243 0.243 - internal_register_select[14] Net - - 0.535 - 1 match_unit_rd_en_2_3[0] LUT2 I0 In - 0.778 - match_unit_rd_en_2_3[0] LUT2 F Out 0.549 1.327 - match_unit_rd_en_2_3[0] Net - - 0.401 - 1 match_unit_rd_en_2[0] LUT4 I2 In - 1.728 - match_unit_rd_en_2[0] LUT4 F Out 0.462 2.190 - internal_reg_start_m_14 Net - - 0.596 - 12 data_from_internal_reg99 LUT3 I2 In - 2.786 - data_from_internal_reg99 LUT3 F Out 0.462 3.248 - data_from_internal_reg99 Net - - 0.596 - 16 data_from_ao_reg_3[0] LUT4 I2 In - 3.844 - data_from_ao_reg_3[0] LUT4 F Out 0.462 4.306 - data_from_ao_reg_3[0] Net - - 0.401 - 1 data_from_ao_reg_5[0] LUT4 I0 In - 4.707 - data_from_ao_reg_5[0] LUT4 F Out 0.549 5.256 - data_from_ao_reg_5[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 5.658 - data_from_ao_reg_6[0] LUT4 F Out 0.570 6.228 - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I1 In - 6.629 - data_out_shift_reg_4[0] LUT4 F Out 0.570 7.199 - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 7.199 - ============================================================================================ Total path delay (propagation time + setup) of 7.260 is 3.928(54.1%) logic and 3.332(45.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 6.189 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.128 - Propagation time: 7.129 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.001 Number of logic level(s): 7 Starting point: internal_register_select[9] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- internal_register_select[9] DFFCE Q Out 0.243 0.243 - internal_register_select[9] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I1 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.570 1.348 - match_unit_rd_en_2_4[0] Net - - 0.401 - 1 match_unit_rd_en_2[0] LUT4 I3 In - 1.749 - match_unit_rd_en_2[0] LUT4 F Out 0.371 2.120 - internal_reg_start_m_14 Net - - 0.596 - 12 data_from_internal_reg99 LUT3 I2 In - 2.716 - data_from_internal_reg99 LUT3 F Out 0.462 3.178 - data_from_internal_reg99 Net - - 0.596 - 16 data_from_ao_reg_3[0] LUT4 I2 In - 3.774 - data_from_ao_reg_3[0] LUT4 F Out 0.462 4.236 - data_from_ao_reg_3[0] Net - - 0.401 - 1 data_from_ao_reg_5[0] LUT4 I0 In - 4.637 - data_from_ao_reg_5[0] LUT4 F Out 0.549 5.186 - data_from_ao_reg_5[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 5.588 - data_from_ao_reg_6[0] LUT4 F Out 0.570 6.158 - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I1 In - 6.559 - data_out_shift_reg_4[0] LUT4 F Out 0.570 7.129 - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 7.129 - =========================================================================================== Total path delay (propagation time + setup) of 7.190 is 3.858(53.7%) logic and 3.332(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 6.189 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.128 - Propagation time: 7.129 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.001 Number of logic level(s): 7 Starting point: internal_register_select[15] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------- internal_register_select[15] DFFCE Q Out 0.243 0.243 - internal_register_select[15] Net - - 0.535 - 1 match_unit_rd_en_2_3[0] LUT2 I1 In - 0.778 - match_unit_rd_en_2_3[0] LUT2 F Out 0.570 1.348 - match_unit_rd_en_2_3[0] Net - - 0.401 - 1 match_unit_rd_en_2[0] LUT4 I2 In - 1.749 - match_unit_rd_en_2[0] LUT4 F Out 0.462 2.211 - internal_reg_start_m_14 Net - - 0.596 - 12 data_from_internal_reg100 LUT3 I2 In - 2.807 - data_from_internal_reg100 LUT3 F Out 0.462 3.269 - data_from_internal_reg100 Net - - 0.596 - 16 data_from_ao_reg_3[0] LUT4 I3 In - 3.865 - data_from_ao_reg_3[0] LUT4 F Out 0.371 4.236 - data_from_ao_reg_3[0] Net - - 0.401 - 1 data_from_ao_reg_5[0] LUT4 I0 In - 4.637 - data_from_ao_reg_5[0] LUT4 F Out 0.549 5.186 - data_from_ao_reg_5[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 5.588 - data_from_ao_reg_6[0] LUT4 F Out 0.570 6.158 - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I1 In - 6.559 - data_out_shift_reg_4[0] LUT4 F Out 0.570 7.129 - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 7.129 - ============================================================================================ Total path delay (propagation time + setup) of 7.190 is 3.858(53.7%) logic and 3.332(46.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 6.189 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.128 - Propagation time: 7.108 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.980 Number of logic level(s): 7 Starting point: internal_register_select[7] / Q Ending point: data_out_shift_reg[0] / D The start point is clocked by ao_top_0|control[0] [rising] on pin CLK The end point is clocked by ao_top_0|control[0] [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------- internal_register_select[7] DFFCE Q Out 0.243 0.243 - internal_register_select[7] Net - - 0.535 - 1 match_unit_rd_en_2_4[0] LUT4 I0 In - 0.778 - match_unit_rd_en_2_4[0] LUT4 F Out 0.549 1.327 - match_unit_rd_en_2_4[0] Net - - 0.401 - 1 match_unit_rd_en_2[0] LUT4 I3 In - 1.728 - match_unit_rd_en_2[0] LUT4 F Out 0.371 2.099 - internal_reg_start_m_14 Net - - 0.596 - 12 data_from_internal_reg99 LUT3 I2 In - 2.695 - data_from_internal_reg99 LUT3 F Out 0.462 3.157 - data_from_internal_reg99 Net - - 0.596 - 16 data_from_ao_reg_3[0] LUT4 I2 In - 3.753 - data_from_ao_reg_3[0] LUT4 F Out 0.462 4.215 - data_from_ao_reg_3[0] Net - - 0.401 - 1 data_from_ao_reg_5[0] LUT4 I0 In - 4.616 - data_from_ao_reg_5[0] LUT4 F Out 0.549 5.165 - data_from_ao_reg_5[0] Net - - 0.401 - 1 data_from_ao_reg_6[0] LUT4 I1 In - 5.567 - data_from_ao_reg_6[0] LUT4 F Out 0.570 6.137 - data_from_ao_reg_6[0] Net - - 0.401 - 1 data_out_shift_reg_4[0] LUT4 I1 In - 6.538 - data_out_shift_reg_4[0] LUT4 F Out 0.570 7.108 - data_out_shift_reg_4[0] Net - - 0.000 - 1 data_out_shift_reg[0] DFFCE D In - 7.108 - =========================================================================================== Total path delay (propagation time + setup) of 7.169 is 3.837(53.5%) logic and 3.332(46.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 System INV O capture_end 0.000 2.187 address_counter_cry_0_RNO[0] System INV O address_counter 0.000 4.273 ============================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------- capture_window_sel[2] System DFFC D capture_window_sel_3[2] 4.268 2.187 capture_window_sel[3] System DFFC D capture_window_sel_3[3] 4.268 2.187 capture_window_sel[1] System DFFC D capture_window_sel_3[1] 4.268 2.412 capture_window_sel[0] System DFFC D capture_window_sel_3[0] 4.268 3.184 internal_reg_start_dly[0] System DFFC D internal_reg_start_dly_2[0] 4.268 3.184 capture_end_dly System DFFP D capture_end 4.268 3.733 address_counter[9] System DFFCE D address_counter_s[9] 6.128 4.273 address_counter[8] System DFFCE D address_counter_s[8] 6.128 4.308 address_counter[7] System DFFCE D address_counter_s[7] 6.128 4.343 address_counter[6] System DFFCE D address_counter_s[6] 6.128 4.378 ================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.329 - Setup time: 0.061 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.268 - Propagation time: 2.081 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.187 Number of logic level(s): 2 Starting point: u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 / O Ending point: capture_window_sel[2] / D The start point is clocked by System [rising] The end point is clocked by ao_top_0|clk_i [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------- u_ao_mem_ctrl.capture_mem_wr_RNIQKR6 INV O Out 0.000 0.000 - capture_end Net - - 0.535 - 6 un1_capture_window_sel_ac0_1 LUT4 I0 In - 0.535 - un1_capture_window_sel_ac0_1 LUT4 F Out 0.549 1.084 - un1_capture_window_sel_c2 Net - - 0.535 - 2 capture_window_sel_3[2] LUT3 I2 In - 1.619 - capture_window_sel_3[2] LUT3 F Out 0.462 2.081 - capture_window_sel_3[2] Net - - 0.000 - 1 capture_window_sel[2] DFFC D In - 2.081 - =================================================================================================== Total path delay (propagation time + setup) of 2.142 is 1.072(50.0%) logic and 1.070(50.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 216MB peak: 221MB) Finished timing report (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 216MB peak: 221MB) --------------------------------------- Resource Usage Report for ao_top_0 Mapping to part: gw2a_55pbga484-8 Cell usage: ALU 72 uses DFF 148 uses DFFC 60 uses DFFCE 456 uses DFFNP 2 uses DFFP 5 uses DFFPE 32 uses GSR 1 use INV 2 uses MUX2_LUT5 6 uses MUX2_LUT6 2 uses SDPX9 9 uses LUT2 55 uses LUT3 118 uses LUT4 389 uses I/O ports: 163 I/O primitives: 163 IBUF 161 uses OBUF 2 uses I/O Register bits: 0 Register bits not including I/Os: 703 of 41040 (1%) RAM/ROM usage summary Block Rams : 9 of 140 (6%) Total load per clock: ao_top_0|clk_i: 1 ao_top_0|control[0]: 518 @S |Mapping Summary: Total LUTs: 562 (1%) Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 48MB peak: 221MB) Process took 0h:00m:10s realtime, 0h:00m:09s cputime # Fri Sep 28 14:05:10 2018 ###########################################################]