@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
@N: CG364 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\Complex_Multiplier\Complex_Multiplier.v":149:7:149:24|Synthesizing module complex_multiplier in library work.
@N: CG364 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":2:7:2:9|Synthesizing module top in library work.
@N: CG179 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":32:13:32:15|Removing redundant assignment.
@N: CG179 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":61:11:61:12|Removing redundant assignment.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[15] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[14] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[13] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[12] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[11] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[10] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[9] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[8] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[7] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[6] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[5] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[4] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[3] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":37:0:37:5|Register bit mimago[2] is always 0.
@N: CL189 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":84:0:84:5|Register bit nimago[2] is always 0.
@N|Running in 64-bit mode
@N: NF107 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":2:7:2:9|Selected library: work cell: top view verilog as top level
@N: NF107 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v":2:7:2:9|Selected library: work cell: top view verilog as top level

