Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\gwsynthesis\cmult_18.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\cmult_18.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\cmult_18.sdc
Tool Version	V1.9.11.02 (64-bit)
Part Number	GW5A-LV25UG324ES
Device	GW5A-25
Device Version	A
Created Time	Tue Jun 10 16:11:31 2025
Legal Announcement	Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.855V 0C ES
Hold Delay Model	Fast 0.945V 85C ES
Numbers of Paths Analyzed	2414
Numbers of Endpoints Analyzed	3435
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
1	clk1	Base	20.000	50.000	0.000	10.000			clk
2	clk2	Base	50.000	20.000	0.000	5.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk1	50.000(MHz)	88.761(MHz)	2	TOP
2	clk2	20.000(MHz)	125.092(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
clk1	Setup	0.000	0
clk1	Hold	0.000	0
clk2	Setup	0.000	0
clk2	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.734	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[26]	clk1:[R]	clk1:[R]	20.000	-0.002	7.801
2	8.774	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[24]	clk1:[R]	clk1:[R]	20.000	-0.002	7.979
3	9.198	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[25]	clk1:[R]	clk1:[R]	20.000	-0.002	7.672
4	9.205	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[29]	clk1:[R]	clk1:[R]	20.000	-0.002	7.292
5	9.228	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[29]	clk1:[R]	clk1:[R]	20.000	-0.002	7.274
6	9.271	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[26]	clk1:[R]	clk1:[R]	20.000	-0.002	7.264
7	9.418	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[24]	clk1:[R]	clk1:[R]	20.000	-0.002	7.335
8	9.734	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[25]	clk1:[R]	clk1:[R]	20.000	-0.002	7.136
9	9.738	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[28]	clk1:[R]	clk1:[R]	20.000	-0.002	7.348
10	9.738	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[28]	clk1:[R]	clk1:[R]	20.000	-0.002	7.348
11	9.801	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[27]	clk1:[R]	clk1:[R]	20.000	-0.002	7.180
12	10.044	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[27]	clk1:[R]	clk1:[R]	20.000	-0.002	6.935
13	10.221	memreal1_memreal1_0_0_s/DO[0]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[3]	clk1:[R]	clk1:[R]	20.000	0.008	6.043
14	10.327	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[4]	clk1:[R]	clk1:[R]	20.000	-0.002	5.959
15	10.389	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[39]	clk1:[R]	clk1:[R]	20.000	-0.002	7.970
16	10.462	memreal1_memreal1_0_0_s/DO[0]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[2]	clk1:[R]	clk1:[R]	20.000	0.008	5.819
17	10.500	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[6]	clk1:[R]	clk1:[R]	20.000	-0.002	6.371
18	10.555	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[5]	clk1:[R]	clk1:[R]	20.000	-0.002	5.648
19	10.555	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[5]	clk1:[R]	clk1:[R]	20.000	-0.002	5.648
20	10.556	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[22]	clk1:[R]	clk1:[R]	20.000	-0.002	7.311
21	10.567	memreal1_memreal1_0_0_s/DO[0]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[1]	clk1:[R]	clk1:[R]	20.000	0.008	5.703
22	10.589	memreal1_memreal1_0_0_s/DO[0]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[0]	clk1:[R]	clk1:[R]	20.000	0.008	5.650
23	10.597	memimag1_memimag1_0_0_s/DO[14]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[20]	clk1:[R]	clk1:[R]	20.000	-0.002	7.443
24	10.733	memreal1_memreal1_0_0_s/DO[0]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[3]	clk1:[R]	clk1:[R]	20.000	0.008	5.530
25	10.735	memimag1_memimag1_0_0_s/DO[8]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[16]	clk1:[R]	clk1:[R]	20.000	-0.002	6.723

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.214	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[13]	clk2:[R]	clk2:[R]	0.000	0.005	0.244
2	0.217	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[12]	clk2:[R]	clk2:[R]	0.000	0.005	0.247
3	0.229	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[0]	clk1:[R]	clk1:[R]	0.000	0.021	0.245
4	0.233	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[17]	clk1:[R]	clk1:[R]	0.000	0.025	0.245
5	0.251	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]	clk1:[R]	clk1:[R]	0.000	0.009	0.279
6	0.257	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_83_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[11]	clk1:[R]	clk1:[R]	0.000	0.009	0.285
7	0.268	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[4]	clk2:[R]	clk2:[R]	0.000	0.010	0.293
8	0.275	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/D	clk1:[R]	clk1:[R]	0.000	0.000	0.222
9	0.275	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
10	0.275	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.300
11	0.278	gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_0_s1/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
12	0.278	gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_1_s1/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
13	0.278	ad_6_s0/Q	ad_6_s0/D	clk1:[R]	clk1:[R]	0.000	0.000	0.303
14	0.278	gw_gao_inst_0/u_la0_top/word_count_2_s0/Q	gw_gao_inst_0/u_la0_top/word_count_2_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
15	0.278	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q	gw_gao_inst_0/u_la0_top/word_count_13_s0/D	clk2:[R]	clk2:[R]	0.000	0.000	0.303
16	0.281	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.306
17	0.281	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D	clk1:[R]	clk1:[R]	0.000	0.000	0.306
18	0.287	ad_4_s0/Q	ad_4_s0/D	clk1:[R]	clk1:[R]	0.000	0.000	0.312
19	0.290	ad_3_s0/Q	ad_3_s0/D	clk1:[R]	clk1:[R]	0.000	0.000	0.315
20	0.291	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[2]	clk1:[R]	clk1:[R]	0.000	0.010	0.318
21	0.298	ad_5_s0/Q	memreal1_memreal1_0_0_s/AD[10]	clk1:[R]	clk1:[R]	0.000	-0.005	0.338
22	0.303	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADA[9]	clk1:[R]	clk1:[R]	0.000	0.000	0.339
23	0.303	ad_6_s0/Q	memreal1_memreal1_0_0_s/AD[11]	clk1:[R]	clk1:[R]	0.000	-0.005	0.345
24	0.304	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[1]	clk1:[R]	clk1:[R]	0.000	-0.014	0.355
25	0.305	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_84_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[12]	clk1:[R]	clk1:[R]	0.000	0.009	0.333

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	6.661	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET	clk1:[F]	clk1:[R]	10.000	-0.025	3.016
2	6.661	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.025	3.016
3	6.664	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.028	3.016
4	6.664	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.028	3.016
5	6.879	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.033	2.806
6	7.074	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.035	2.614
7	7.076	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.038	2.614
8	7.076	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.038	2.614
9	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
10	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
11	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
12	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
13	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
14	7.115	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	-0.001	2.539
15	7.123	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.008	2.521
16	7.123	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.008	2.521
17	7.134	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.518
18	7.134	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.518
19	7.148	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.020	2.484
20	7.148	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.020	2.484
21	7.312	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.338
22	7.312	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.338
23	7.312	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.338
24	7.312	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.002	2.338
25	7.327	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR	clk1:[F]	clk1:[R]	10.000	0.001	2.325

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	10.480	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.414
2	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
3	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
4	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
5	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
6	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
7	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
8	10.582	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.013	0.516
9	10.586	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.017	0.516
10	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
11	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
12	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
13	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
14	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
15	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.626
16	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.021	0.614
17	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.021	0.614
18	10.688	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.021	0.614
19	10.780	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.017	0.710
20	10.923	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.869
21	10.923	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.001	0.869
22	11.021	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.005	0.963
23	11.025	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.963
24	11.025	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR	clk1:[F]	clk1:[R]	-10.000	0.009	0.963
25	11.025	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET	clk1:[F]	clk1:[R]	-10.000	0.009	0.963

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	2.453	3.453	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
2	2.453	3.453	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
3	2.453	3.453	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s
4	2.458	3.458	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
5	2.458	3.458	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s
6	2.458	3.458	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
7	2.458	3.458	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s
8	2.464	3.464	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
9	2.464	3.464	1.000	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s
10	3.193	3.443	0.250	High Pulse Width	clk2	gw_gao_inst_0/u_la0_top/data_register_142_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.734
Data Arrival Time	10.415
Data Required Time	19.149
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.092	3.624	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[26]
10.415	1.324	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.149	-3.466	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.624, 46.452%; route: 2.163, 27.719%; tC2Q: 2.015, 25.829%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path2

Path Summary:

Slack	8.774
Data Arrival Time	10.593
Data Required Time	19.367
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.240	3.908	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[24]
10.593	1.352	tNET	FF	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[24]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.367	-3.249	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.908, 48.974%; route: 2.056, 25.771%; tC2Q: 2.015, 25.254%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path3

Path Summary:

Slack	9.198
Data Arrival Time	10.286
Data Required Time	19.484
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.124	3.791	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[25]
10.286	1.163	tNET	FF	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.484	-3.132	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.791, 49.411%; route: 1.866, 24.325%; tC2Q: 2.015, 26.264%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path4

Path Summary:

Slack	9.205
Data Arrival Time	9.906
Data Required Time	19.111
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.284	3.951	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[29]
9.906	0.623	tNET	FF	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.111	-3.505	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.951, 54.179%; route: 1.326, 18.188%; tC2Q: 2.015, 27.633%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path5

Path Summary:

Slack	9.228
Data Arrival Time	9.888
Data Required Time	19.116
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.205	3.737	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[29]
9.888	0.682	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[29]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.116	-3.500	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.737, 51.382%; route: 1.521, 20.915%; tC2Q: 2.015, 27.703%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path6

Path Summary:

Slack	9.271
Data Arrival Time	9.878
Data Required Time	19.149
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.092	3.624	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[26]
9.878	0.786	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[26]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.149	-3.466	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.624, 49.889%; route: 1.625, 22.371%; tC2Q: 2.015, 27.740%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path7

Path Summary:

Slack	9.418
Data Arrival Time	9.949
Data Required Time	19.367
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.240	3.908	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[24]
9.949	0.709	tNET	FF	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[24]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.367	-3.249	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.908, 53.272%; route: 1.412, 19.257%; tC2Q: 2.015, 27.471%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path8

Path Summary:

Slack	9.734
Data Arrival Time	9.750
Data Required Time	19.484
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.124	3.791	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[25]
9.750	0.626	tNET	FF	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[25]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.484	-3.132	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.791, 53.124%; route: 1.330, 18.638%; tC2Q: 2.015, 28.238%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path9

Path Summary:

Slack	9.738
Data Arrival Time	9.962
Data Required Time	19.701
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.176	3.708	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[28]
9.962	0.786	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.701	-2.915	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.708, 50.463%; route: 1.625, 22.115%; tC2Q: 2.015, 27.422%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path10

Path Summary:

Slack	9.738
Data Arrival Time	9.962
Data Required Time	19.701
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.176	3.708	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[28]
9.962	0.786	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[28]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.701	-2.915	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.708, 50.463%; route: 1.625, 22.115%; tC2Q: 2.015, 27.422%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path11

Path Summary:

Slack	9.801
Data Arrival Time	9.794
Data Required Time	19.594
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
9.090	3.622	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[27]
9.794	0.704	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.594	-3.021	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.622, 50.449%; route: 1.542, 21.485%; tC2Q: 2.015, 28.066%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path12

Path Summary:

Slack	10.044
Data Arrival Time	9.549
Data Required Time	19.592
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.156	3.823	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[27]
9.549	0.393	tNET	FF	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[27]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
19.592	-3.023	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.823, 55.134%; route: 1.096, 15.809%; tC2Q: 2.015, 29.058%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path13

Path Summary:

Slack	10.221
Data Arrival Time	8.666
Data Required Time	18.886
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	36	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
4.638	2.015	tC2Q	RR	2	BSRAM_R10[17]	memreal1_memreal1_0_0_s/DO[0]
5.531	0.892	tNET	RR	97	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/A[0]
7.633	2.103	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[3]
8.666	1.033	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.886	-3.729	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 2.103, 34.796%; route: 1.925, 31.857%; tC2Q: 2.015, 33.347%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path14

Path Summary:

Slack	10.327
Data Arrival Time	8.573
Data Required Time	18.900
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
7.700	2.232	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[4]
8.573	0.873	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.900	-3.716	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.232, 37.464%; route: 1.711, 28.719%; tC2Q: 2.015, 33.817%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path15

Path Summary:

Slack	10.389
Data Arrival Time	10.584
Data Required Time	20.973
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
9.499	4.166	tINS	RR	24	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[36]
10.584	1.085	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[39]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
20.973	-1.643	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 4.166, 52.271%; route: 1.789, 22.445%; tC2Q: 2.015, 25.284%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path16

Path Summary:

Slack	10.462
Data Arrival Time	8.442
Data Required Time	18.904
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	36	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
4.638	2.015	tC2Q	RR	2	BSRAM_R10[17]	memreal1_memreal1_0_0_s/DO[0]
5.531	0.892	tNET	RR	97	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/A[0]
7.580	2.049	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[2]
8.442	0.863	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.904	-3.712	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 2.049, 35.211%; route: 1.755, 30.160%; tC2Q: 2.015, 34.629%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path17

Path Summary:

Slack	10.500
Data Arrival Time	8.985
Data Required Time	19.485
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
7.848	2.380	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[6]
8.985	1.138	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[6]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
19.485	-3.130	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.380, 37.354%; route: 1.976, 31.019%; tC2Q: 2.015, 31.627%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path18

Path Summary:

Slack	10.555
Data Arrival Time	8.262
Data Required Time	18.817
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
7.780	2.312	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[5]
8.262	0.482	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
18.817	-3.798	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.312, 40.934%; route: 1.321, 23.392%; tC2Q: 2.015, 35.674%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path19

Path Summary:

Slack	10.555
Data Arrival Time	8.262
Data Required Time	18.817
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
7.780	2.312	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[5]
8.262	0.482	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.817	-3.798	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 2.312, 40.934%; route: 1.321, 23.392%; tC2Q: 2.015, 35.674%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path20

Path Summary:

Slack	10.556
Data Arrival Time	9.925
Data Required Time	20.482
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
8.873	3.405	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[22]
9.925	1.053	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[22]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
20.482	-2.134	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.405, 46.573%; route: 1.891, 25.867%; tC2Q: 2.015, 27.560%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path21

Path Summary:

Slack	10.567
Data Arrival Time	8.327
Data Required Time	18.894
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	36	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
4.638	2.015	tC2Q	RR	2	BSRAM_R10[17]	memreal1_memreal1_0_0_s/DO[0]
5.531	0.892	tNET	RR	97	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/A[0]
7.429	1.898	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[1]
8.327	0.898	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.894	-3.722	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 1.898, 33.283%; route: 1.790, 31.386%; tC2Q: 2.015, 35.331%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path22

Path Summary:

Slack	10.589
Data Arrival Time	8.274
Data Required Time	18.863
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	36	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
4.638	2.015	tC2Q	RR	2	BSRAM_R10[17]	memreal1_memreal1_0_0_s/DO[0]
5.531	0.892	tNET	RR	97	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/A[0]
7.381	1.850	tINS	RF	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[0]
8.274	0.893	tNET	FF	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/C[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
18.863	-3.753	tSu		1	DSP_R19[18]	u_complex_mult/comp_mult_inst/prod2_36_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 1.850, 32.748%; route: 1.785, 31.591%; tC2Q: 2.015, 35.661%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path23

Path Summary:

Slack	10.597
Data Arrival Time	10.057
Data Required Time	20.653
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[14]
5.468	0.839	tNET	RR	94	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[14]
8.843	3.375	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[20]
10.057	1.214	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[20]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
20.653	-1.962	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.375, 45.350%; route: 2.053, 27.577%; tC2Q: 2.015, 27.073%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path24

Path Summary:

Slack	10.733
Data Arrival Time	8.153
Data Required Time	18.886
From	memreal1_memreal1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.623	1.941	tNET	RR	36	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
4.638	2.015	tC2Q	RR	2	BSRAM_R10[17]	memreal1_memreal1_0_0_s/DO[0]
5.531	0.892	tNET	RR	97	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/A[0]
7.633	2.103	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[3]
8.153	0.520	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
18.886	-3.729	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	-0.008
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.015%; route: 1.941, 73.985%
Arrival Data Path Delay	cell: 2.103, 38.020%; route: 1.412, 25.542%; tC2Q: 2.015, 36.437%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Path25

Path Summary:

Slack	10.735
Data Arrival Time	9.337
Data Required Time	20.071
From	memimag1_memimag1_0_0_s
To	u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
2.614	1.932	tNET	RR	36	BSRAM_R10[18]	memimag1_memimag1_0_0_s/CLK
4.629	2.015	tC2Q	RR	2	BSRAM_R10[18]	memimag1_memimag1_0_0_s/DO[8]
5.333	0.704	tNET	RR	90	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
8.620	3.288	tINS	RR	2	DSP_R19[19]	u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[16]
9.337	0.716	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/C[16]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.616	1.933	tNET	RR	1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
20.071	-2.544	tSu		1	DSP_R19[20]	u_complex_mult/comp_mult_inst/prod3_36_s0

Path Statistics:

Clock Skew	0.002
Setup Relationship	20.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.683, 26.109%; route: 1.932, 73.891%
Arrival Data Path Delay	cell: 3.288, 48.904%; route: 1.420, 21.123%; tC2Q: 2.015, 29.973%
Required Clock Path Delay	cell: 0.683, 26.093%; route: 1.933, 73.907%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.214
Data Arrival Time	2.662
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_9_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/CLK
2.559	0.141	tC2Q	RF	10	R27C63[0][A]	gw_gao_inst_0/u_la0_top/address_counter_9_s0/Q
2.662	0.103	tNET	FF	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[13]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.103, 42.213%; tC2Q: 0.141, 57.787%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path2

Path Summary:

Slack	0.217
Data Arrival Time	2.665
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.418	1.067	tNET	RR	1	R27C63[0][B]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/CLK
2.559	0.141	tC2Q	RF	11	R27C63[0][B]	gw_gao_inst_0/u_la0_top/address_counter_8_s0/Q
2.665	0.106	tNET	FF	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.873%; route: 1.067, 44.127%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.106, 42.915%; tC2Q: 0.141, 57.085%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path3

Path Summary:

Slack	0.229
Data Arrival Time	1.640
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.395	0.720	tNET	RR	1	R24C61[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/CLK
1.539	0.144	tC2Q	RR	1	R24C61[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_90_s0/Q
1.640	0.101	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.021
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.414%; route: 0.720, 51.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path4

Path Summary:

Slack	0.233
Data Arrival Time	1.640
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.395	0.720	tNET	RR	1	R24C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/CLK
1.539	0.144	tC2Q	RR	1	R24C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_89_s0/Q
1.640	0.101	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[17]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	-0.025
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.414%; route: 0.720, 51.586%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.101, 41.224%; tC2Q: 0.144, 58.776%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path5

Path Summary:

Slack	0.251
Data Arrival Time	1.658
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C60[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_77_s0/Q
1.658	0.135	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.135, 48.387%; tC2Q: 0.144, 51.613%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path6

Path Summary:

Slack	0.257
Data Arrival Time	1.664
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_83_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C58[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_83_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C58[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_83_s0/Q
1.664	0.141	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.141, 49.474%; tC2Q: 0.144, 50.526%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path7

Path Summary:

Slack	0.268
Data Arrival Time	2.716
Data Required Time	2.448
From	gw_gao_inst_0/u_la0_top/address_counter_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.423	1.072	tNET	RR	1	R26C63[1][B]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/CLK
2.567	0.144	tC2Q	RR	14	R26C63[1][B]	gw_gao_inst_0/u_la0_top/address_counter_0_s0/Q
2.716	0.149	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADB[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.413	1.062	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB
2.448	0.035	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 1.351, 55.757%; route: 1.072, 44.243%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.149, 50.853%; tC2Q: 0.144, 49.147%
Required Clock Path Delay	cell: 1.351, 55.988%; route: 1.062, 44.012%

Path8

Path Summary:

Slack	0.275
Data Arrival Time	1.596
Data Required Time	1.321
From	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R16C64[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
1.518	0.144	tC2Q	RR	1	R16C64[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/Q
1.596	0.078	tNET	RR	1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
1.321	-0.053	tHld		1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.078, 35.135%; tC2Q: 0.144, 64.865%
Required Clock Path Delay	cell: 0.675, 49.172%; route: 0.698, 50.828%

Path9

Path Summary:

Slack	0.275
Data Arrival Time	1.673
Data Required Time	1.397
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.513	0.141	tC2Q	RF	3	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q
1.520	0.006	tNET	FF	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n851_s0/I1
1.673	0.153	tINS	FF	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n851_s0/F
1.673	0.000	tNET	FF	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.397	0.025	tHld		1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path10

Path Summary:

Slack	0.275
Data Arrival Time	1.675
Data Required Time	1.400
From	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.516	0.141	tC2Q	RF	3	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/Q
1.522	0.006	tNET	FF	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/n5129_s1/I2
1.675	0.153	tINS	FF	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/n5129_s1/F
1.675	0.000	tNET	FF	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
1.400	0.025	tHld		1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.153, 51.000%; route: 0.006, 2.000%; tC2Q: 0.141, 47.000%
Required Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%

Path11

Path Summary:

Slack	0.278
Data Arrival Time	2.733
Data Required Time	2.455
From	gw_gao_inst_0/u_la0_top/bit_count_0_s1
To	gw_gao_inst_0/u_la0_top/bit_count_0_s1
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
2.571	0.141	tC2Q	RF	6	R24C51[0][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q
2.580	0.009	tNET	FF	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/n1029_s3/I0
2.733	0.153	tINS	FF	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/n1029_s3/F
2.733	0.000	tNET	FF	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
2.455	0.025	tHld		1	R24C51[0][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%

Path12

Path Summary:

Slack	0.278
Data Arrival Time	2.733
Data Required Time	2.455
From	gw_gao_inst_0/u_la0_top/bit_count_1_s1
To	gw_gao_inst_0/u_la0_top/bit_count_1_s1
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
2.571	0.141	tC2Q	RF	5	R24C51[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q
2.580	0.009	tNET	FF	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/n1028_s2/I2
2.733	0.153	tINS	FF	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/n1028_s2/F
2.733	0.000	tNET	FF	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.430	1.079	tNET	RR	1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
2.455	0.025	tHld		1	R24C51[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.602%; route: 1.079, 44.398%

Path13

Path Summary:

Slack	0.278
Data Arrival Time	1.672
Data Required Time	1.394
From	ad_6_s0
To	ad_6_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][A]	ad_6_s0/CLK
1.510	0.141	tC2Q	RF	9	R11C54[0][A]	ad_6_s0/Q
1.519	0.009	tNET	FF	1	R11C54[0][A]	n320_s1/I3
1.672	0.153	tINS	FF	1	R11C54[0][A]	n320_s1/F
1.672	0.000	tNET	FF	1	R11C54[0][A]	ad_6_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][A]	ad_6_s0/CLK
1.394	0.025	tHld		1	R11C54[0][A]	ad_6_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path14

Path Summary:

Slack	0.278
Data Arrival Time	2.719
Data Required Time	2.441
From	gw_gao_inst_0/u_la0_top/word_count_2_s0
To	gw_gao_inst_0/u_la0_top/word_count_2_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.416	1.065	tNET	RR	1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/word_count_2_s0/CLK
2.557	0.141	tC2Q	RF	4	R16C48[0][A]	gw_gao_inst_0/u_la0_top/word_count_2_s0/Q
2.566	0.009	tNET	FF	1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_2_s0/I1
2.719	0.153	tINS	FF	1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_2_s0/F
2.719	0.000	tNET	FF	1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/word_count_2_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.416	1.065	tNET	RR	1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/word_count_2_s0/CLK
2.441	0.025	tHld		1	R16C48[0][A]	gw_gao_inst_0/u_la0_top/word_count_2_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.913%; route: 1.065, 44.087%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.913%; route: 1.065, 44.087%

Path15

Path Summary:

Slack	0.278
Data Arrival Time	2.734
Data Required Time	2.456
From	gw_gao_inst_0/u_la0_top/word_count_13_s0
To	gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk	clk2:[R]
Latch Clk	clk2:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.080	tNET	RR	1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.572	0.141	tC2Q	RF	4	R21C50[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
2.581	0.009	tNET	FF	1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I1
2.734	0.153	tINS	FF	1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
2.734	0.000	tNET	FF	1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk2
0.000	0.000	tCL	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR1[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	R28C89	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	499	R28C89	gw_gao_inst_0/u_gw_jtag/tck_o
2.431	1.080	tNET	RR	1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.456	0.025	tHld		1	R21C50[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 55.574%; route: 1.080, 44.426%
Arrival Data Path Delay	cell: 0.153, 50.495%; route: 0.009, 2.970%; tC2Q: 0.141, 46.535%
Required Clock Path Delay	cell: 1.351, 55.574%; route: 1.080, 44.426%

Path16

Path Summary:

Slack	0.281
Data Arrival Time	1.683
Data Required Time	1.402
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.518	0.141	tC2Q	RF	14	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/Q
1.530	0.012	tNET	FF	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n953_s1/I1
1.683	0.153	tINS	FF	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n953_s1/F
1.683	0.000	tNET	FF	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.402	0.025	tHld		1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path17

Path Summary:

Slack	0.281
Data Arrival Time	1.681
Data Required Time	1.400
From	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.516	0.141	tC2Q	RF	5	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/Q
1.528	0.012	tNET	FF	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/n5131_s1/I0
1.681	0.153	tINS	FF	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/n5131_s1/F
1.681	0.000	tNET	FF	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
1.400	0.025	tHld		1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.153, 50.000%; route: 0.012, 3.922%; tC2Q: 0.141, 46.078%
Required Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%

Path18

Path Summary:

Slack	0.287
Data Arrival Time	1.686
Data Required Time	1.399
From	ad_4_s0
To	ad_4_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C53[0][A]	ad_4_s0/CLK
1.518	0.144	tC2Q	RR	11	R11C53[0][A]	ad_4_s0/Q
1.533	0.015	tNET	RR	1	R11C53[0][A]	n322_s1/I0
1.686	0.153	tINS	RF	1	R11C53[0][A]	n322_s1/F
1.686	0.000	tNET	FF	1	R11C53[0][A]	ad_4_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.374	0.698	tNET	RR	1	R11C53[0][A]	ad_4_s0/CLK
1.399	0.025	tHld		1	R11C53[0][A]	ad_4_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%
Arrival Data Path Delay	cell: 0.153, 49.038%; route: 0.015, 4.808%; tC2Q: 0.144, 46.154%
Required Clock Path Delay	cell: 0.675, 49.181%; route: 0.698, 50.819%

Path19

Path Summary:

Slack	0.290
Data Arrival Time	1.684
Data Required Time	1.394
From	ad_3_s0
To	ad_3_s0
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[1][A]	ad_3_s0/CLK
1.513	0.144	tC2Q	RR	9	R11C54[1][A]	ad_3_s0/Q
1.531	0.018	tNET	RR	1	R11C54[1][A]	n323_s1/I3
1.684	0.153	tINS	RF	1	R11C54[1][A]	n323_s1/F
1.684	0.000	tNET	FF	1	R11C54[1][A]	ad_3_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[1][A]	ad_3_s0/CLK
1.394	0.025	tHld		1	R11C54[1][A]	ad_3_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.153, 48.571%; route: 0.018, 5.714%; tC2Q: 0.144, 45.714%
Required Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%

Path20

Path Summary:

Slack	0.291
Data Arrival Time	1.699
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.381	0.705	tNET	RR	1	R26C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/CLK
1.525	0.144	tC2Q	RR	1	R26C59[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_74_s0/Q
1.699	0.174	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	-0.010
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.932%; route: 0.705, 51.068%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.174, 54.717%; tC2Q: 0.144, 45.283%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path21

Path Summary:

Slack	0.298
Data Arrival Time	1.707
Data Required Time	1.410
From	ad_5_s0
To	memreal1_memreal1_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][B]	ad_5_s0/CLK
1.513	0.144	tC2Q	RR	10	R11C54[0][B]	ad_5_s0/Q
1.707	0.194	tNET	RR	1	BSRAM_R10[17]	memreal1_memreal1_0_0_s/AD[10]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
1.410	0.035	tHld		1	BSRAM_R10[17]	memreal1_memreal1_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.194, 57.396%; tC2Q: 0.144, 42.604%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path22

Path Summary:

Slack	0.303
Data Arrival Time	1.714
Data Required Time	1.411
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.700	tNET	RR	1	R17C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
1.519	0.144	tC2Q	RR	13	R17C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/Q
1.714	0.195	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/ADA[9]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA
1.411	0.037	tHld		1	BSRAM_R28[19]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Path Statistics:

Clock Skew	-0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.127%; route: 0.700, 50.873%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.195, 57.522%; tC2Q: 0.144, 42.478%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path23

Path Summary:

Slack	0.303
Data Arrival Time	1.714
Data Required Time	1.411
From	ad_6_s0
To	memreal1_memreal1_0_0_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.369	0.694	tNET	RR	1	R11C54[0][A]	ad_6_s0/CLK
1.513	0.144	tC2Q	RR	9	R11C54[0][A]	ad_6_s0/Q
1.714	0.201	tNET	RR	1	BSRAM_R10[17]	memreal1_memreal1_0_0_s/AD[11]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.375	0.699	tNET	RR	1	BSRAM_R10[17]	memreal1_memreal1_0_0_s/CLK
1.411	0.037	tHld		1	BSRAM_R10[17]	memreal1_memreal1_0_0_s

Path Statistics:

Clock Skew	0.005
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.325%; route: 0.694, 50.675%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.201, 58.261%; tC2Q: 0.144, 41.739%
Required Clock Path Delay	cell: 0.675, 49.145%; route: 0.699, 50.855%

Path24

Path Summary:

Slack	0.304
Data Arrival Time	1.711
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.356	0.681	tNET	RR	1	R12C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/CLK
1.497	0.141	tC2Q	RF	1	R12C59[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_73_s0/Q
1.711	0.214	tNET	FF	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[1]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	0.014
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.214, 60.282%; tC2Q: 0.141, 39.718%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Path25

Path Summary:

Slack	0.305
Data Arrival Time	1.712
Data Required Time	1.408
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_84_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s
Launch Clk	clk1:[R]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.379	0.704	tNET	RR	1	R27C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_84_s0/CLK
1.523	0.144	tC2Q	RR	1	R27C58[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_84_s0/Q
1.712	0.189	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/DI[12]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.371	0.695	tNET	RR	1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKA
1.408	0.037	tHld		1	BSRAM_R28[18]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Path Statistics:

Clock Skew	-0.009
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 48.967%; route: 0.704, 51.033%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.189, 56.757%; tC2Q: 0.144, 43.243%
Required Clock Path Delay	cell: 0.675, 49.289%; route: 0.695, 50.711%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	6.661
Data Arrival Time	15.627
Data Required Time	22.288
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.627	2.574	tNET	FF	1	R25C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.636	1.953	tNET	RR	1	R25C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1/CLK
22.288	-0.347	tSu		1	R25C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_3_s1

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.574, 85.329%; tC2Q: 0.442, 14.671%
Required Clock Path Delay	cell: 0.683, 25.895%; route: 1.953, 74.105%

Path2

Path Summary:

Slack	6.661
Data Arrival Time	15.627
Data Required Time	22.288
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.627	2.574	tNET	FF	1	R25C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.636	1.953	tNET	RR	1	R25C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1/CLK
22.288	-0.347	tSu		1	R25C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_0_s1

Path Statistics:

Clock Skew	0.025
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.574, 85.329%; tC2Q: 0.442, 14.671%
Required Clock Path Delay	cell: 0.683, 25.895%; route: 1.953, 74.105%

Path3

Path Summary:

Slack	6.664
Data Arrival Time	15.627
Data Required Time	22.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.627	2.574	tNET	FF	1	R24C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.638	1.956	tNET	RR	1	R24C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
22.291	-0.347	tSu		1	R24C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.028
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.574, 85.329%; tC2Q: 0.442, 14.671%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path4

Path Summary:

Slack	6.664
Data Arrival Time	15.627
Data Required Time	22.291
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.627	2.574	tNET	FF	1	R24C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.638	1.956	tNET	RR	1	R24C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1/CLK
22.291	-0.347	tSu		1	R24C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_2_s1

Path Statistics:

Clock Skew	0.028
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.574, 85.329%; tC2Q: 0.442, 14.671%
Required Clock Path Delay	cell: 0.683, 25.871%; route: 1.956, 74.129%

Path5

Path Summary:

Slack	6.879
Data Arrival Time	15.417
Data Required Time	22.296
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.417	2.364	tNET	FF	1	R22C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.643	1.961	tNET	RR	1	R22C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
22.296	-0.347	tSu		1	R22C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	0.033
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.364, 84.232%; tC2Q: 0.442, 15.768%
Required Clock Path Delay	cell: 0.683, 25.822%; route: 1.961, 74.178%

Path6

Path Summary:

Slack	7.074
Data Arrival Time	15.224
Data Required Time	22.298
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.224	2.171	tNET	FF	1	R21C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.646	1.963	tNET	RR	1	R21C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
22.298	-0.347	tSu		1	R21C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	0.035
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.171, 83.070%; tC2Q: 0.442, 16.930%
Required Clock Path Delay	cell: 0.683, 25.797%; route: 1.963, 74.203%

Path7

Path Summary:

Slack	7.076
Data Arrival Time	15.224
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.224	2.171	tNET	FF	1	R20C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1/CLK
22.301	-0.347	tSu		1	R20C62[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_4_s1

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.171, 83.070%; tC2Q: 0.442, 16.930%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path8

Path Summary:

Slack	7.076
Data Arrival Time	15.224
Data Required Time	22.301
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.224	2.171	tNET	FF	1	R20C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.648	1.966	tNET	RR	1	R20C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1/CLK
22.301	-0.347	tSu		1	R20C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_5_s1

Path Statistics:

Clock Skew	0.038
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.171, 83.070%; tC2Q: 0.442, 16.930%
Required Clock Path Delay	cell: 0.683, 25.773%; route: 1.966, 74.227%

Path9

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1/CLK
22.264	-0.347	tSu		1	R17C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_4_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path10

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1/CLK
22.264	-0.347	tSu		1	R17C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_5_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path11

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1/CLK
22.264	-0.347	tSu		1	R17C64[2][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_6_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path12

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1/CLK
22.264	-0.347	tSu		1	R17C64[0][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_7_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path13

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1/CLK
22.264	-0.347	tSu		1	R17C64[0][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_8_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path14

Path Summary:

Slack	7.115
Data Arrival Time	15.149
Data Required Time	22.264
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.149	2.096	tNET	FF	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.612	1.929	tNET	RR	1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1/CLK
22.264	-0.347	tSu		1	R17C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_9_s1

Path Statistics:

Clock Skew	0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.096, 82.570%; tC2Q: 0.442, 17.430%
Required Clock Path Delay	cell: 0.683, 26.131%; route: 1.929, 73.869%

Path15

Path Summary:

Slack	7.123
Data Arrival Time	15.132
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.132	2.079	tNET	FF	1	R14C64[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.602	1.920	tNET	RR	1	R14C64[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
22.255	-0.347	tSu		1	R14C64[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.079, 82.449%; tC2Q: 0.442, 17.551%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path16

Path Summary:

Slack	7.123
Data Arrival Time	15.132
Data Required Time	22.255
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.132	2.079	tNET	FF	1	R14C64[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.602	1.920	tNET	RR	1	R14C64[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
22.255	-0.347	tSu		1	R14C64[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-0.008
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.079, 82.449%; tC2Q: 0.442, 17.551%
Required Clock Path Delay	cell: 0.683, 26.228%; route: 1.920, 73.772%

Path17

Path Summary:

Slack	7.134
Data Arrival Time	15.128
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.128	2.075	tNET	FF	1	R16C64[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C64[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0/CLK
22.263	-0.347	tSu		1	R16C64[3][A]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_0_s0

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.075, 82.423%; tC2Q: 0.442, 17.577%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path18

Path Summary:

Slack	7.134
Data Arrival Time	15.128
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.128	2.075	tNET	FF	1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0/CLK
22.263	-0.347	tSu		1	R16C64[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_start_syn_1_s0

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.075, 82.423%; tC2Q: 0.442, 17.577%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Path19

Path Summary:

Slack	7.148
Data Arrival Time	15.094
Data Required Time	22.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.094	2.041	tNET	FF	1	R12C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.590	1.908	tNET	RR	1	R12C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
22.243	-0.347	tSu		1	R12C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-0.020
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.041, 82.184%; tC2Q: 0.442, 17.816%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path20

Path Summary:

Slack	7.148
Data Arrival Time	15.094
Data Required Time	22.243
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
15.094	2.041	tNET	FF	1	R12C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.590	1.908	tNET	RR	1	R12C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
22.243	-0.347	tSu		1	R12C62[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-0.020
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 2.041, 82.184%; tC2Q: 0.442, 17.816%
Required Clock Path Delay	cell: 0.683, 26.348%; route: 1.908, 73.652%

Path21

Path Summary:

Slack	7.312
Data Arrival Time	14.948
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.948	1.895	tNET	FF	1	R15C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R15C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
22.261	-0.347	tSu		1	R15C64[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.895, 81.070%; tC2Q: 0.442, 18.930%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path22

Path Summary:

Slack	7.312
Data Arrival Time	14.948
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.948	1.895	tNET	FF	1	R15C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R15C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1/CLK
22.261	-0.347	tSu		1	R15C64[1][B]	gw_gao_inst_0/u_la0_top/capture_window_sel_2_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.895, 81.070%; tC2Q: 0.442, 18.930%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path23

Path Summary:

Slack	7.312
Data Arrival Time	14.948
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.948	1.895	tNET	FF	1	R15C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R15C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1/CLK
22.261	-0.347	tSu		1	R15C64[2][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_3_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.895, 81.070%; tC2Q: 0.442, 18.930%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path24

Path Summary:

Slack	7.312
Data Arrival Time	14.948
Data Required Time	22.261
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.948	1.895	tNET	FF	1	R15C64[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.608	1.926	tNET	RR	1	R15C64[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
22.261	-0.347	tSu		1	R15C64[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-0.002
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.895, 81.070%; tC2Q: 0.442, 18.930%
Required Clock Path Delay	cell: 0.683, 26.168%; route: 1.926, 73.832%

Path25

Path Summary:

Slack	7.327
Data Arrival Time	14.936
Data Required Time	22.263
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.688	0.688	tINS	FF	399	IOB29[A]	clk_ibuf/O
12.611	1.923	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
13.053	0.442	tC2Q	FF	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
14.936	1.883	tNET	FF	1	R16C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					clk1
20.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
20.683	0.683	tINS	RR	399	IOB29[A]	clk_ibuf/O
22.610	1.928	tNET	RR	1	R16C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
22.263	-0.347	tSu		1	R16C62[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	-0.001
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 26.335%; route: 1.923, 73.665%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.883, 80.968%; tC2Q: 0.442, 19.032%
Required Clock Path Delay	cell: 0.683, 26.149%; route: 1.928, 73.851%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	10.480
Data Arrival Time	11.792
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.791	0.256	tNET	RR	1	R13C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R13C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
1.312	-0.053	tHld		1	R13C54[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.256, 61.836%; tC2Q: 0.158, 38.164%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path2

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
1.312	-0.053	tHld		1	R14C55[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path3

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
1.312	-0.053	tHld		1	R14C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path4

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK
1.312	-0.053	tHld		1	R14C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path5

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
1.312	-0.053	tHld		1	R14C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path6

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
1.312	-0.053	tHld		1	R14C55[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path7

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
1.312	-0.053	tHld		1	R14C55[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path8

Path Summary:

Slack	10.582
Data Arrival Time	11.893
Data Required Time	1.312
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R14C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.365	0.689	tNET	RR	1	R14C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK
1.312	-0.053	tHld		1	R14C55[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Path Statistics:

Clock Skew	-0.013
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.505%; route: 0.689, 50.495%

Path9

Path Summary:

Slack	10.586
Data Arrival Time	11.893
Data Required Time	1.308
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.893	0.358	tNET	RR	1	R13C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.361	0.685	tNET	RR	1	R13C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
1.308	-0.053	tHld		1	R13C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.358, 69.380%; tC2Q: 0.158, 30.620%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path10

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
1.316	-0.053	tHld		1	R14C56[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path11

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
1.316	-0.053	tHld		1	R14C56[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path12

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
1.316	-0.053	tHld		1	R14C56[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path13

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
1.316	-0.053	tHld		1	R14C56[3][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path14

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
1.316	-0.053	tHld		1	R14C56[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path15

Path Summary:

Slack	10.688
Data Arrival Time	12.003
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.003	0.468	tNET	RR	1	R14C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
1.316	-0.053	tHld		1	R14C56[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.468, 74.760%; tC2Q: 0.158, 25.240%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path16

Path Summary:

Slack	10.688
Data Arrival Time	11.991
Data Required Time	1.303
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.991	0.456	tNET	RR	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.356	0.681	tNET	RR	1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0/CLK
1.303	-0.053	tHld		1	R12C55[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_6_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.456, 74.267%; tC2Q: 0.158, 25.733%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path17

Path Summary:

Slack	10.688
Data Arrival Time	11.991
Data Required Time	1.303
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.991	0.456	tNET	RR	1	R12C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.356	0.681	tNET	RR	1	R12C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0/CLK
1.303	-0.053	tHld		1	R12C55[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_7_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.456, 74.267%; tC2Q: 0.158, 25.733%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path18

Path Summary:

Slack	10.688
Data Arrival Time	11.991
Data Required Time	1.303
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
11.991	0.456	tNET	RR	1	R12C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.356	0.681	tNET	RR	1	R12C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0/CLK
1.303	-0.053	tHld		1	R12C55[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_8_s0

Path Statistics:

Clock Skew	-0.021
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.456, 74.267%; tC2Q: 0.158, 25.733%
Required Clock Path Delay	cell: 0.675, 49.797%; route: 0.681, 50.203%

Path19

Path Summary:

Slack	10.780
Data Arrival Time	12.087
Data Required Time	1.308
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.087	0.552	tNET	RR	1	R12C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.361	0.685	tNET	RR	1	R12C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
1.308	-0.053	tHld		1	R12C54[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew	-0.017
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.552, 77.746%; tC2Q: 0.158, 22.254%
Required Clock Path Delay	cell: 0.675, 49.651%; route: 0.685, 50.349%

Path20

Path Summary:

Slack	10.923
Data Arrival Time	12.247
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.247	0.711	tNET	RR	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
1.324	-0.053	tHld		1	R15C61[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.711, 81.818%; tC2Q: 0.158, 18.182%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path21

Path Summary:

Slack	10.923
Data Arrival Time	12.247
Data Required Time	1.324
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.247	0.711	tNET	RR	1	R15C61[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.377	0.701	tNET	RR	1	R15C61[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
1.324	-0.053	tHld		1	R15C61[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-0.001
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.711, 81.818%; tC2Q: 0.158, 18.182%
Required Clock Path Delay	cell: 0.675, 49.074%; route: 0.701, 50.926%

Path22

Path Summary:

Slack	11.021
Data Arrival Time	12.340
Data Required Time	1.319
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.340	0.805	tNET	RR	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.372	0.697	tNET	RR	1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.319	-0.053	tHld		1	R15C62[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-0.005
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 83.593%; tC2Q: 0.158, 16.407%
Required Clock Path Delay	cell: 0.675, 49.217%; route: 0.697, 50.783%

Path23

Path Summary:

Slack	11.025
Data Arrival Time	12.340
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.340	0.805	tNET	RR	1	R14C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
1.316	-0.053	tHld		1	R14C62[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 83.593%; tC2Q: 0.158, 16.407%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path24

Path Summary:

Slack	11.025
Data Arrival Time	12.340
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.340	0.805	tNET	RR	1	R14C62[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C62[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
1.316	-0.053	tHld		1	R14C62[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 83.593%; tC2Q: 0.158, 16.407%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Path25

Path Summary:

Slack	11.025
Data Arrival Time	12.340
Data Required Time	1.315
From	gw_gao_inst_0/u_la0_top/rst_ao_s0
To	gw_gao_inst_0/u_la0_top/capture_end_dly_s0
Launch Clk	clk1:[F]
Latch Clk	clk1:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					clk1
10.000	0.000	tCL	FF	1	IOB29[A]	clk_ibuf/I
10.677	0.678	tINS	FF	399	IOB29[A]	clk_ibuf/O
11.377	0.700	tNET	FF	1	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK
11.535	0.158	tC2Q	FR	69	R15C62[2][A]	gw_gao_inst_0/u_la0_top/rst_ao_s0/Q
12.340	0.805	tNET	RR	1	R14C62[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/PRESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					clk1
0.000	0.000	tCL	RR	1	IOB29[A]	clk_ibuf/I
0.675	0.675	tINS	RR	399	IOB29[A]	clk_ibuf/O
1.368	0.693	tNET	RR	1	R14C62[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0/CLK
1.316	-0.053	tHld		1	R14C62[0][A]	gw_gao_inst_0/u_la0_top/capture_end_dly_s0

Path Statistics:

Clock Skew	-0.009
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 49.183%; route: 0.700, 50.817%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.805, 83.593%; tC2Q: 0.158, 16.407%
Required Clock Path Delay	cell: 0.675, 49.361%; route: 0.693, 50.639%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	2.453
Actual Width:	3.453
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.066	2.701	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.519	1.164	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKB

MPW2

MPW Summary:

Slack:	2.453
Actual Width:	3.453
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.066	2.701	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.519	1.164	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_4_s/CLKB

MPW3

MPW Summary:

Slack:	2.453
Actual Width:	3.453
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.066	2.701	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.519	1.164	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKB

MPW4

MPW Summary:

Slack:	2.458
Actual Width:	3.458
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.057	2.692	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.515	1.160	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKB

MPW5

MPW Summary:

Slack:	2.458
Actual Width:	3.458
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.057	2.692	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.515	1.160	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_3_s/CLKB

MPW6

MPW Summary:

Slack:	2.458
Actual Width:	3.458
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.057	2.692	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.515	1.160	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKB

MPW7

MPW Summary:

Slack:	2.458
Actual Width:	3.458
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.057	2.692	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.515	1.160	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKB

MPW8

MPW Summary:

Slack:	2.464
Actual Width:	3.464
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.047	2.682	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.511	1.156	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKB

MPW9

MPW Summary:

Slack:	2.464
Actual Width:	3.464
Required Width:	1.000
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.047	2.682	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKB

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.511	1.156	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKB

MPW10

MPW Summary:

Slack:	3.193
Actual Width:	3.443
Required Width:	0.250
Type:	High Pulse Width
Clock:	clk2
Objects:	gw_gao_inst_0/u_la0_top/data_register_142_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
0.000	0.000			active clock edge time
0.000	0.000			clk2
0.000	0.000	tCL	RR	gw_gao_inst_0/tck_ibuf/I
0.683	0.683	tINS	RR	gw_gao_inst_0/tck_ibuf/O
0.683	0.000	tNET	RR	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.365	0.683	tINS	RR	gw_gao_inst_0/u_gw_jtag/tck_o
4.100	2.735	tNET	RR	gw_gao_inst_0/u_la0_top/data_register_142_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
5.000	0.000			active clock edge time
5.000	0.000			clk2
5.000	0.000	tCL	FF	gw_gao_inst_0/tck_ibuf/I
5.677	0.678	tINS	FF	gw_gao_inst_0/tck_ibuf/O
5.677	0.000	tNET	FF	gw_gao_inst_0/u_gw_jtag/tck_pad_i
6.355	0.678	tINS	FF	gw_gao_inst_0/u_gw_jtag/tck_o
7.543	1.188	tNET	FF	gw_gao_inst_0/u_la0_top/data_register_142_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
499	gw_gao_inst_0/control0[0]	42.006	2.735
399	clk_d	8.734	1.975
170	gw_gao_inst_0/u_la0_top/n20_3	45.166	1.893
150	gw_gao_inst_0/u_la0_top/data_out_shift_reg_147_7	42.598	1.900
148	gw_gao_inst_0/u_la0_top/n1271_5	42.531	1.766
134	gw_gao_inst_0/u_la0_top/n1271_4	44.307	2.078
69	gw_gao_inst_0/u_la0_top/rst_ao	6.661	2.574
54	gw_gao_inst_0/u_la0_top/data_to_word_counter_15_5	42.369	1.290
38	gw_gao_inst_0/u_la0_top/op_reg_en_10	43.263	1.376
32	gw_gao_inst_0/u_la0_top/u_ao_crc32/crc_28_7	44.077	0.740

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R2C2	100.00%
R2C3	100.00%
R2C4	100.00%
R2C19	100.00%
R2C20	100.00%
R2C52	100.00%
R3C26	100.00%
R4C63	100.00%
R7C48	100.00%
R13C87	100.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name clk1 -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK	Actived	create_clock -name clk2 -period 50 -waveform {0 5} [get_ports {tck_pad_i}]
TC_CLOCK_GROUP	Actived	set_clock_groups -asynchronous -group [get_clocks {clk1}] -group [get_clocks {clk2}]