Synthesis Messages

Report Title GowinSynthesis Report
Design File E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\top.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\src\Complex_Multiplier\complex_multiplier.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.02_x64\IDE\data\ipcores\gw_jtag.v
E:\myWork\IP\releaseVerify\version\1.9.11.02\Gowin_Complex_Multiplier_RefDesign\Complex_Multiplier_18\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Tue Jun 10 16:10:56 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.515s, Elapsed time = 0h 0m 0.534s, Peak memory usage = 640.105MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 640.105MB
    Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 640.105MB
    Optimizing Phase 2: CPU time = 0h 0m 0.375s, Elapsed time = 0h 0m 0.375s, Peak memory usage = 640.105MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 640.105MB
    Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 640.105MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 640.105MB
    Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 640.105MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.193s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 640.105MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.125s, Peak memory usage = 640.105MB
Generate output files:
    CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.124s, Peak memory usage = 640.105MB
Total Time and Memory Usage CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 640.105MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 82
I/O Buf 82
    IBUF 5
    OBUF 77
Register 873
    DFFRE 1
    DFFPE 38
    DFFCE 834
LUT 599
    LUT2 48
    LUT3 126
    LUT4 425
MUX 1
    MUX16 1
ALU 50
    ALU 50
INV 5
    INV 5
DSP
    MULTALU27X18 3
BSRAM 14
    SDPX9B 9
    pROM 3
    pROMX9 2
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 662(612 LUT, 50 ALU) / 23040 3%
Register 873 / 23685 4%
  --Register as Latch 0 / 23685 0%
  --Register as FF 873 / 23685 4%
BSRAM 14 / 56 25%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 10.000 100.000 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.000(MHz) 98.084(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.195
Data Arrival Time 7.066
Data Required Time 6.870
From memimag1_memimag1_0_0_s
To u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 399 clk_ibuf/O
0.375 0.375 tNET RR 36 memimag1_memimag1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memimag1_memimag1_0_0_s/DO[8]
2.765 0.375 tNET RR 90 u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
6.716 3.951 tINS RF 2 u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[29]
7.066 0.350 tNET FF 1 u_complex_mult/comp_mult_inst/prod3_36_s0/C[29]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 399 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
6.870 -3.505 tSu 1 u_complex_mult/comp_mult_inst/prod3_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.951, 59.048%; route: 0.725, 10.836%; tC2Q: 2.015, 30.116%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack -0.195
Data Arrival Time 7.066
Data Required Time 6.870
From memimag1_memimag1_0_0_s
To u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 399 clk_ibuf/O
0.375 0.375 tNET RR 36 memimag1_memimag1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memimag1_memimag1_0_0_s/DO[8]
2.765 0.375 tNET RR 90 u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
6.716 3.951 tINS RF 2 u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[29]
7.066 0.350 tNET FF 1 u_complex_mult/comp_mult_inst/prod2_36_s0/C[29]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 399 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
6.870 -3.505 tSu 1 u_complex_mult/comp_mult_inst/prod2_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.951, 59.048%; route: 0.725, 10.836%; tC2Q: 2.015, 30.116%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack -0.058
Data Arrival Time 6.925
Data Required Time 6.867
From memimag1_memimag1_0_0_s
To u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 399 clk_ibuf/O
0.375 0.375 tNET RR 36 memimag1_memimag1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memimag1_memimag1_0_0_s/DO[8]
2.765 0.375 tNET RR 90 u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
6.575 3.810 tINS RF 2 u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[26]
6.925 0.350 tNET FF 1 u_complex_mult/comp_mult_inst/prod3_36_s0/C[26]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 399 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
6.867 -3.508 tSu 1 u_complex_mult/comp_mult_inst/prod3_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.810, 58.166%; route: 0.725, 11.069%; tC2Q: 2.015, 30.765%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack -0.058
Data Arrival Time 6.925
Data Required Time 6.867
From memimag1_memimag1_0_0_s
To u_complex_mult/comp_mult_inst/prod2_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 399 clk_ibuf/O
0.375 0.375 tNET RR 36 memimag1_memimag1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memimag1_memimag1_0_0_s/DO[8]
2.765 0.375 tNET RR 90 u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
6.575 3.810 tINS RF 2 u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[26]
6.925 0.350 tNET FF 1 u_complex_mult/comp_mult_inst/prod2_36_s0/C[26]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 399 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/prod2_36_s0/CLK[0]
6.867 -3.508 tSu 1 u_complex_mult/comp_mult_inst/prod2_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.810, 58.166%; route: 0.725, 11.069%; tC2Q: 2.015, 30.765%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 0.104
Data Arrival Time 7.023
Data Required Time 7.126
From memimag1_memimag1_0_0_s
To u_complex_mult/comp_mult_inst/prod3_36_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 399 clk_ibuf/O
0.375 0.375 tNET RR 36 memimag1_memimag1_0_0_s/CLK
2.390 2.015 tC2Q RR 2 memimag1_memimag1_0_0_s/DO[8]
2.765 0.375 tNET RR 90 u_complex_mult/comp_mult_inst/prod1_36_s0/D[8]
6.673 3.908 tINS RF 2 u_complex_mult/comp_mult_inst/prod1_36_s0/DOUT[24]
7.023 0.350 tNET FF 1 u_complex_mult/comp_mult_inst/prod3_36_s0/C[24]
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.000 0.000 tINS RR 399 clk_ibuf/O
10.375 0.375 tNET RR 1 u_complex_mult/comp_mult_inst/prod3_36_s0/CLK[0]
7.126 -3.249 tSu 1 u_complex_mult/comp_mult_inst/prod3_36_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 3.908, 58.782%; route: 0.725, 10.906%; tC2Q: 2.015, 30.312%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%