rtl_dir:=				../../project/src
tb_dir:=				../../tb
inc_dir:=				$(rtl_dir)/data
vo_file:=				$(rtl_dir)/basic_fir_filter/basic_fir_filter.vo
tb_file:=				$(tb_dir)/tb_vcs.v
rtl_file:=				$(rtl_dir)/fir_onboard.v						\
						$(rtl_dir)/deUstb.v								\
						$(rtl_dir)/gw_pll.v			

vcs:
	vcs -debug_all -R -full64 -fsdb -sverilog 							\
	-v $(tb_dir)/prim_sim.v											\
	$(tb_file)															\
	$(rtl_file)															\
	$(vo_file)															\
	+incdir+$(inc_dir)													\
    -cm line+cond+fsm+branch+tgl
	
vd:
	verdi -sverilog														\
	-v $(tb_dir)/prim_sim.v											\
	$(tb_file)															\
	$(rtl_file)															\
	$(vo_file)															\
	+incdir+$(inc_dir)													\
	-ssf tb.fsdb														\
	&
#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf csrc simv.daidir simv.vdb verdiLog cm.log novas.conf novas.rc novas_dump.log simv tb.fsdb ucli.key wave.ses.png 