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                  Basic FIR Filter参考设计阅读指南
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目标器件：GW2A-LV55PG484C8/I7
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文件列表
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.
| -- docs
|    `-- readme.txt				-->	自述文件
| -- project
|    `-- project.gprj				-->	参考设计工程
|    |-- impl
|    |-- src
|        `-- data
|        |   `-- idata.dat			-->	输入数据文件
|        |   |-- icoeffi.dat			-->	输入系数文件
|        |   |-- golden.txt			-->	标准结果
|        |-- basic_fir_filter
|        |   `-- basic_fir_filter.ipc
|        |   |-- basic_fir_filter.v
|        |   |-- basic_fir_filter.vo		-->	仿真使用vo文件
|        |-- fir_onboard.v			-->	工程顶层模块
|        |-- gw_pll.v				-->	工程所需文件
|        |-- deUstb.v				-->	工程所需文件
|        |-- gao.v
|        |-- project.cst
|        |-- project.gao
| -- simulation
|        `-- Modelsim
|        |   `-- cmd.do				-->	modelsim仿真脚本
|        |-- VCS_SIM
|            `-- makefile			-->	vcs仿真脚本
| -- tb
     `-- tb_vcs.v				-->	vcs仿真testbench
     |-- tb_mod.v				-->	modelsim仿真testbench
     |-- prim_sim.v				-->	仿真原语库

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使用说明：
	1、板测：使用云源软件打开上述文件中project.gprj，设置工程顶层模块，将data文件夹设置为加载路径，综合；根据所使用器件设置约束和gao.v后布局布线后下载测试。使用GAO抓取数据。
	2、modelsim仿真：仿真脚本存放于Modelsim文件夹中。
	3、vcs仿真：在VCS_SIM中，运行“make vcs”，开始仿真；运行“make vd”,打开使用verdi查看波形；运行“make clean”，清除仿真产生的文件。

	注：tb文件夹下prim_sim.v仅供参考，建议用户根据情况在仿真时使用最新版替换。

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                  Example Basic FIR Filter Design Readme
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Object device:GW2A-LV55PG484C8/I7
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File List:
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.
| -- docs
|    `-- readme.txt				-->	readme file (this file)
| -- project
|    `-- project.gprj				-->	GowinYunYuan Project File for Example Design
|    |-- impl
|    |-- src
|        `-- data
|        |   `-- idata.dat			-->	Input data file
|        |   |-- icoeffi.dat			-->	Input coefficient data file
|        |   |-- golden.txt			-->	Standard result
|        |-- basic_fir_filter
|        |   `-- basic_fir_filter.ipc
|        |   |-- basic_fir_filter.v
|        |   |-- basic_fir_filter.vo		-->	Verilog simulation File for tb
|        |-- fir_onboard.v			-->	File for GowinYunYuan Project
|        |-- gw_pll.v				-->	File for GowinYunYuan Project
|        |-- deUstb.v				-->	File for GowinYunYuan Project
|        |-- gao.v
|        |-- project.cst
|        |-- project.gao
| -- simulation
|        `-- Modelsim
|        |   `-- cmd.do				-->	modelsim simulation script
|        |-- VCS_SIM
|            `-- makefile			-->	vcs simulation script
| -- tb
     `-- tb_vcs.v				-->	TestBench for vcs simulation
     |-- tb_mod.v				-->	TestBench for modelsim simulation
     |-- prim_sim.v				-->	Verilog functional simulation library

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Instructions:
	1、Onboard test: Launch GowinYunYuan and select "File -> Open -> Project", set Top Module and Include Path. After Sythesize, cofigure Physical Constraints and GAO Config Files.
	2、Modelsim simulation: Please use script in Modelsim folder.
	3、Open the terminal window in the above VCS_SIM folder and enter the "make vcs" command to simulate, enter the "make vd" command to view the waveform, enter the "make clean" command to clear the generated files.