tbDir:=			../tb
designDir:=		../project/src
voDir:=			../project/src/Fra_div
voFile:=		$(voDir)/Fra_div.vo
tbFile:=		$(tbDir)/tb.v
topFile:=		$(designDir)/top.v

vcs:		
	vcs -debug_all -R -full64 -fsdb -sverilog	\
	-v ../tb/prim_sim.v 		                \
	$(tbFile)			 						\
	$(voFile)									\
	$(topFile)          						\
	+incdir+$(rtlDir)
vd:
	
	verdi -sverilog								\
	-v ../tb/prim_sim.v 		                \
	$(tbFile)			 						\
	$(voFile)									\
	$(topFile)          						\
	+incdir+$(rtlDir)							\
	-ssf tb.fsdb								\
	&

#----------------------------------------------------------------------------------------------------
# Rule to clean temp files
#----------------------------------------------------------------------------------------------------
clean:
	rm -rf compile  *.err *.log csrc  run.do  simv  simv.daidir  ucli.key  vc_hdrs.h  work novas.rc  nWaveLog   vcd2fsdbLog  verilog.vcd  verilog.vcd.fsdb vsim.wlf simv.vdb INCA_libs waves.shm .simvision *.rc cov_work dataset.asdb  fcover.acdb  library.cfg elab_file *.ucdb verdiLog inter.vpd novas.conf wave.ses.png tb.fsdb data
	

