@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\Gowin\1.8\SynplifyPro\lib\generic\gw2a.v":1597:7:1597:9|Synthesizing module GSR in library work.
@N: CG364 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\src\Fra_div\Fra_div.v":3549:7:3549:13|Synthesizing module fra_div in library work.
@N: CG364 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\src\top.v":4:7:4:9|Synthesizing module top in library work.
@N|Running in 64-bit mode
@N: NF107 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\src\top.v":4:7:4:9|Selected library: work cell: top view verilog as top level
@N: NF107 :"E:\ide\IP_TEST_GOLDEN\gwip_ref_design\gwip_ref_design\Gowin_DIVIDER_RefDesign\DIVIDER_31\project\src\top.v":4:7:4:9|Selected library: work cell: top view verilog as top level

