@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":3:19:3:19|Synthesizing module fra_div in library work.
@N|Running in 64-bit mode
@N: NF107 :"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":3:19:3:19|Selected library: work cell: fra_div view verilog as top level
@N: NF107 :"D:\Gowin\1.8\IDE\ipcore\DIVIDER\data\div_wrap.v":3:19:3:19|Selected library: work cell: fra_div view verilog as top level

