Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDS\data\DDS_wrap.v
C:\Gowin\Gowin_V1.9.8.07\IDE\ipcore\DDS\data\DDS_top.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.07
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Created Time Tue Jul 05 16:55:20 2022
Legal Announcement Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module DDS_Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.229s, Peak memory usage = 45.270MB
Running netlist conversion:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.270MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 45.270MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 45.270MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 45.270MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 45.270MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 45.270MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 45.270MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 45.270MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 45.270MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 45.270MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 45.270MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.812s, Elapsed time = 0h 0m 0.823s, Peak memory usage = 56.336MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 56.336MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 56.336MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 56.336MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 70
I/O Buf 41
    IBUF 22
    OBUF 19
Register 175
    DFF 18
    DFFR 93
    DFFPE 13
    DFFC 20
    DFFCE 31
LUT 175
    LUT2 14
    LUT3 63
    LUT4 98
ALU 42
    ALU 42
INV 19
    INV 19
BSRAM 6
    pROMX9 6

Resource Utilization Summary

Resource Usage Utilization
Logic 236(194 LUTs, 42 ALUs) / 20736 1%
Register 175 / 16173 1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 175 / 16173 1%
BSRAM 6 / 46 13%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 10.000 100.0 0.000 5.000 clk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 100.0(MHz) 272.3(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 6.328
Data Arrival Time 4.500
Data Required Time 10.828
From DDS/PhaseAdder/phase_reg_1_s0
To DDS/DDS_LUT/index_addr_8_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 181 clk_ibuf/O
0.863 0.180 tNET RR 1 DDS/PhaseAdder/phase_reg_1_s0/CLK
1.095 0.232 tC2Q RF 6 DDS/PhaseAdder/phase_reg_1_s0/Q
1.332 0.237 tNET FF 1 DDS/DDS_LUT/n126_s2/I1
1.887 0.555 tINS FF 4 DDS/DDS_LUT/n126_s2/F
2.124 0.237 tNET FF 1 DDS/DDS_LUT/n125_s2/I1
2.679 0.555 tINS FF 2 DDS/DDS_LUT/n125_s2/F
2.916 0.237 tNET FF 1 DDS/DDS_LUT/n122_s3/I1
3.471 0.555 tINS FF 1 DDS/DDS_LUT/n122_s3/F
3.708 0.237 tNET FF 1 DDS/DDS_LUT/n122_s1/I1
4.263 0.555 tINS FF 1 DDS/DDS_LUT/n122_s1/F
4.500 0.237 tNET FF 1 DDS/DDS_LUT/index_addr_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 181 clk_ibuf/O
10.863 0.180 tNET RR 1 DDS/DDS_LUT/index_addr_8_s0/CLK
10.828 -0.035 tSu 1 DDS/DDS_LUT/index_addr_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.220, 61.039%; route: 1.185, 32.582%; tC2Q: 0.232, 6.379%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 2

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From DDS/DDS_LUT/mem_out_p_6_s0
To DDS/DDS_LUT/dout_r_9_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 181 clk_ibuf/O
0.863 0.180 tNET RR 1 DDS/DDS_LUT/mem_out_p_6_s0/CLK
1.095 0.232 tC2Q RF 5 DDS/DDS_LUT/mem_out_p_6_s0/Q
1.332 0.237 tNET FF 1 DDS/DDS_LUT/n752_s6/I1
1.887 0.555 tINS FF 3 DDS/DDS_LUT/n752_s6/F
2.124 0.237 tNET FF 1 DDS/DDS_LUT/n759_s5/I1
2.679 0.555 tINS FF 3 DDS/DDS_LUT/n759_s5/F
2.916 0.237 tNET FF 1 DDS/DDS_LUT/n760_s1/I1
3.471 0.555 tINS FF 1 DDS/DDS_LUT/n760_s1/F
3.708 0.237 tNET FF 1 DDS/DDS_LUT/n760_s0/I0
4.225 0.517 tINS FF 1 DDS/DDS_LUT/n760_s0/F
4.462 0.237 tNET FF 1 DDS/DDS_LUT/dout_r_9_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 181 clk_ibuf/O
10.863 0.180 tNET RR 1 DDS/DDS_LUT/dout_r_9_s0/CLK
10.828 -0.035 tSu 1 DDS/DDS_LUT/dout_r_9_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 3

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From DDS/DDS_LUT/mem_out_p_6_s0
To DDS/DDS_LUT/dout_r_10_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 181 clk_ibuf/O
0.863 0.180 tNET RR 1 DDS/DDS_LUT/mem_out_p_6_s0/CLK
1.095 0.232 tC2Q RF 5 DDS/DDS_LUT/mem_out_p_6_s0/Q
1.332 0.237 tNET FF 1 DDS/DDS_LUT/n752_s6/I1
1.887 0.555 tINS FF 3 DDS/DDS_LUT/n752_s6/F
2.124 0.237 tNET FF 1 DDS/DDS_LUT/n759_s5/I1
2.679 0.555 tINS FF 3 DDS/DDS_LUT/n759_s5/F
2.916 0.237 tNET FF 1 DDS/DDS_LUT/n759_s1/I1
3.471 0.555 tINS FF 1 DDS/DDS_LUT/n759_s1/F
3.708 0.237 tNET FF 1 DDS/DDS_LUT/n759_s0/I0
4.225 0.517 tINS FF 1 DDS/DDS_LUT/n759_s0/F
4.462 0.237 tNET FF 1 DDS/DDS_LUT/dout_r_10_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 181 clk_ibuf/O
10.863 0.180 tNET RR 1 DDS/DDS_LUT/dout_r_10_s0/CLK
10.828 -0.035 tSu 1 DDS/DDS_LUT/dout_r_10_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 4

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From DDS/DDS_LUT/mem_out_p_6_s0
To DDS/DDS_LUT/dout_r_12_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 181 clk_ibuf/O
0.863 0.180 tNET RR 1 DDS/DDS_LUT/mem_out_p_6_s0/CLK
1.095 0.232 tC2Q RF 5 DDS/DDS_LUT/mem_out_p_6_s0/Q
1.332 0.237 tNET FF 1 DDS/DDS_LUT/n752_s6/I1
1.887 0.555 tINS FF 3 DDS/DDS_LUT/n752_s6/F
2.124 0.237 tNET FF 1 DDS/DDS_LUT/n757_s4/I1
2.679 0.555 tINS FF 2 DDS/DDS_LUT/n757_s4/F
2.916 0.237 tNET FF 1 DDS/DDS_LUT/n757_s1/I1
3.471 0.555 tINS FF 1 DDS/DDS_LUT/n757_s1/F
3.708 0.237 tNET FF 1 DDS/DDS_LUT/n757_s0/I0
4.225 0.517 tINS FF 1 DDS/DDS_LUT/n757_s0/F
4.462 0.237 tNET FF 1 DDS/DDS_LUT/dout_r_12_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 181 clk_ibuf/O
10.863 0.180 tNET RR 1 DDS/DDS_LUT/dout_r_12_s0/CLK
10.828 -0.035 tSu 1 DDS/DDS_LUT/dout_r_12_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%

Path 5

Path Summary:
Slack 6.366
Data Arrival Time 4.462
Data Required Time 10.828
From DDS/DDS_LUT/mem_out_p_6_s0
To DDS/DDS_LUT/dout_r_14_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.683 0.683 tINS RR 181 clk_ibuf/O
0.863 0.180 tNET RR 1 DDS/DDS_LUT/mem_out_p_6_s0/CLK
1.095 0.232 tC2Q RF 5 DDS/DDS_LUT/mem_out_p_6_s0/Q
1.332 0.237 tNET FF 1 DDS/DDS_LUT/n752_s6/I1
1.887 0.555 tINS FF 3 DDS/DDS_LUT/n752_s6/F
2.124 0.237 tNET FF 1 DDS/DDS_LUT/n752_s4/I1
2.679 0.555 tINS FF 5 DDS/DDS_LUT/n752_s4/F
2.916 0.237 tNET FF 1 DDS/DDS_LUT/n755_s1/I1
3.471 0.555 tINS FF 1 DDS/DDS_LUT/n755_s1/F
3.708 0.237 tNET FF 1 DDS/DDS_LUT/n755_s0/I0
4.225 0.517 tINS FF 1 DDS/DDS_LUT/n755_s0/F
4.462 0.237 tNET FF 1 DDS/DDS_LUT/dout_r_14_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clk
10.000 0.000 tCL RR 1 clk_ibuf/I
10.682 0.683 tINS RR 181 clk_ibuf/O
10.863 0.180 tNET RR 1 DDS/DDS_LUT/dout_r_14_s0/CLK
10.828 -0.035 tSu 1 DDS/DDS_LUT/dout_r_14_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%
Arrival Data Path Delay: cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%
Required Clock Path Delay: cell: 0.683, 79.130%; route: 0.180, 20.870%