Timing Messages

Report Title	Timing Analysis Report
Design File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\impl\gwsynthesis\project.vg
Physical Constraints File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\demo.cst
Timing Constraint File	E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\project.sdc
Version	V1.9.8.07
Part Number	GW2A-LV18PG256C8/I7
Device	GW2A-18
Created Time	Wed Jul 06 11:13:48 2022
Legal Announcement	Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model	Slow 0.95V 85C C8/I7
Hold Delay Model	Fast 1.05V 0C C8/I7
Numbers of Paths Analyzed	1456
Numbers of Endpoints Analyzed	1664
Numbers of Falling Endpoints	3
Numbers of Setup Violated Endpoints	0
Numbers of Hold Violated Endpoints	0

Clock Summary:

Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Objects
SYM_CLK	Base	20.000	50.000	0.000	10.000			SYM_CLK
tck_pad_i	Base	50.000	20.000	0.000	25.000			tck_pad_i

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	SYM_CLK	50.000(MHz)	208.304(MHz)	3	TOP
2	tck_pad_i	20.000(MHz)	171.462(MHz)	6	TOP

Total Negative Slack Summary:

Clock Name	Analysis Type	Endpoints TNS	Number of Endpoints
SYM_CLK	Setup	0.000	0
SYM_CLK	Hold	0.000	0
tck_pad_i	Setup	0.000	0
tck_pad_i	Hold	0.000	0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	4.760	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.949
2	4.760	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.949
3	4.775	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.934
4	4.775	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.934
5	4.775	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.934
6	4.850	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.859
7	4.950	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.759
8	4.950	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.759
9	4.950	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.759
10	4.974	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.735
11	5.182	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.527
12	5.208	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.501
13	5.270	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.439
14	5.348	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.361
15	5.386	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.323
16	5.531	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.179
17	5.569	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.140
18	5.671	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	3.038
19	5.773	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	2.936
20	5.864	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_s0/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	2.845
21	6.058	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q	gw_gao_inst_0/u_la0_top/start_reg_s0/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	2.651
22	6.098	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	2.611
23	6.941	gw_gao_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_ctl_en_0_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	1.768
24	7.172	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	1.537
25	7.190	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D	tck_pad_i:[R]	SYM_CLK:[R]	10.000	1.221	1.519

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.202
2	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.202
3	0.190	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.202
4	0.225	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.474
5	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.612
6	0.363	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.612
7	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.624
8	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.624
9	0.375	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.624
10	0.425	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q	gw_gao_inst_0/u_la0_top/word_count_13_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.436
11	0.427	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.438
12	0.427	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.438
13	0.427	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.438
14	0.427	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.438
15	0.427	gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_0_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.438
16	0.427	gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q	gw_gao_inst_0/u_la0_top/bit_count_1_s1/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.438
17	0.427	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q	gw_gao_inst_0/u_la0_top/word_count_0_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.438
18	0.427	gw_gao_inst_0/u_la0_top/word_count_8_s0/Q	gw_gao_inst_0/u_la0_top/word_count_8_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.438
19	0.428	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.439
20	0.428	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.439
21	0.429	gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_1_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.440
22	0.429	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q	gw_gao_inst_0/u_la0_top/address_counter_7_s0/D	tck_pad_i:[R]	tck_pad_i:[R]	0.000	0.000	0.440
23	0.429	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.440
24	0.429	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/Q	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.440
25	0.430	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D	SYM_CLK:[R]	SYM_CLK:[R]	0.000	0.000	0.441

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
2	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
3	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
4	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
5	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
6	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
7	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
8	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
9	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
10	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
11	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
12	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
13	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
14	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
15	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
16	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
17	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
18	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
19	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
20	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
21	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
22	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
23	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
24	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559
25	8.382	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	10.000	0.023	1.559

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number	Path Slack	From Node	To Node	From Clock	To Clock	Relation	Clock Skew	Data Delay
1	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
2	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
3	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
4	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
5	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
6	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
7	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
8	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
9	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
10	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
11	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
12	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
13	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
14	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
15	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
16	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
17	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
18	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
19	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
20	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
21	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
22	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
23	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
24	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058
25	11.059	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR	SYM_CLK:[F]	SYM_CLK:[R]	-10.000	0.012	1.058

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number	Slack	Actual Width	Required Width	Type	Clock	Objects
1	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	SW2_d_s0
2	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	SW4_d_s0
3	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	data_out_14_s1
4	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	data_out_6_s1
5	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0
6	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0
7	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
8	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	DDS_Top/DDS/DDS_LUT/mem_out_12_s0
9	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	DDS_Top/DDS/DDS_LUT/mem_out_13_s0
10	8.911	9.911	1.000	Low Pulse Width	SYM_CLK	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	4.760
Data Arrival Time	56.096
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.526	0.437	tNET	FF	1	R22C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n257_s3/I3
56.096	0.570	tINS	FR	1	R22C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n257_s3/F
56.096	0.000	tNET	RR	1	R22C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1
60.856	-0.035	tSu		1	R22C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.212, 56.014%; route: 1.505, 38.111%; tC2Q: 0.232, 5.875%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	4.760
Data Arrival Time	56.096
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.526	0.437	tNET	FF	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n253_s1/I3
56.096	0.570	tINS	FR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n253_s1/F
56.096	0.000	tNET	RR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
60.856	-0.035	tSu		1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.212, 56.014%; route: 1.505, 38.111%; tC2Q: 0.232, 5.875%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	4.775
Data Arrival Time	56.081
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.532	0.442	tNET	FF	1	R22C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n256_s1/I3
56.081	0.549	tINS	FR	1	R22C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n256_s1/F
56.081	0.000	tNET	RR	1	R22C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
60.856	-0.035	tSu		1	R22C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.191, 55.697%; route: 1.511, 38.405%; tC2Q: 0.232, 5.898%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	4.775
Data Arrival Time	56.081
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.532	0.442	tNET	FF	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n255_s1/I2
56.081	0.549	tINS	FR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n255_s1/F
56.081	0.000	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
60.856	-0.035	tSu		1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.191, 55.697%; route: 1.511, 38.405%; tC2Q: 0.232, 5.898%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	4.775
Data Arrival Time	56.081
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.532	0.442	tNET	FF	1	R22C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n254_s1/I3
56.081	0.549	tINS	FR	1	R22C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n254_s1/F
56.081	0.000	tNET	RR	1	R22C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1
60.856	-0.035	tSu		1	R22C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_5_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.191, 55.697%; route: 1.511, 38.405%; tC2Q: 0.232, 5.898%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	4.850
Data Arrival Time	56.006
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.535	0.446	tNET	FF	1	R25C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/I0
55.862	0.327	tINS	FR	1	R25C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s4/F
56.006	0.144	tNET	RR	1	R25C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1
60.856	-0.035	tSu		1	R25C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_loop_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.969, 51.020%; route: 1.658, 42.969%; tC2Q: 0.232, 6.011%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	4.950
Data Arrival Time	55.906
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.535	0.446	tNET	FF	1	R24C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n252_s1/I2
55.906	0.371	tINS	FF	1	R24C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n252_s1/F
55.906	0.000	tNET	FF	1	R24C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R24C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
60.856	-0.035	tSu		1	R24C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.013, 53.550%; route: 1.514, 40.278%; tC2Q: 0.232, 6.172%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	4.950
Data Arrival Time	55.906
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.535	0.446	tNET	FF	1	R25C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n251_s1/I3
55.906	0.371	tINS	FF	1	R25C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n251_s1/F
55.906	0.000	tNET	FF	1	R25C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1
60.856	-0.035	tSu		1	R25C27[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.013, 53.550%; route: 1.514, 40.278%; tC2Q: 0.232, 6.172%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	4.950
Data Arrival Time	55.906
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.535	0.446	tNET	FF	1	R24C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n250_s1/I2
55.906	0.371	tINS	FF	1	R24C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n250_s1/F
55.906	0.000	tNET	FF	1	R24C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R24C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
60.856	-0.035	tSu		1	R24C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.013, 53.550%; route: 1.514, 40.278%; tC2Q: 0.232, 6.172%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	4.974
Data Arrival Time	55.882
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.089	0.517	tINS	FF	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.511	0.422	tNET	FF	1	R22C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s1/I3
55.882	0.371	tINS	FF	1	R22C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s1/F
55.882	0.000	tNET	FF	1	R22C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R22C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
60.856	-0.035	tSu		1	R22C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.013, 53.892%; route: 1.490, 39.897%; tC2Q: 0.232, 6.211%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	5.182
Data Arrival Time	55.674
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.572	0.494	tNET	FF	1	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/I1
55.121	0.549	tINS	FR	11	R23C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s4/F
55.303	0.181	tNET	RR	1	R23C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n258_s1/I2
55.674	0.371	tINS	RF	1	R23C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n258_s1/F
55.674	0.000	tNET	FF	1	R23C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R23C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
60.856	-0.035	tSu		1	R23C27[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 2.045, 57.984%; route: 1.250, 35.438%; tC2Q: 0.232, 6.578%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	5.208
Data Arrival Time	55.648
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.635	0.911	tNET	FF	1	R25C29[3][A]	gw_gao_inst_0/u_la0_top/n1720_s2/I1
55.184	0.549	tINS	FR	1	R25C29[3][A]	gw_gao_inst_0/u_la0_top/n1720_s2/F
55.186	0.001	tNET	RR	1	R25C29[1][B]	gw_gao_inst_0/u_la0_top/n1719_s1/I3
55.648	0.462	tINS	RR	1	R25C29[1][B]	gw_gao_inst_0/u_la0_top/n1719_s1/F
55.648	0.000	tNET	RR	1	R25C29[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C29[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1
60.856	-0.035	tSu		1	R25C29[1][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_2_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.687, 48.174%; route: 1.582, 45.199%; tC2Q: 0.232, 6.627%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	5.270
Data Arrival Time	55.586
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.604	0.880	tNET	FF	1	R24C31[3][A]	gw_gao_inst_0/u_la0_top/n1740_s1/I0
54.975	0.371	tINS	FF	1	R24C31[3][A]	gw_gao_inst_0/u_la0_top/n1740_s1/F
54.980	0.004	tNET	FF	1	R24C31[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/I3
55.442	0.462	tINS	FR	1	R24C31[2][B]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s3/F
55.586	0.144	tNET	RR	1	R24C31[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R24C31[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/trigger_seq_start_s1
60.856	-0.035	tSu		1	R24C31[2][A]	gw_gao_inst_0/u_la0_top/trigger_seq_start_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	5
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.509, 43.863%; route: 1.699, 49.392%; tC2Q: 0.232, 6.745%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	5.348
Data Arrival Time	55.508
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/CLK
52.379	0.232	tC2Q	RF	3	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q
53.040	0.661	tNET	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I0
53.595	0.555	tINS	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
54.008	0.413	tNET	FF	1	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.563	0.555	tINS	FF	3	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.815	0.252	tNET	FF	1	R20C26[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/I0
55.364	0.549	tINS	FR	1	R20C26[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s3/F
55.508	0.144	tNET	RR	1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
60.856	-0.035	tSu		1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.659, 49.357%; route: 1.470, 43.741%; tC2Q: 0.232, 6.902%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	5.386
Data Arrival Time	55.469
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/CLK
52.379	0.232	tC2Q	RF	3	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q
53.040	0.661	tNET	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I0
53.595	0.555	tINS	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
54.008	0.413	tNET	FF	1	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.578	0.570	tINS	FR	3	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.755	0.177	tNET	RR	1	R20C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/I1
55.325	0.570	tINS	RR	1	R20C26[3][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s5/F
55.469	0.144	tNET	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CE

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
60.856	-0.035	tSu		1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.695, 51.012%; route: 1.396, 42.005%; tC2Q: 0.232, 6.982%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	5.531
Data Arrival Time	55.325
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/CLK
52.379	0.232	tC2Q	RF	3	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q
53.040	0.661	tNET	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/I0
53.595	0.555	tINS	FF	1	R21C23[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s7/F
54.008	0.413	tNET	FF	1	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/I1
54.578	0.570	tINS	FR	3	R20C25[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s4/F
54.755	0.177	tNET	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n140_s3/I1
55.325	0.570	tINS	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n140_s3/F
55.325	0.000	tNET	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1
60.856	-0.035	tSu		1	R20C26[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_addr_inc_en_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.695, 53.327%; route: 1.252, 39.374%; tC2Q: 0.232, 7.299%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	5.569
Data Arrival Time	55.287
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/CLK
52.379	0.232	tC2Q	RF	2	R26C22[0][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_max_10_s0/Q
52.780	0.402	tNET	FF	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/I1
53.350	0.570	tINS	FR	1	R24C22[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s14/F
53.523	0.172	tNET	RR	1	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/I3
54.078	0.555	tINS	RF	2	R23C22[3][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n249_s7/F
54.738	0.660	tNET	FF	1	R23C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n259_s2/I2
55.287	0.549	tINS	FR	1	R23C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n259_s2/F
55.287	0.000	tNET	RR	1	R23C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R23C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1
60.856	-0.035	tSu		1	R23C27[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_0_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.674, 53.306%; route: 1.234, 39.306%; tC2Q: 0.232, 7.388%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	5.671
Data Arrival Time	55.184
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.635	0.911	tNET	FF	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/n1720_s3/I3
55.184	0.549	tINS	FR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/n1720_s3/F
55.184	0.000	tNET	RR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
60.856	-0.035	tSu		1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.225, 40.313%; route: 1.581, 52.050%; tC2Q: 0.232, 7.637%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	5.773
Data Arrival Time	55.083
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.621	0.896	tNET	FF	1	R25C30[0][A]	gw_gao_inst_0/u_la0_top/n1718_s3/I2
55.083	0.462	tINS	FR	1	R25C30[0][A]	gw_gao_inst_0/u_la0_top/n1718_s3/F
55.083	0.000	tNET	RR	1	R25C30[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C30[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1
60.856	-0.035	tSu		1	R25C30[0][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_3_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.138, 38.747%; route: 1.566, 53.351%; tC2Q: 0.232, 7.902%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	5.864
Data Arrival Time	54.992
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.621	0.896	tNET	FF	1	R24C30[2][A]	gw_gao_inst_0/u_la0_top/n1740_s2/I1
54.992	0.371	tINS	FF	1	R24C30[2][A]	gw_gao_inst_0/u_la0_top/n1740_s2/F
54.992	0.000	tNET	FF	1	R24C30[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R24C30[2][A]	gw_gao_inst_0/u_la0_top/triger_s0/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_s0
60.856	-0.035	tSu		1	R24C30[2][A]	gw_gao_inst_0/u_la0_top/triger_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.047, 36.788%; route: 1.566, 55.057%; tC2Q: 0.232, 8.155%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	6.058
Data Arrival Time	54.798
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0
To	gw_gao_inst_0/u_la0_top/start_reg_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C29[0][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/CLK
52.379	0.232	tC2Q	RF	5	R25C29[0][A]	gw_gao_inst_0/u_la0_top/capture_windows_num_1_s0/Q
52.947	0.568	tNET	FF	2	R26C30[0][B]	gw_gao_inst_0/u_la0_top/n1670_s9/I0
53.496	0.549	tINS	FR	1	R26C30[0][B]	gw_gao_inst_0/u_la0_top/n1670_s9/COUT
53.496	0.000	tNET	RR	2	R26C30[1][A]	gw_gao_inst_0/u_la0_top/n1670_s10/CIN
53.531	0.035	tINS	RF	1	R26C30[1][A]	gw_gao_inst_0/u_la0_top/n1670_s10/COUT
54.249	0.717	tNET	FF	1	R24C30[2][B]	gw_gao_inst_0/u_la0_top/start_reg1_s0/I3
54.798	0.549	tINS	FR	1	R24C30[2][B]	gw_gao_inst_0/u_la0_top/start_reg1_s0/F
54.798	0.000	tNET	RR	1	R24C30[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R24C30[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/start_reg_s0
60.856	-0.035	tSu		1	R24C30[2][B]	gw_gao_inst_0/u_la0_top/start_reg_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.133, 42.750%; route: 1.286, 48.498%; tC2Q: 0.232, 8.752%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	6.098
Data Arrival Time	54.758
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/CLK
52.379	0.232	tC2Q	RF	2	R25C27[2][B]	gw_gao_inst_0/u_la0_top/internal_reg_trig_level_max_0_s0/Q
53.049	0.670	tNET	FF	2	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/I1
53.619	0.570	tINS	FR	1	R26C31[0][B]	gw_gao_inst_0/u_la0_top/n1696_s0/COUT
53.619	0.000	tNET	RR	2	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/CIN
53.654	0.035	tINS	RF	1	R26C31[1][A]	gw_gao_inst_0/u_la0_top/n1697_s0/COUT
53.654	0.000	tNET	FF	2	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/CIN
53.689	0.035	tINS	FF	1	R26C31[1][B]	gw_gao_inst_0/u_la0_top/n1698_s0/COUT
53.689	0.000	tNET	FF	2	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/CIN
53.724	0.035	tINS	FF	6	R26C31[2][A]	gw_gao_inst_0/u_la0_top/n1699_s0/COUT
54.387	0.663	tNET	FF	1	R25C31[2][B]	gw_gao_inst_0/u_la0_top/n1721_s3/I2
54.758	0.371	tINS	FF	1	R25C31[2][B]	gw_gao_inst_0/u_la0_top/n1721_s3/F
54.758	0.000	tNET	FF	1	R25C31[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R25C31[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3
60.856	-0.035	tSu		1	R25C31[2][B]	gw_gao_inst_0/u_la0_top/triger_level_cnt_0_s3

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	4
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 1.047, 40.080%; route: 1.333, 51.035%; tC2Q: 0.232, 8.885%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	6.941
Data Arrival Time	53.915
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_ctl_en_0_s0
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R23C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_ctl_en_0_s0/CLK
52.379	0.232	tC2Q	RF	21	R23C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/internal_reg_match_ctl_en_0_s0/Q
52.819	0.441	tNET	FF	1	R21C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/n531_s10/I2
53.190	0.371	tINS	FF	1	R21C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/n531_s10/F
53.345	0.154	tNET	FF	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/n531_s7/I3
53.915	0.570	tINS	FR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/n531_s7/F
53.915	0.000	tNET	RR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
60.856	-0.035	tSu		1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	3
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 0.941, 53.225%; route: 0.595, 33.652%; tC2Q: 0.232, 13.122%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	7.172
Data Arrival Time	53.684
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R20C19[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/CLK
52.379	0.232	tC2Q	RF	3	R20C19[2][A]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_6_s0/Q
53.313	0.934	tNET	FF	1	R20C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n161_s0/I0
53.684	0.371	tINS	FF	1	R20C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n161_s0/F
53.684	0.000	tNET	FF	1	R20C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R20C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1
60.856	-0.035	tSu		1	R20C27[0][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_6_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 0.371, 24.140%; route: 0.934, 60.764%; tC2Q: 0.232, 15.096%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	7.190
Data Arrival Time	53.666
Data Required Time	60.856
From	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
50.000	50.000					active clock edge time
50.000	0.000					tck_pad_i
50.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
50.682	0.683	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
50.682	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
51.365	0.683	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
52.147	0.782	tNET	RR	1	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/CLK
52.379	0.232	tC2Q	RF	3	R23C26[2][B]	gw_gao_inst_0/u_la0_top/capture_mem_addr_rem_8_s0/Q
53.117	0.738	tNET	FF	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s0/I0
53.666	0.549	tINS	FR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s0/F
53.666	0.000	tNET	RR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
60.000	60.000					active clock edge time
60.000	0.000					SYM_CLK
60.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
60.682	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
60.926	0.243	tNET	RR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
60.891	-0.035	tUnc				gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
60.856	-0.035	tSu		1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	-1.221
Setup Relationship	10.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.365, 63.584%; route: 0.782, 36.416%
Arrival Data Path Delay	cell: 0.549, 36.142%; route: 0.738, 48.585%; tC2Q: 0.232, 15.273%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	0.190
Data Arrival Time	1.062
Data Required Time	0.872
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/CLK
1.062	0.202	tC2Q	RR	10	R20C26[2][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_wr_s1/Q
1.062	0.000	tNET	RR	1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CEA

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s/CLKA
0.872	0.012	tHld		1	BSRAM_R10[5]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_0_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.202, 100.000%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	0.225
Data Arrival Time	1.334
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_18_s0/Q
1.334	0.272	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/DI[0]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[7]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_2_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C24[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C24[2][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_12_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[3]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	0.363
Data Arrival Time	1.471
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C24[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/CLK
1.062	0.202	tC2Q	RR	1	R20C24[1][B]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_11_s0/Q
1.471	0.410	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[2]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.410, 66.974%; tC2Q: 0.202, 33.026%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/CLK
1.062	0.202	tC2Q	RR	1	R22C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_16_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[7]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C25[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/CLK
1.062	0.202	tC2Q	RR	1	R22C25[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_14_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[5]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	0.375
Data Arrival Time	1.483
Data Required Time	1.109
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R18C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/CLK
1.062	0.202	tC2Q	RR	1	R18C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_13_s0/Q
1.483	0.422	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/DI[4]

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s/CLKA
1.109	0.249	tHld		1	BSRAM_R10[6]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_1_s

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.422, 67.614%; tC2Q: 0.202, 32.386%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	0.425
Data Arrival Time	2.353
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/word_count_13_s0
To	gw_gao_inst_0/u_la0_top/word_count_13_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
2.118	0.202	tC2Q	RR	4	R29C22[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/Q
2.121	0.002	tNET	RR	1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/I1
2.353	0.232	tINS	RF	1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_13_s0/F
2.353	0.000	tNET	FF	1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0/CLK
1.927	0.011	tHld		1	R29C22[0][A]	gw_gao_inst_0/u_la0_top/word_count_13_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path11

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
1.062	0.202	tC2Q	RR	6	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/Q
1.065	0.004	tNET	RR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n253_s1/I2
1.297	0.232	tINS	RF	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n253_s1/F
1.297	0.000	tNET	FF	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
0.871	0.011	tHld		1	R22C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
1.062	0.202	tC2Q	RR	4	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/Q
1.065	0.004	tNET	RR	1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n160_s0/I1
1.297	0.232	tINS	RF	1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n160_s0/F
1.297	0.000	tNET	FF	1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1/CLK
0.871	0.011	tHld		1	R20C27[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_7_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
1.062	0.202	tC2Q	RR	4	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/Q
1.065	0.004	tNET	RR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s0/I1
1.297	0.232	tINS	RF	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s0/F
1.297	0.000	tNET	FF	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1/CLK
0.871	0.011	tHld		1	R20C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_8_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	0.427
Data Arrival Time	1.297
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
1.062	0.202	tC2Q	RR	3	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/Q
1.065	0.004	tNET	RR	1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n158_s0/I1
1.297	0.232	tINS	RF	1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n158_s0/F
1.297	0.000	tNET	FF	1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1/CLK
0.871	0.011	tHld		1	R20C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_9_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	0.427
Data Arrival Time	2.354
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/bit_count_0_s1
To	gw_gao_inst_0/u_la0_top/bit_count_0_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
2.118	0.202	tC2Q	RR	7	R30C26[1][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/Q
2.122	0.004	tNET	RR	1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/n488_s1/I0
2.354	0.232	tINS	RF	1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/n488_s1/F
2.354	0.000	tNET	FF	1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1/CLK
1.927	0.011	tHld		1	R30C26[1][A]	gw_gao_inst_0/u_la0_top/bit_count_0_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path16

Path Summary:

Slack	0.427
Data Arrival Time	2.354
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/bit_count_1_s1
To	gw_gao_inst_0/u_la0_top/bit_count_1_s1
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
2.118	0.202	tC2Q	RR	6	R30C25[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/Q
2.122	0.004	tNET	RR	1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/n487_s1/I2
2.354	0.232	tINS	RF	1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/n487_s1/F
2.354	0.000	tNET	FF	1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1/CLK
1.927	0.011	tHld		1	R30C25[1][A]	gw_gao_inst_0/u_la0_top/bit_count_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path17

Path Summary:

Slack	0.427
Data Arrival Time	2.354
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/word_count_0_s0
To	gw_gao_inst_0/u_la0_top/word_count_0_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
2.118	0.202	tC2Q	RR	7	R29C25[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/Q
2.122	0.004	tNET	RR	1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s0/I0
2.354	0.232	tINS	RF	1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_0_s0/F
2.354	0.000	tNET	FF	1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0/CLK
1.927	0.011	tHld		1	R29C25[0][A]	gw_gao_inst_0/u_la0_top/word_count_0_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path18

Path Summary:

Slack	0.427
Data Arrival Time	2.354
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/word_count_8_s0
To	gw_gao_inst_0/u_la0_top/word_count_8_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
2.118	0.202	tC2Q	RR	5	R27C23[0][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/Q
2.122	0.004	tNET	RR	1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_8_s0/I1
2.354	0.232	tINS	RF	1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/data_to_word_counter_8_s0/F
2.354	0.000	tNET	FF	1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0/CLK
1.927	0.011	tHld		1	R27C23[0][A]	gw_gao_inst_0/u_la0_top/word_count_8_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path19

Path Summary:

Slack	0.428
Data Arrival Time	2.355
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/address_counter_10_s0
To	gw_gao_inst_0/u_la0_top/address_counter_10_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
2.118	0.202	tC2Q	RR	7	R26C24[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/Q
2.123	0.005	tNET	RR	1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/I1
2.355	0.232	tINS	RF	1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_10_s0/F
2.355	0.000	tNET	FF	1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0/CLK
1.927	0.011	tHld		1	R26C24[1][A]	gw_gao_inst_0/u_la0_top/address_counter_10_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path20

Path Summary:

Slack	0.428
Data Arrival Time	1.299
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
1.062	0.202	tC2Q	RR	5	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q
1.067	0.005	tNET	RR	1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n166_s0/I1
1.299	0.232	tINS	RF	1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n166_s0/F
1.299	0.000	tNET	FF	1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK
0.871	0.011	tHld		1	R21C26[1][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	0.429
Data Arrival Time	2.356
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/address_counter_1_s0
To	gw_gao_inst_0/u_la0_top/address_counter_1_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
2.118	0.202	tC2Q	RR	10	R26C25[1][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/Q
2.124	0.006	tNET	RR	1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/I2
2.356	0.232	tINS	RF	1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_1_s0/F
2.356	0.000	tNET	FF	1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0/CLK
1.927	0.011	tHld		1	R26C25[1][A]	gw_gao_inst_0/u_la0_top/address_counter_1_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path22

Path Summary:

Slack	0.429
Data Arrival Time	2.356
Data Required Time	1.927
From	gw_gao_inst_0/u_la0_top/address_counter_7_s0
To	gw_gao_inst_0/u_la0_top/address_counter_7_s0
Launch Clk	tck_pad_i:[R]
Latch Clk	tck_pad_i:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
2.118	0.202	tC2Q	RR	10	R26C24[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/Q
2.124	0.006	tNET	RR	1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/I1
2.356	0.232	tINS	RF	1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/data_to_addr_counter_7_s0/F
2.356	0.000	tNET	FF	1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					tck_pad_i
0.000	0.000	tCL	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/I
0.675	0.675	tINS	RR	1	IOR26[A]	gw_gao_inst_0/tck_ibuf/O
0.675	0.000	tNET	RR	1	-	gw_gao_inst_0/u_gw_jtag/tck_pad_i
1.351	0.675	tINS	RR	277	-	gw_gao_inst_0/u_gw_jtag/tck_o
1.916	0.565	tNET	RR	1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0/CLK
1.927	0.011	tHld		1	R26C24[0][A]	gw_gao_inst_0/u_la0_top/address_counter_7_s0

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 1.351, 70.497%; route: 0.565, 29.503%

Path23

Path Summary:

Slack	0.429
Data Arrival Time	1.300
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
To	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
1.062	0.202	tC2Q	RR	8	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/Q
1.068	0.006	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n255_s1/I0
1.300	0.232	tINS	RF	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n255_s1/F
1.300	0.000	tNET	FF	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1/CLK
0.871	0.011	tHld		1	R22C27[0][A]	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_mem_addr_4_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	0.429
Data Arrival Time	1.300
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
To	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
1.062	0.202	tC2Q	RR	5	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/Q
1.068	0.006	tNET	RR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/n1720_s3/I0
1.300	0.232	tINS	RF	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/n1720_s3/F
1.300	0.000	tNET	FF	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1/CLK
0.871	0.011	tHld		1	R25C29[1][A]	gw_gao_inst_0/u_la0_top/triger_level_cnt_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	0.430
Data Arrival Time	1.301
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
To	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1
Launch Clk	SYM_CLK:[R]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
1.062	0.202	tC2Q	RR	7	R22C30[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/Q
1.069	0.007	tNET	RR	1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/n1755_s1/I0
1.301	0.232	tINS	RF	1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/n1755_s1/F
1.301	0.000	tNET	FF	1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/D

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1/CLK
0.871	0.011	tHld		1	R22C30[1][A]	gw_gao_inst_0/u_la0_top/capture_window_sel_1_s1

Path Statistics:

Clock Skew	0.000
Hold Relationship	0.000
Logic Level	2
Arrival Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%
Arrival Data Path Delay	cell: 0.232, 52.568%; route: 0.007, 1.662%; tC2Q: 0.202, 45.770%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
20.891	-0.035	tSu		1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path2

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
20.891	-0.035	tSu		1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path3

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
20.891	-0.035	tSu		1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path4

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
20.891	-0.035	tSu		1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path5

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
20.891	-0.035	tSu		1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path6

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
20.891	-0.035	tSu		1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path7

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK
20.891	-0.035	tSu		1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path8

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
20.891	-0.035	tSu		1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path9

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
20.891	-0.035	tSu		1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path10

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
20.891	-0.035	tSu		1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path11

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLK
20.891	-0.035	tSu		1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path12

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLK
20.891	-0.035	tSu		1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path13

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLK
20.891	-0.035	tSu		1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path14

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLK
20.891	-0.035	tSu		1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path15

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLK
20.891	-0.035	tSu		1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path16

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLK
20.891	-0.035	tSu		1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path17

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLK
20.891	-0.035	tSu		1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path18

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLK
20.891	-0.035	tSu		1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path19

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLK
20.891	-0.035	tSu		1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path20

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
20.891	-0.035	tSu		1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path21

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
20.891	-0.035	tSu		1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path22

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
20.891	-0.035	tSu		1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path23

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
20.891	-0.035	tSu		1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path24

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
20.891	-0.035	tSu		1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Path25

Path Summary:

Slack	8.382
Data Arrival Time	12.508
Data Required Time	20.891
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.181	0.232	tC2Q	FF	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
12.508	1.327	tNET	FF	1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
20.000	20.000					active clock edge time
20.000	0.000					SYM_CLK
20.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
20.683	0.683	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
20.926	0.243	tNET	RR	1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK
20.891	-0.035	tSu		1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Path Statistics:

Clock Skew	-0.023
Setup Relationship	10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.688, 72.453%; route: 0.261, 27.547%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%
Required Clock Path Delay	cell: 0.683, 73.717%; route: 0.243, 26.283%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK
0.871	0.011	tHld		1	R21C30[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path2

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK
0.871	0.011	tHld		1	R20C30[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path3

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK
0.871	0.011	tHld		1	R20C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path4

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK
0.871	0.011	tHld		1	R21C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path5

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK
0.871	0.011	tHld		1	R21C31[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path6

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK
0.871	0.011	tHld		1	R21C31[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path7

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK
0.871	0.011	tHld		1	R21C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path8

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK
0.871	0.011	tHld		1	R20C29[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path9

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK
0.871	0.011	tHld		1	R22C31[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path10

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK
0.871	0.011	tHld		1	R20C28[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path11

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLK
0.871	0.011	tHld		1	R20C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path12

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLK
0.871	0.011	tHld		1	R21C28[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path13

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLK
0.871	0.011	tHld		1	R20C29[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path14

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLK
0.871	0.011	tHld		1	R20C29[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path15

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLK
0.871	0.011	tHld		1	R22C29[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path16

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLK
0.871	0.011	tHld		1	R22C29[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path17

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLK
0.871	0.011	tHld		1	R24C28[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path18

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLK
0.871	0.011	tHld		1	R23C30[2][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path19

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLK
0.871	0.011	tHld		1	R20C25[0][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path20

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0/CLK
0.871	0.011	tHld		1	R20C30[1][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_0_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path21

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0/CLK
0.871	0.011	tHld		1	R20C30[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_1_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path22

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0/CLK
0.871	0.011	tHld		1	R21C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_2_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path23

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0/CLK
0.871	0.011	tHld		1	R22C31[0][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_3_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path24

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK
0.871	0.011	tHld		1	R22C31[2][A]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Path25

Path Summary:

Slack	11.059
Data Arrival Time	11.930
Data Required Time	0.871
From	gw_gao_inst_0/u_la0_top/rst_ao_s1
To	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0
Launch Clk	SYM_CLK:[F]
Latch Clk	SYM_CLK:[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
10.000	10.000					active clock edge time
10.000	0.000					SYM_CLK
10.000	0.000	tCL	FF	1	IOT27[A]	SYM_CLK_ibuf/I
10.677	0.678	tINS	FF	331	IOT27[A]	SYM_CLK_ibuf/O
10.872	0.195	tNET	FF	1	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/CLK
11.074	0.202	tC2Q	FR	85	R25C32[0][A]	gw_gao_inst_0/u_la0_top/rst_ao_s1/Q
11.930	0.856	tNET	RR	1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLEAR

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	LOC	NODE
0.000	0.000					active clock edge time
0.000	0.000					SYM_CLK
0.000	0.000	tCL	RR	1	IOT27[A]	SYM_CLK_ibuf/I
0.675	0.675	tINS	RR	331	IOT27[A]	SYM_CLK_ibuf/O
0.860	0.184	tNET	RR	1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK
0.871	0.011	tHld		1	R20C30[1][B]	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Path Statistics:

Clock Skew	-0.012
Hold Relationship	-10.000
Logic Level	1
Arrival Clock Path Delay	cell: 0.678, 77.694%; route: 0.195, 22.306%
Arrival Data Path Delay	cell: 0.000, 0.000%; route: 0.856, 80.902%; tC2Q: 0.202, 19.098%
Required Clock Path Delay	cell: 0.675, 78.568%; route: 0.184, 21.432%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	SW2_d_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	SW2_d_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	SW2_d_s0/CLK

MPW2

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	SW4_d_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	SW4_d_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	SW4_d_s0/CLK

MPW3

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	data_out_14_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	data_out_14_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	data_out_14_s1/CLK

MPW4

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	data_out_6_s1

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	data_out_6_s1/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	data_out_6_s1/CLK

MPW5

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	gw_gao_inst_0/u_la0_top/internal_reg_start_dly_0_s0/CLK

MPW6

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_0_s0/CLK

MPW7

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_4_s0/CLK

MPW8

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	DDS_Top/DDS/DDS_LUT/mem_out_12_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	DDS_Top/DDS/DDS_LUT/mem_out_12_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	DDS_Top/DDS/DDS_LUT/mem_out_12_s0/CLK

MPW9

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	DDS_Top/DDS/DDS_LUT/mem_out_13_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	DDS_Top/DDS/DDS_LUT/mem_out_13_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	DDS_Top/DDS/DDS_LUT/mem_out_13_s0/CLK

MPW10

MPW Summary:

Slack:	8.911
Actual Width:	9.911
Required Width:	1.000
Type:	Low Pulse Width
Clock:	SYM_CLK
Objects:	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0

Late clock Path:

AT	DELAY	TYPE	RF	NODE
10.000	0.000			active clock edge time
10.000	0.000			SYM_CLK
10.000	0.000	tCL	FF	SYM_CLK_ibuf/I
10.688	0.688	tINS	FF	SYM_CLK_ibuf/O
10.949	0.261	tNET	FF	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK

Early clock Path:

AT	DELAY	TYPE	RF	NODE
20.000	0.000			active clock edge time
20.000	0.000			SYM_CLK
20.000	0.000	tCL	RR	SYM_CLK_ibuf/I
20.676	0.675	tINS	RR	SYM_CLK_ibuf/O
20.860	0.184	tNET	RR	gw_gao_inst_0/u_la0_top/u_ao_match_0/trig_dly_in_5_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT	NET NAME	WORST SLACK	MAX DELAY
331	SYM_CLK_d	8.382	0.261
277	control0[0]	4.760	0.912
85	rst_ao	8.382	1.327
41	n20_3	46.174	1.916
37	addr_tx[12]	16.300	1.602
36	jtag_strobe_i	44.493	1.324
35	op_reg_en	44.887	1.190
35	n465_6	16.430	0.894
32	crc_28_7	45.148	0.693
30	n610_6	45.194	1.137

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC	ROUTE CONGESTIONS
R25C23	87.50%
R11C20	86.11%
R22C24	86.11%
R22C27	86.11%
R11C26	84.72%
R34C29	83.33%
R34C30	83.33%
R35C20	83.33%
R21C25	83.33%
R22C29	83.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type	State	Detail Command
TC_CLOCK	Actived	create_clock -name SYM_CLK -period 20 -waveform {0 10} [get_ports {SYM_CLK}]
TC_CLOCK	Actived	create_clock -name tck_pad_i -period 50 -waveform {0 25} [get_ports {tck_pad_i}]
TC_FALSE_PATH	Actived	set_false_path -from [get_clocks {SYM_CLK}] -to [get_clocks {tck_pad_i}]