| Report Title |
Power Analysis Report |
| Design File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\impl\gwsynthesis\project.vg |
| Physical Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\demo.cst |
| Timing Constraints File |
E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\project.sdc |
| Version |
V1.9.8.07 |
| Part Number |
GW2A-LV18PG256C8/I7 |
| Device |
GW2A-18 |
| Created Time |
Wed Jul 06 11:13:48 2022
|
| Legal Announcement |
Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved. |
| Total Power (mW) |
187.730 |
| Quiescent Power (mW) |
162.927 |
| Dynamic Power (mW) |
24.803 |
| Junction Temperature |
31.011 |
| Theta JA |
32.020 |
| Max Allowed Ambient Temperature |
78.989 |
| Default IO Toggle Rate |
0.125 |
Default Remain Toggle Rate |
0.125 |
| Use Vectorless Estimation |
false |
| Filter Glitches |
false |
| Related Vcd File |
|
| Related Saif File |
|
| Use Custom Theta JA |
false |
| Air Flow |
LFM_0 |
| Heat Sink |
None |
| Use Custom Theta SA |
false |
| Board Thermal Model |
None |
| Use Custom Theta JB |
false |
| Ambient Temperature |
25.000
|
| Voltage Source |
Voltage |
Dynamic Current(mA) |
Quiescent Current(mA) |
Power(mW) |
| VCC |
1.000 |
20.729 |
102.666 |
123.395 |
| VCCX |
2.500 |
0.950 |
23.366 |
60.788 |
| VCCO18 |
1.800 |
0.944 |
1.026 |
3.547 |
| Block Type |
Total Power(mW) |
Static Power(mW) |
Average Toggle Rate(millions of transitions/sec) |
| Logic |
0.465 |
NA |
4.445 |
| IO |
10.515
| 5.487
| 8.448
|
| BSRAM |
19.291
| NA |
NA |
| Hierarchy Entity |
Total Power(mW) |
Block Dynamic Power(mW) |
| DDS_exp |
19.757 |
19.757(19.747) |
| DDS_exp/DDS_Top/ |
4.280 |
4.280(4.280) |
| DDS_exp/DDS_Top/DDS/ |
4.280 |
4.280(4.280) |
| DDS_exp/DDS_Top/DDS/DDS_LUT/ |
4.206 |
4.206(0.000) |
| DDS_exp/DDS_Top/DDS/PhaseAdder/ |
0.059 |
0.059(0.000) |
| DDS_exp/DDS_Top/DDS/ctrl/ |
0.015 |
0.015(0.000) |
| DDS_exp/gw_gao_inst_0/ |
15.466 |
15.466(15.466) |
| DDS_exp/gw_gao_inst_0/u_icon_top/ |
0.005 |
0.005(0.000) |
| DDS_exp/gw_gao_inst_0/u_la0_top/ |
15.461 |
15.461(15.361) |
| DDS_exp/gw_gao_inst_0/u_la0_top/u_ao_crc32/ |
0.010 |
0.010(0.000) |
| DDS_exp/gw_gao_inst_0/u_la0_top/u_ao_match_0/ |
0.024 |
0.024(0.000) |
| DDS_exp/gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/ |
15.327 |
15.327(0.000) |
| Clock Domain |
Clock Frequency(Mhz) |
Total Dynamic Power(mW) |
| SYM_CLK |
50.000 |
15.325 |
| tck_pad_i |
20.000 |
4.451 |