Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\DDS_exp.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\src\dds\dds.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v C:\Gowin\Gowin_V1.9.8.07\IDE\data\ipcores\gw_jtag.v E:\myWork\IP\releaseVerify\RefDesign\DSP_Math\Gowin_DDS_RefDesign\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v |
| GowinSynthesis Constraints File | --- |
| Version | GowinSynthesis V1.9.8.07 |
| Part Number | GW2A-LV18PG256C8/I7 |
| Device | GW2A-18 |
| Created Time | Tue Jul 05 16:55:31 2022 |
| Legal Announcement | Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | DDS_exp |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.609s, Elapsed time = 0h 0m 0.548s, Peak memory usage = 131.793MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 131.793MB Optimizing Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 131.793MB Optimizing Phase 2: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 131.793MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 131.793MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 131.793MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 131.793MB Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 131.793MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.036s, Peak memory usage = 131.793MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 131.793MB Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 131.793MB Tech-Mapping Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 145.586MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.077s, Peak memory usage = 145.586MB Generate output files: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.065s, Peak memory usage = 145.586MB |
| Total Time and Memory Usage | CPU time = 0h 0m 3s, Elapsed time = 0h 0m 2s, Peak memory usage = 145.586MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 29 |
| I/O Buf | 29 |
| IBUF | 9 |
| OBUF | 20 |
| Register | 563 |
| DFF | 56 |
| DFFR | 93 |
| DFFP | 1 |
| DFFPE | 46 |
| DFFC | 102 |
| DFFCE | 259 |
| DFFNP | 2 |
| DFFNC | 4 |
| LUT | 604 |
| LUT2 | 70 |
| LUT3 | 178 |
| LUT4 | 356 |
| MUX | 1 |
| MUX16 | 1 |
| ALU | 52 |
| ALU | 52 |
| INV | 21 |
| INV | 21 |
| BSRAM | 9 |
| SDPX9B | 3 |
| pROMX9 | 6 |
| Black Box | 1 |
| GW_JTAG | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 685(633 LUTs, 52 ALUs) / 20736 | 3% |
| Register | 563 / 16173 | 3% |
| --Register as Latch | 0 / 16173 | 0% |
| --Register as FF | 563 / 16173 | 3% |
| BSRAM | 9 / 46 | 20% |
Timing
Clock Summary:
| Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|
| SYM_CLK | Base | 10.000 | 100.0 | 0.000 | 5.000 | SYM_CLK_ibuf/I |
Max Frequency Summary:
| No. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | SYM_CLK | 100.0(MHz) | 242.7(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.880 |
| Data Arrival Time | 4.948 |
| Data Required Time | 10.828 |
| From | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1 |
| To | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_1_s1/Q |
| 1.332 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n163_s1/I1 |
| 1.887 | 0.555 | tINS | FF | 4 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n163_s1/F |
| 2.124 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n161_s1/I2 |
| 2.577 | 0.453 | tINS | FF | 3 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n161_s1/F |
| 2.814 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s1/I2 |
| 3.267 | 0.453 | tINS | FF | 2 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n159_s1/F |
| 3.504 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n157_s1/I2 |
| 3.957 | 0.453 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n157_s1/F |
| 4.194 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n157_s3/I0 |
| 4.711 | 0.517 | tINS | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/n157_s3/F |
| 4.948 | 0.237 | tNET | FF | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1/CLK |
| 10.828 | -0.035 | tSu | 1 | gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/capture_length_10_s1 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.431, 59.511%; route: 1.422, 34.810%; tC2Q: 0.232, 5.679% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 2
Path Summary:| Slack | 6.328 |
| Data Arrival Time | 4.500 |
| Data Required Time | 10.828 |
| From | DDS_Top/DDS/PhaseAdder/phase_reg_1_s0 |
| To | DDS_Top/DDS/DDS_LUT/index_addr_8_s0 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/PhaseAdder/phase_reg_1_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 6 | DDS_Top/DDS/PhaseAdder/phase_reg_1_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n126_s2/I1 |
| 1.887 | 0.555 | tINS | FF | 4 | DDS_Top/DDS/DDS_LUT/n126_s2/F |
| 2.124 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n125_s2/I1 |
| 2.679 | 0.555 | tINS | FF | 2 | DDS_Top/DDS/DDS_LUT/n125_s2/F |
| 2.916 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n122_s3/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n122_s3/F |
| 3.708 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n122_s1/I1 |
| 4.263 | 0.555 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n122_s1/F |
| 4.500 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/index_addr_8_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/index_addr_8_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | DDS_Top/DDS/DDS_LUT/index_addr_8_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.220, 61.039%; route: 1.185, 32.582%; tC2Q: 0.232, 6.379% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 3
Path Summary:| Slack | 6.366 |
| Data Arrival Time | 4.462 |
| Data Required Time | 10.828 |
| From | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0 |
| To | DDS_Top/DDS/DDS_LUT/dout_r_9_s0 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n752_s6/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | DDS_Top/DDS/DDS_LUT/n752_s6/F |
| 2.124 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s5/I1 |
| 2.679 | 0.555 | tINS | FF | 3 | DDS_Top/DDS/DDS_LUT/n759_s5/F |
| 2.916 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n760_s1/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n760_s1/F |
| 3.708 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n760_s0/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n760_s0/F |
| 4.462 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/dout_r_9_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/dout_r_9_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | DDS_Top/DDS/DDS_LUT/dout_r_9_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 4
Path Summary:| Slack | 6.366 |
| Data Arrival Time | 4.462 |
| Data Required Time | 10.828 |
| From | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0 |
| To | DDS_Top/DDS/DDS_LUT/dout_r_10_s0 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n752_s6/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | DDS_Top/DDS/DDS_LUT/n752_s6/F |
| 2.124 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s5/I1 |
| 2.679 | 0.555 | tINS | FF | 3 | DDS_Top/DDS/DDS_LUT/n759_s5/F |
| 2.916 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s1/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s1/F |
| 3.708 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s0/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n759_s0/F |
| 4.462 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/dout_r_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/dout_r_10_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | DDS_Top/DDS/DDS_LUT/dout_r_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
Path 5
Path Summary:| Slack | 6.366 |
| Data Arrival Time | 4.462 |
| Data Required Time | 10.828 |
| From | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0 |
| To | DDS_Top/DDS/DDS_LUT/dout_r_12_s0 |
| Launch Clk | SYM_CLK[R] |
| Latch Clk | SYM_CLK[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | SYM_CLK | |||
| 0.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 0.683 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 0.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/CLK |
| 1.095 | 0.232 | tC2Q | RF | 5 | DDS_Top/DDS/DDS_LUT/mem_out_p_6_s0/Q |
| 1.332 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n752_s6/I1 |
| 1.887 | 0.555 | tINS | FF | 3 | DDS_Top/DDS/DDS_LUT/n752_s6/F |
| 2.124 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n757_s4/I1 |
| 2.679 | 0.555 | tINS | FF | 2 | DDS_Top/DDS/DDS_LUT/n757_s4/F |
| 2.916 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n757_s1/I1 |
| 3.471 | 0.555 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n757_s1/F |
| 3.708 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/n757_s0/I0 |
| 4.225 | 0.517 | tINS | FF | 1 | DDS_Top/DDS/DDS_LUT/n757_s0/F |
| 4.462 | 0.237 | tNET | FF | 1 | DDS_Top/DDS/DDS_LUT/dout_r_12_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | SYM_CLK | |||
| 10.000 | 0.000 | tCL | RR | 1 | SYM_CLK_ibuf/I |
| 10.682 | 0.683 | tINS | RR | 331 | SYM_CLK_ibuf/O |
| 10.863 | 0.180 | tNET | RR | 1 | DDS_Top/DDS/DDS_LUT/dout_r_12_s0/CLK |
| 10.828 | -0.035 | tSu | 1 | DDS_Top/DDS/DDS_LUT/dout_r_12_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 10.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |
| Arrival Data Path Delay: | cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446% |
| Required Clock Path Delay: | cell: 0.683, 79.130%; route: 0.180, 20.870% |