Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Users\vito\Desktop\pdm2pcm_update\Gowin_PDM2PCM_RefDesign\5A\project\src\Top.v
C:\Users\vito\Desktop\pdm2pcm_update\Gowin_PDM2PCM_RefDesign\5A\project\src\clk_div_even.v
C:\Users\vito\Desktop\pdm2pcm_update\Gowin_PDM2PCM_RefDesign\5A\project\src\pdm2pcm\pdm2pcm.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.11.03_x64\IDE\data\ipcores\gw_jtag.v
C:\Users\vito\Desktop\pdm2pcm_update\Gowin_PDM2PCM_RefDesign\5A\project\impl\gwsynthesis\RTL_GAO\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.03 (64-bit)
Part Number GW5A-LV25UG324ES
Device GW5A-25
Device Version A
Created Time Wed Jun 18 11:12:11 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module Top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.796s, Elapsed time = 0h 0m 0.798s, Peak memory usage = 205.238MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.105s, Peak memory usage = 205.238MB
    Optimizing Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 205.238MB
    Optimizing Phase 2: CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.341s, Peak memory usage = 205.238MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.165s, Peak memory usage = 205.238MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 205.238MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.034s, Peak memory usage = 205.238MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 205.238MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.439s, Peak memory usage = 210.512MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.129s, Peak memory usage = 210.512MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 210.512MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 236.273MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.216s, Peak memory usage = 236.273MB
Generate output files:
    CPU time = 0h 0m 0.328s, Elapsed time = 0h 0m 0.353s, Peak memory usage = 243.035MB
Total Time and Memory Usage CPU time = 0h 0m 14s, Elapsed time = 0h 0m 14s, Peak memory usage = 243.035MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 32
I/O Buf 32
    IBUF 5
    OBUF 27
Register 2556
    DFFRE 26
    DFFPE 45
    DFFCE 2485
LUT 2958
    LUT2 291
    LUT3 620
    LUT4 2047
MUX 1
    MUX16 1
ALU 807
    ALU 807
INV 16
    INV 16
DSP
    MULTALU27X18 1
BSRAM 34
    SDPB 32
    SDPX9B 1
    pROMX9 1
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 3789(2982 LUT, 807 ALU) / 23040 17%
Register 2556 / 23685 11%
  --Register as Latch 0 / 23685 0%
  --Register as FF 2556 / 23685 11%
BSRAM 34 / 56 61%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 SYM_CLK Base 10.000 100.000 0.000 5.000 SYM_CLK_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 SYM_CLK 100.000(MHz) 93.251(MHz) 12 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.724
Data Arrival Time 11.035
Data Required Time 10.311
From drom_addr_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
0.375 0.375 tNET RR 1 drom_addr_12_s0/CLK
0.757 0.382 tC2Q RR 407 drom_addr_12_s0/Q
1.132 0.375 tNET RR 1 n124_s28841/I0
1.659 0.526 tINS RR 21 n124_s28841/F
2.034 0.375 tNET RR 1 n124_s30645/I2
2.495 0.461 tINS RR 26 n124_s30645/F
2.870 0.375 tNET RR 1 n124_s28646/I0
3.396 0.526 tINS RR 1 n124_s28646/F
3.771 0.375 tNET RR 1 n124_s30433/I0
4.298 0.526 tINS RR 1 n124_s30433/F
4.673 0.375 tNET RR 1 n124_s30067/I2
5.134 0.461 tINS RR 1 n124_s30067/F
5.509 0.375 tNET RR 1 n124_s29382/I1
6.025 0.516 tINS RR 1 n124_s29382/F
6.400 0.375 tNET RR 1 n124_s29026/I1
6.916 0.516 tINS RR 1 n124_s29026/F
7.291 0.375 tNET RR 1 n124_s28886/I2
7.753 0.461 tINS RR 1 n124_s28886/F
8.128 0.375 tNET RR 1 n124_s30775/I3
8.390 0.262 tINS RR 1 n124_s30775/F
8.765 0.375 tNET RR 1 n124_s30752/I0
8.901 0.136 tINS RR 1 n124_s30752/O
9.276 0.375 tNET RR 1 n124_s30741/I1
9.363 0.086 tINS RR 1 n124_s30741/O
9.738 0.375 tNET RR 1 n124_s28807/I0
9.824 0.086 tINS RR 1 n124_s28807/O
10.199 0.375 tNET RR 1 u_PDM2PCM_Top_26_s0/I2
10.660 0.461 tINS RR 8 u_PDM2PCM_Top_26_s0/F
11.035 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.027, 47.162%; route: 5.250, 49.250%; tC2Q: 0.382, 3.588%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack -0.724
Data Arrival Time 11.035
Data Required Time 10.311
From drom_addr_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
0.375 0.375 tNET RR 1 drom_addr_12_s0/CLK
0.757 0.382 tC2Q RR 407 drom_addr_12_s0/Q
1.132 0.375 tNET RR 1 n124_s28841/I0
1.659 0.526 tINS RR 21 n124_s28841/F
2.034 0.375 tNET RR 1 n124_s30645/I2
2.495 0.461 tINS RR 26 n124_s30645/F
2.870 0.375 tNET RR 1 n124_s28646/I0
3.396 0.526 tINS RR 1 n124_s28646/F
3.771 0.375 tNET RR 1 n124_s30433/I0
4.298 0.526 tINS RR 1 n124_s30433/F
4.673 0.375 tNET RR 1 n124_s30067/I2
5.134 0.461 tINS RR 1 n124_s30067/F
5.509 0.375 tNET RR 1 n124_s29382/I1
6.025 0.516 tINS RR 1 n124_s29382/F
6.400 0.375 tNET RR 1 n124_s29026/I1
6.916 0.516 tINS RR 1 n124_s29026/F
7.291 0.375 tNET RR 1 n124_s28886/I2
7.753 0.461 tINS RR 1 n124_s28886/F
8.128 0.375 tNET RR 1 n124_s30775/I3
8.390 0.262 tINS RR 1 n124_s30775/F
8.765 0.375 tNET RR 1 n124_s30752/I0
8.901 0.136 tINS RR 1 n124_s30752/O
9.276 0.375 tNET RR 1 n124_s30741/I1
9.363 0.086 tINS RR 1 n124_s30741/O
9.738 0.375 tNET RR 1 n124_s28807/I0
9.824 0.086 tINS RR 1 n124_s28807/O
10.199 0.375 tNET RR 1 u_PDM2PCM_Top_26_s0/I2
10.660 0.461 tINS RR 8 u_PDM2PCM_Top_26_s0/F
11.035 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.027, 47.162%; route: 5.250, 49.250%; tC2Q: 0.382, 3.588%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack -0.724
Data Arrival Time 11.035
Data Required Time 10.311
From drom_addr_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
0.375 0.375 tNET RR 1 drom_addr_12_s0/CLK
0.757 0.382 tC2Q RR 407 drom_addr_12_s0/Q
1.132 0.375 tNET RR 1 n124_s28841/I0
1.659 0.526 tINS RR 21 n124_s28841/F
2.034 0.375 tNET RR 1 n124_s30645/I2
2.495 0.461 tINS RR 26 n124_s30645/F
2.870 0.375 tNET RR 1 n124_s28646/I0
3.396 0.526 tINS RR 1 n124_s28646/F
3.771 0.375 tNET RR 1 n124_s30433/I0
4.298 0.526 tINS RR 1 n124_s30433/F
4.673 0.375 tNET RR 1 n124_s30067/I2
5.134 0.461 tINS RR 1 n124_s30067/F
5.509 0.375 tNET RR 1 n124_s29382/I1
6.025 0.516 tINS RR 1 n124_s29382/F
6.400 0.375 tNET RR 1 n124_s29026/I1
6.916 0.516 tINS RR 1 n124_s29026/F
7.291 0.375 tNET RR 1 n124_s28886/I2
7.753 0.461 tINS RR 1 n124_s28886/F
8.128 0.375 tNET RR 1 n124_s30775/I3
8.390 0.262 tINS RR 1 n124_s30775/F
8.765 0.375 tNET RR 1 n124_s30752/I0
8.901 0.136 tINS RR 1 n124_s30752/O
9.276 0.375 tNET RR 1 n124_s30741/I1
9.363 0.086 tINS RR 1 n124_s30741/O
9.738 0.375 tNET RR 1 n124_s28807/I0
9.824 0.086 tINS RR 1 n124_s28807/O
10.199 0.375 tNET RR 1 u_PDM2PCM_Top_26_s0/I2
10.660 0.461 tINS RR 8 u_PDM2PCM_Top_26_s0/F
11.035 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.027, 47.162%; route: 5.250, 49.250%; tC2Q: 0.382, 3.588%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack -0.724
Data Arrival Time 11.035
Data Required Time 10.311
From drom_addr_12_s0
To gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
0.375 0.375 tNET RR 1 drom_addr_12_s0/CLK
0.757 0.382 tC2Q RR 407 drom_addr_12_s0/Q
1.132 0.375 tNET RR 1 n124_s28841/I0
1.659 0.526 tINS RR 21 n124_s28841/F
2.034 0.375 tNET RR 1 n124_s30645/I2
2.495 0.461 tINS RR 26 n124_s30645/F
2.870 0.375 tNET RR 1 n124_s28646/I0
3.396 0.526 tINS RR 1 n124_s28646/F
3.771 0.375 tNET RR 1 n124_s30433/I0
4.298 0.526 tINS RR 1 n124_s30433/F
4.673 0.375 tNET RR 1 n124_s30067/I2
5.134 0.461 tINS RR 1 n124_s30067/F
5.509 0.375 tNET RR 1 n124_s29382/I1
6.025 0.516 tINS RR 1 n124_s29382/F
6.400 0.375 tNET RR 1 n124_s29026/I1
6.916 0.516 tINS RR 1 n124_s29026/F
7.291 0.375 tNET RR 1 n124_s28886/I2
7.753 0.461 tINS RR 1 n124_s28886/F
8.128 0.375 tNET RR 1 n124_s30775/I3
8.390 0.262 tINS RR 1 n124_s30775/F
8.765 0.375 tNET RR 1 n124_s30752/I0
8.901 0.136 tINS RR 1 n124_s30752/O
9.276 0.375 tNET RR 1 n124_s30741/I1
9.363 0.086 tINS RR 1 n124_s30741/O
9.738 0.375 tNET RR 1 n124_s28807/I0
9.824 0.086 tINS RR 1 n124_s28807/O
10.199 0.375 tNET RR 1 u_PDM2PCM_Top_26_s0/I2
10.660 0.461 tINS RR 8 u_PDM2PCM_Top_26_s0/F
11.035 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
10.375 0.375 tNET RR 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0/CLK
10.311 -0.064 tSu 1 gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_dly_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.027, 47.162%; route: 5.250, 49.250%; tC2Q: 0.382, 3.588%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack -0.724
Data Arrival Time 11.035
Data Required Time 10.311
From drom_addr_12_s0
To u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0
Launch Clk SYM_CLK[R]
Latch Clk SYM_CLK[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 SYM_CLK
0.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
0.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
0.375 0.375 tNET RR 1 drom_addr_12_s0/CLK
0.757 0.382 tC2Q RR 407 drom_addr_12_s0/Q
1.132 0.375 tNET RR 1 n124_s28841/I0
1.659 0.526 tINS RR 21 n124_s28841/F
2.034 0.375 tNET RR 1 n124_s30645/I2
2.495 0.461 tINS RR 26 n124_s30645/F
2.870 0.375 tNET RR 1 n124_s28646/I0
3.396 0.526 tINS RR 1 n124_s28646/F
3.771 0.375 tNET RR 1 n124_s30433/I0
4.298 0.526 tINS RR 1 n124_s30433/F
4.673 0.375 tNET RR 1 n124_s30067/I2
5.134 0.461 tINS RR 1 n124_s30067/F
5.509 0.375 tNET RR 1 n124_s29382/I1
6.025 0.516 tINS RR 1 n124_s29382/F
6.400 0.375 tNET RR 1 n124_s29026/I1
6.916 0.516 tINS RR 1 n124_s29026/F
7.291 0.375 tNET RR 1 n124_s28886/I2
7.753 0.461 tINS RR 1 n124_s28886/F
8.128 0.375 tNET RR 1 n124_s30775/I3
8.390 0.262 tINS RR 1 n124_s30775/F
8.765 0.375 tNET RR 1 n124_s30752/I0
8.901 0.136 tINS RR 1 n124_s30752/O
9.276 0.375 tNET RR 1 n124_s30741/I1
9.363 0.086 tINS RR 1 n124_s30741/O
9.738 0.375 tNET RR 1 n124_s28807/I0
9.824 0.086 tINS RR 1 n124_s28807/O
10.199 0.375 tNET RR 1 u_PDM2PCM_Top_26_s0/I2
10.660 0.461 tINS RR 8 u_PDM2PCM_Top_26_s0/F
11.035 0.375 tNET RR 1 u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 SYM_CLK
10.000 0.000 tCL RR 1 SYM_CLK_ibuf/I
10.000 0.000 tINS RR 2319 SYM_CLK_ibuf/O
10.375 0.375 tNET RR 1 u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0/CLK
10.311 -0.064 tSu 1 u_PDM2PCM_Top/u_pdm2pcm/u_syn_signal/data_r1_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 5.027, 47.162%; route: 5.250, 49.250%; tC2Q: 0.382, 3.588%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%