@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG1350 :	| Running Verilog Compiler in Multiple File Compilation Unit mode
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\generic\gw2a.v":1908:7:1908:9|Synthesizing module GSR in library work.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\sdio_slave_controller\sdio_slave_controller.v":51061:7:51061:31|Synthesizing module SDIO_Slave_Controller_Top in library work.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":1:7:1:24|Synthesizing module user_sdio_cmd53_if in library work.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd52_if.v":1:7:1:24|Synthesizing module user_sdio_cmd52_if in library work.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":9:7:9:22|Synthesizing module syn_hyper_source in library __hyper__lib__.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_tuning_pattern.v":1:7:1:25|Synthesizing module user_tuning_pattern in library work.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\button.v":1:7:1:12|Synthesizing module deUstb in library work.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v":1:7:1:27|Synthesizing module user_cpu_slave_reg_if in library work.
@N: CG179 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v":89:15:89:17|Removing redundant assignment.
@N: CG364 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\top.v":2:7:2:9|Synthesizing module top in library work.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CG364 :"D:\Gowin\sdio_sweg\SynplifyPro\lib\vlog\hypermods.v":16:7:16:23|Synthesizing module syn_hyper_connect in library __hyper__lib__.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v":3:10:3:16|Input cpu_rst is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v":10:17:10:31|Input slv_cpu_rd_data is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_cpu_slave_reg_if.v":12:10:12:20|Input slv_cpu_err is unused.
@N: CL201 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":102:0:102:5|Trying to extract state machine for register c_state.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":9:16:9:32|Input sdio_cmd53_fn_num is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":10:16:10:30|Input sdio_cmd53_addr is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":12:16:12:33|Input sdio_cmd53_op_code is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":15:16:15:33|Input sdio_cmd53_wr_data is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":17:16:17:31|Input sdio_cmd53_wr_ok is unused.
@N: CL159 :"C:\Users\guitong\Desktop\sdio_reference_design\Gowin_SDIO_Slave_Controller_RefDesign\project\src\user_sdio_cmd53_if.v":23:16:23:32|Input sdio_cmd53_rd_end is unused.
@N|Running in 64-bit mode
@N: NF107 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\top.v":2:7:2:9|Selected library: work cell: top view verilog as top level
@N: NF107 :"c:\users\guitong\desktop\sdio_reference_design\gowin_sdio_slave_controller_refdesign\project\src\top.v":2:7:2:9|Selected library: work cell: top view verilog as top level

