Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\RFFE\data\rffe.v
C:\Gowin\Gowin_V1.9.8.01\IDE\ipcore\RFFE\data\rffe_wrapper.v
GowinSynthesis Constraints File ---
Version GowinSynthesis V1.9.8.01
Part Number GW2A-LV18LQ144C7/I6
Device GW2A-18
Created Time Mon Nov 01 10:37:44 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module rffe_slave
Synthesis Process Running parser:
    CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.224s, Peak memory usage = 43.285MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 43.285MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 43.285MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 43.285MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 43.285MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 43.285MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 43.285MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 43.285MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 43.285MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 43.285MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 43.285MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 43.285MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 54.328MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 54.328MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.027s, Peak memory usage = 54.328MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 54.328MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 64
I/O Buf 64
    IBUF 15
    OBUF 48
    IOBUF 1
Register 231
    DFF 27
    DFFE 12
    DFFS 1
    DFFR 11
    DFFRE 55
    DFFC 10
    DFFN 12
    DFFNE 42
    DFFNSE 2
    DFFNR 2
    DFFNRE 28
    DFFNC 24
    DFFNCE 5
LUT 248
    LUT2 30
    LUT3 71
    LUT4 147
ALU 39
    ALU 39
INV 9
    INV 9

Resource Utilization Summary

Resource Usage Utilization
Logic 296(257 LUTs, 39 ALUs) / 20736 1%
Register 231 / 15909 1%
  --Register as Latch 0 / 15909 0%
  --Register as FF 231 / 15909 1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
i_clk Base 10.000 100.0 0.000 5.000 i_clk_ibuf/I
i_sclk Base 10.000 100.0 0.000 5.000 i_sclk_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 i_clk 100.0(MHz) 220.1(MHz) 5 TOP
2 i_sclk 100.0(MHz) 144.1(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 0.220
Data Arrival Time 10.779
Data Required Time 10.999
From u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1
To u_rffe_wrapper/u_rffe_slave_inf/o_rd_en_s0
Launch Clk i_sclk[R]
Latch Clk i_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 i_sclk
5.000 0.000 tCL FF 1 i_sclk_ibuf/I
5.859 0.859 tINS FF 126 i_sclk_ibuf/O
6.156 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/CLK
6.446 0.290 tC2Q FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/Q
6.742 0.296 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/I0
7.428 0.686 tINS FR 1 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/COUT
7.428 0.000 tNET RR 2 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/CIN
7.472 0.044 tINS RF 1 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/COUT
7.472 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/CIN
7.516 0.044 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/COUT
7.516 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/CIN
7.560 0.044 tINS FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/COUT
7.856 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/I1
8.550 0.694 tINS FF 6 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/F
8.846 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/I0
9.493 0.646 tINS FF 20 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/F
9.789 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1501_s1/I1
10.483 0.694 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1501_s1/F
10.779 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_en_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 i_clk
10.000 0.000 tCL RR 1 i_clk_ibuf/I
10.853 0.853 tINS RR 106 i_clk_ibuf/O
11.078 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_en_s0/CLK
11.043 -0.035 tUnc u_rffe_wrapper/u_rffe_slave_inf/o_rd_en_s0
10.999 -0.044 tSu 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_en_s0
Path Statistics:
Clock Skew: -0.077
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%
Arrival Data Path Delay: cell: 2.852, 61.688%; route: 1.481, 32.039%; tC2Q: 0.290, 6.273%
Required Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%

Path 2

Path Summary:
Slack 0.299
Data Arrival Time 10.700
Data Required Time 10.999
From u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1
To u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_0_s1
Launch Clk i_sclk[R]
Latch Clk i_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 i_sclk
5.000 0.000 tCL FF 1 i_sclk_ibuf/I
5.859 0.859 tINS FF 126 i_sclk_ibuf/O
6.156 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/CLK
6.446 0.290 tC2Q FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/Q
6.742 0.296 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/I0
7.428 0.686 tINS FR 1 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/COUT
7.428 0.000 tNET RR 2 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/CIN
7.472 0.044 tINS RF 1 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/COUT
7.472 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/CIN
7.516 0.044 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/COUT
7.516 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/CIN
7.560 0.044 tINS FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/COUT
7.856 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/I1
8.550 0.694 tINS FF 6 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/F
8.846 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/I0
9.493 0.646 tINS FF 20 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/F
9.789 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/I0
10.475 0.686 tINS FR 5 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/F
10.700 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_0_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 i_clk
10.000 0.000 tCL RR 1 i_clk_ibuf/I
10.853 0.853 tINS RR 106 i_clk_ibuf/O
11.078 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_0_s1/CLK
11.043 -0.035 tUnc u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_0_s1
10.999 -0.044 tSu 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_0_s1
Path Statistics:
Clock Skew: -0.077
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%
Arrival Data Path Delay: cell: 2.845, 62.592%; route: 1.410, 31.027%; tC2Q: 0.290, 6.381%
Required Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%

Path 3

Path Summary:
Slack 0.299
Data Arrival Time 10.700
Data Required Time 10.999
From u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1
To u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_1_s1
Launch Clk i_sclk[R]
Latch Clk i_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 i_sclk
5.000 0.000 tCL FF 1 i_sclk_ibuf/I
5.859 0.859 tINS FF 126 i_sclk_ibuf/O
6.156 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/CLK
6.446 0.290 tC2Q FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/Q
6.742 0.296 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/I0
7.428 0.686 tINS FR 1 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/COUT
7.428 0.000 tNET RR 2 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/CIN
7.472 0.044 tINS RF 1 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/COUT
7.472 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/CIN
7.516 0.044 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/COUT
7.516 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/CIN
7.560 0.044 tINS FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/COUT
7.856 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/I1
8.550 0.694 tINS FF 6 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/F
8.846 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/I0
9.493 0.646 tINS FF 20 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/F
9.789 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/I0
10.475 0.686 tINS FR 5 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/F
10.700 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_1_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 i_clk
10.000 0.000 tCL RR 1 i_clk_ibuf/I
10.853 0.853 tINS RR 106 i_clk_ibuf/O
11.078 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_1_s1/CLK
11.043 -0.035 tUnc u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_1_s1
10.999 -0.044 tSu 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_1_s1
Path Statistics:
Clock Skew: -0.077
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%
Arrival Data Path Delay: cell: 2.845, 62.592%; route: 1.410, 31.027%; tC2Q: 0.290, 6.381%
Required Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%

Path 4

Path Summary:
Slack 0.299
Data Arrival Time 10.700
Data Required Time 10.999
From u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1
To u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_2_s1
Launch Clk i_sclk[R]
Latch Clk i_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 i_sclk
5.000 0.000 tCL FF 1 i_sclk_ibuf/I
5.859 0.859 tINS FF 126 i_sclk_ibuf/O
6.156 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/CLK
6.446 0.290 tC2Q FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/Q
6.742 0.296 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/I0
7.428 0.686 tINS FR 1 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/COUT
7.428 0.000 tNET RR 2 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/CIN
7.472 0.044 tINS RF 1 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/COUT
7.472 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/CIN
7.516 0.044 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/COUT
7.516 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/CIN
7.560 0.044 tINS FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/COUT
7.856 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/I1
8.550 0.694 tINS FF 6 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/F
8.846 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/I0
9.493 0.646 tINS FF 20 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/F
9.789 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/I0
10.475 0.686 tINS FR 5 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/F
10.700 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_2_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 i_clk
10.000 0.000 tCL RR 1 i_clk_ibuf/I
10.853 0.853 tINS RR 106 i_clk_ibuf/O
11.078 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_2_s1/CLK
11.043 -0.035 tUnc u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_2_s1
10.999 -0.044 tSu 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_2_s1
Path Statistics:
Clock Skew: -0.077
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%
Arrival Data Path Delay: cell: 2.845, 62.592%; route: 1.410, 31.027%; tC2Q: 0.290, 6.381%
Required Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%

Path 5

Path Summary:
Slack 0.299
Data Arrival Time 10.700
Data Required Time 10.999
From u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1
To u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_3_s1
Launch Clk i_sclk[R]
Latch Clk i_clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 i_sclk
5.000 0.000 tCL FF 1 i_sclk_ibuf/I
5.859 0.859 tINS FF 126 i_sclk_ibuf/O
6.156 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/CLK
6.446 0.290 tC2Q FF 1 u_rffe_wrapper/u_rffe_slave_inf/command_frame_data_pre_8_s1/Q
6.742 0.296 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/I0
7.428 0.686 tINS FR 1 u_rffe_wrapper/u_rffe_slave_inf/n496_s0/COUT
7.428 0.000 tNET RR 2 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/CIN
7.472 0.044 tINS RF 1 u_rffe_wrapper/u_rffe_slave_inf/n497_s0/COUT
7.472 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/CIN
7.516 0.044 tINS FF 1 u_rffe_wrapper/u_rffe_slave_inf/n498_s0/COUT
7.516 0.000 tNET FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/CIN
7.560 0.044 tINS FF 2 u_rffe_wrapper/u_rffe_slave_inf/n499_s0/COUT
7.856 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/I1
8.550 0.694 tINS FF 6 u_rffe_wrapper/u_rffe_slave_inf/n1450_s0/F
8.846 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/I0
9.493 0.646 tINS FF 20 u_rffe_wrapper/u_rffe_slave_inf/n1518_s3/F
9.789 0.296 tNET FF 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/I0
10.475 0.686 tINS FR 5 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_4_s4/F
10.700 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_3_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 i_clk
10.000 0.000 tCL RR 1 i_clk_ibuf/I
10.853 0.853 tINS RR 106 i_clk_ibuf/O
11.078 0.225 tNET RR 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_3_s1/CLK
11.043 -0.035 tUnc u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_3_s1
10.999 -0.044 tSu 1 u_rffe_wrapper/u_rffe_slave_inf/o_rd_addr_3_s1
Path Statistics:
Clock Skew: -0.077
Setup Relationship: 5.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%
Arrival Data Path Delay: cell: 2.845, 62.592%; route: 1.410, 31.027%; tC2Q: 0.290, 6.381%
Required Clock Path Delay: cell: 0.859, 74.365%; route: 0.296, 25.635%