Timing Messages

Report Title Gowin Timing Analysis Report
Design File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\impl\gwsynthesis\psram_board_test.vg
Physical Constraints File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram.cst
Timing Constraint File E:\myWork\IP\releaseVerify\V1.9.7.02\zipFile\apsram_reference_design\Gowin_PSRAM_HS_V2_refDesign\PSRAM_2CH_HS_V2\GW1NR9-MG100\project\src\psram.sdc
GOWIN version V1.9.7.02Beta
Part Number GW1NR-LV9MG100PC7/I6
Device GW1NR-9C
Created Time Wed Mar 10 15:40:56 2021
Legal Announcement Copyright (C)2014-2021 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C
Hold Delay Model Fast 1.26V 0C
Numbers of Paths Analyzed 4031
Numbers of Endpoints Analyzed 4093
Numbers of Falling Endpoints 9
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
clk_d Base 33.333 30.000 0.000 16.666 clk_d
clk_x2p Base 10.000 100.000 0.000 5.000 u_PSRAM_TOP/clk_x2p
clk Base 20.000 50.000 0.000 10.000 clk
clk_x1 Base 20.000 50.000 0.000 10.000 clk_x1
clk_x2 Base 10.000 100.000 0.000 5.000 memory_clk
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Generated 8.333 120.000 2.083 6.250 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTP
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Generated 25.000 40.000 0.000 12.500 clk_ibuf/I clk your_instance_name/rpll_inst/CLKOUTD3

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk_d 30.000(MHz) 137.869(MHz) 5 TOP
2 clk_x1 50.000(MHz) 79.291(MHz) 6 TOP

No timing paths to get frequency of clk_x2p!

No timing paths to get frequency of clk!

No timing paths to get frequency of clk_x2!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTP.default_gen_clk!

No timing paths to get frequency of your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk_d Setup 0.000 0
clk_d Hold 0.000 0
clk_x2p Setup 0.000 0
clk_x2p Hold 0.000 0
clk Setup 0.000 0
clk Hold 0.000 0
clk_x1 Setup 0.000 0
clk_x1 Hold 0.000 0
clk_x2 Setup 0.000 0
clk_x2 Hold 0.000 0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Setup 0.000 0
your_instance_name/rpll_inst/CLKOUTP.default_gen_clk Hold 0.000 0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Setup 0.000 0
your_instance_name/rpll_inst/CLKOUTD3.default_gen_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 6.110 u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q u_PSRAM_TOP/u_dhcen_clk_x2p/CE clk_d:[R] your_instance_name/rpll_inst/CLKOUTP.default_gen_clk:[F] 6.250 -1.022 0.944
2 7.388 u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q u_test1/error_d_s0/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 12.580
3 10.424 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_test0/error_d_s0/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 9.544
4 11.314 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_16_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.654
5 11.631 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_26_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.337
6 11.651 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_3_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.317
7 11.696 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_29_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.272
8 11.698 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_27_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.270
9 11.794 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_5_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.174
10 11.794 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_12_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.174
11 11.797 u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.171
12 11.797 u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.171
13 11.797 u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.171
14 11.801 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_16_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.167
15 11.801 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_30_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.167
16 11.816 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_3_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.152
17 11.818 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_9_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.149
18 11.839 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_1_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.129
19 11.839 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.129
20 11.839 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_4_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.129
21 11.839 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.129
22 11.847 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_13_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.121
23 11.850 u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_0_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.118
24 11.893 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_0_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.074
25 11.929 u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].id_reg_19_s1/CE clk_x1:[R] clk_x1:[R] 20.000 0.000 8.039

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.412 u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE clk_x1:[R] clk_x1:[R] 0.000 0.000 0.423
2 0.524 u_test1/check_data_4_s3/Q u_test1/check_data_4_s3/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
3 0.524 u_test1/wr_data_add_3_s1/Q u_test1/wr_data_add_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
4 0.524 u_test1/wr_data_add_11_s1/Q u_test1/wr_data_add_11_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
5 0.524 u_test1/RD_CYC_CNT_14_s1/Q u_test1/RD_CYC_CNT_14_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
6 0.524 u_test1/WR_CYC_CNT_3_s1/Q u_test1/WR_CYC_CNT_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
7 0.524 u_test1/WR_CYC_CNT_11_s1/Q u_test1/WR_CYC_CNT_11_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
8 0.524 u_test0/RD_CYC_CNT_0_s3/Q u_test0/RD_CYC_CNT_0_s3/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
9 0.524 u_test0/wr_data_add_11_s1/Q u_test0/wr_data_add_11_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
10 0.524 u_test0/wr_data_add_12_s1/Q u_test0/wr_data_add_12_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
11 0.524 u_test0/addr_add_w_20_s1/Q u_test0/addr_add_w_20_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
12 0.524 u_test0/RD_CYC_CNT_11_s1/Q u_test0/RD_CYC_CNT_11_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
13 0.524 u_test0/WR_CYC_CNT_3_s1/Q u_test0/WR_CYC_CNT_3_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
14 0.524 u_test0/WR_CYC_CNT_5_s1/Q u_test0/WR_CYC_CNT_5_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
15 0.524 u_test0/WR_CYC_CNT_6_s1/Q u_test0/WR_CYC_CNT_6_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
16 0.524 u_test0/WR_CYC_CNT_16_s1/Q u_test0/WR_CYC_CNT_16_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
17 0.524 u_test0/start_cnt_0_s1/Q u_test0/start_cnt_0_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
18 0.524 u_test0/start_cnt_7_s1/Q u_test0/start_cnt_7_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
19 0.524 u_test0/addr_add_r_10_s0/Q u_test0/addr_add_r_10_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
20 0.524 u_test0/addr_add_r_12_s0/Q u_test0/addr_add_r_12_s0/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
21 0.524 u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
22 0.524 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
23 0.524 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
24 0.524 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524
25 0.524 u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/Q u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/D clk_x1:[R] clk_x1:[R] 0.000 0.000 0.524

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
2 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
3 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
4 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
5 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
6 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
7 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
8 28.008 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] 31.667 0.073 3.522
9 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
10 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
11 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
12 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
13 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
14 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
15 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522
16 29.671 u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] 33.334 0.078 3.522

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
2 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
3 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
4 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
5 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
6 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
7 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
8 18.755 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[R] -16.666 0.061 2.070
9 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
10 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
11 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
12 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
13 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
14 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
15 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070
16 20.418 u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET clk_d:[R] clk_x2p:[F] -18.333 0.056 2.070

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0
2 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0
3 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0
4 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0
5 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0
6 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0
7 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_30_s0
8 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/shift_burst128_r_27_s0
9 9.016 9.942 0.926 Low Pulse Width clk_x1 u_PSRAM_TOP/u_psram_top1/rd_data_d_62_s0
10 9.016 9.942 0.926 Low Pulse Width clk_x1 u_test0/addr_add_r_8_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 6.110
Data Arrival Time 1.125
Data Required Time 7.235
From u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0
To u_PSRAM_TOP/u_dhcen_clk_x2p
Launch Clk clk_d:[R]
Latch Clk your_instance_name/rpll_inst/CLKOUTP.default_gen_clk:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_d
0.000 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
0.181 0.181 tNET RR 1 R20C46[0][A] u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/CLK
0.520 0.340 tC2Q RF 9 R20C46[0][A] u_PSRAM_TOP/u_psram_sync/cs_memsync_4_s0/Q
1.125 0.604 tNET FF 1 - u_PSRAM_TOP/u_dhcen_clk_x2p/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
6.250 6.250 active clock edge time
6.250 0.000 your_instance_name/rpll_inst/CLKOUTP.default_gen_clk
7.453 1.203 tCL FF 1 PLL_R your_instance_name/rpll_inst/CLKOUTP
7.453 0.000 tNET FF 3 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKIN
7.423 -0.030 tUnc u_PSRAM_TOP/u_dhcen_clk_x2p
7.235 -0.188 tSu 1 - u_PSRAM_TOP/u_dhcen_clk_x2p

Path Statistics:

Clock Skew 1.022
Setup Relationship 6.250
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.604, 64.025%; tC2Q: 0.340, 35.975%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.000, 0.000%

Path2

Path Summary:

Slack 7.388
Data Arrival Time 12.760
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0
To u_test1/error_d_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R21C30[2][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R21C30[2][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/init_calib_s0/Q
2.270 1.750 tNET FF 1 R18C36[3][B] u_PSRAM_TOP/u_psram_top1/rd_data1_d_61_s/I0
3.035 0.765 tINS FF 1 R18C36[3][B] u_PSRAM_TOP/u_psram_top1/rd_data1_d_61_s/F
3.631 0.596 tNET FF 1 R18C35[3][A] u_test1/n1120_s23/I1
4.445 0.814 tINS FF 1 R18C35[3][A] u_test1/n1120_s23/F
6.125 1.680 tNET FF 1 R18C12[0][B] u_test1/n1120_s10/I2
6.589 0.464 tINS FF 1 R18C12[0][B] u_test1/n1120_s10/F
8.269 1.680 tNET FF 1 R18C35[3][B] u_test1/n1120_s2/I2
9.034 0.765 tINS FF 1 R18C35[3][B] u_test1/n1120_s2/F
11.085 2.051 tNET FF 1 R18C9[3][B] u_test1/n1120_s0/I1
11.871 0.786 tINS FR 1 R18C9[3][B] u_test1/n1120_s0/F
12.760 0.889 tNET RR 1 IOB11[A] u_test1/error_d_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 IOB11[A] u_test1/error_d_s0/CLK
20.149 -0.032 tSu 1 IOB11[A] u_test1/error_d_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 3.594, 28.569%; route: 8.646, 68.731%; tC2Q: 0.340, 2.700%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path3

Path Summary:

Slack 10.424
Data Arrival Time 9.725
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_test0/error_d_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
2.044 1.524 tNET FF 1 R23C21[0][A] u_PSRAM_TOP/u_psram_top0/rd_data0_d_51_s/I0
2.809 0.765 tINS FF 1 R23C21[0][A] u_PSRAM_TOP/u_psram_top0/rd_data0_d_51_s/F
3.058 0.249 tNET FF 1 R23C21[3][A] u_test0/n1120_s13/I3
3.872 0.814 tINS FF 1 R23C21[3][A] u_test0/n1120_s13/F
5.430 1.558 tNET FF 1 R13C14[0][B] u_test0/n1120_s5/I0
6.195 0.765 tINS FF 1 R13C14[0][B] u_test0/n1120_s5/F
7.150 0.955 tNET FF 1 R14C11[3][A] u_test0/n1120_s2/I0
7.964 0.814 tINS FF 1 R14C11[3][A] u_test0/n1120_s2/F
7.968 0.004 tNET FF 1 R14C11[3][B] u_test0/n1120_s0/I1
8.563 0.594 tINS FR 1 R14C11[3][B] u_test0/n1120_s0/F
9.725 1.162 tNET RR 1 IOB15[A] u_test0/error_d_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 IOB15[A] u_test0/error_d_s0/CLK
20.149 -0.032 tSu 1 IOB15[A] u_test0/error_d_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 3.752, 39.318%; route: 5.452, 57.123%; tC2Q: 0.340, 3.559%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path4

Path Summary:

Slack 11.314
Data Arrival Time 8.835
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_16_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/I0
5.930 0.765 tINS FF 36 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/F
6.936 1.006 tNET FF 1 R6C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1450_s0/I2
7.697 0.760 tINS FR 1 R6C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1450_s0/F
8.835 1.138 tNET RR 1 R6C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_16_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R6C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_16_s1/CLK
20.149 -0.032 tSu 1 R6C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_16_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.754, 31.818%; route: 5.561, 64.258%; tC2Q: 0.340, 3.924%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path5

Path Summary:

Slack 11.631
Data Arrival Time 8.518
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_26_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/I0
5.930 0.765 tINS FF 36 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/F
6.927 0.997 tNET FF 1 R7C23[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1440_s0/I2
7.391 0.463 tINS FR 1 R7C23[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1440_s0/F
8.518 1.128 tNET RR 1 R7C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_26_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_26_s1/CLK
20.149 -0.032 tSu 1 R7C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_26_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.456, 29.463%; route: 5.541, 66.464%; tC2Q: 0.340, 4.074%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path6

Path Summary:

Slack 11.651
Data Arrival Time 8.497
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C25[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1459_s1/I2
5.630 0.464 tINS FF 8 R8C25[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1459_s1/F
6.610 0.980 tNET FF 1 R7C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1463_s0/I1
7.370 0.760 tINS FR 1 R7C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1463_s0/F
8.497 1.128 tNET RR 1 R7C22[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C22[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_3_s1/CLK
20.149 -0.032 tSu 1 R7C22[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.453, 29.491%; route: 5.524, 66.425%; tC2Q: 0.340, 4.084%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path7

Path Summary:

Slack 11.696
Data Arrival Time 8.453
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_29_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/I0
5.930 0.765 tINS FF 36 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/F
6.565 0.635 tNET FF 1 R7C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1437_s0/I2
7.325 0.760 tINS FR 1 R7C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1437_s0/F
8.453 1.128 tNET RR 1 R7C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_29_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_29_s1/CLK
20.149 -0.032 tSu 1 R7C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_29_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.754, 33.288%; route: 5.179, 62.607%; tC2Q: 0.340, 4.106%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path8

Path Summary:

Slack 11.698
Data Arrival Time 8.450
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_27_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.563 1.578 tNET FF 1 R7C32[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1903_s0/I2
7.323 0.760 tINS FR 1 R7C32[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1903_s0/F
8.450 1.128 tNET RR 1 R7C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_27_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_27_s1/CLK
20.149 -0.032 tSu 1 R7C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_27_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 35.654%; route: 4.981, 60.239%; tC2Q: 0.340, 4.107%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path9

Path Summary:

Slack 11.794
Data Arrival Time 8.355
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.467 1.482 tNET FF 1 R9C30[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1925_s0/I2
7.227 0.760 tINS FR 1 R9C30[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1925_s0/F
8.355 1.128 tNET RR 1 R9C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_5_s1/CLK
20.149 -0.032 tSu 1 R9C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.071%; route: 4.886, 59.774%; tC2Q: 0.340, 4.155%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path10

Path Summary:

Slack 11.794
Data Arrival Time 8.355
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_12_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.467 1.482 tNET FF 1 R7C30[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s0/I2
7.227 0.760 tINS FR 1 R7C30[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1918_s0/F
8.355 1.128 tNET RR 1 R7C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_12_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_12_s1/CLK
20.149 -0.032 tSu 1 R7C30[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_12_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.071%; route: 4.886, 59.774%; tC2Q: 0.340, 4.155%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path11

Path Summary:

Slack 11.797
Data Arrival Time 8.352
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/CLK
0.520 0.340 tC2Q RF 9 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q
2.097 1.577 tNET FF 1 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
2.862 0.765 tINS FF 2 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
3.474 0.612 tNET FF 1 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
4.261 0.786 tINS FR 8 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
4.578 0.318 tNET RR 1 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
5.343 0.765 tINS RF 8 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
6.435 1.092 tNET FF 1 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/I2
7.221 0.786 tINS FR 3 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/F
8.352 1.131 tNET RR 1 R9C39[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C39[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1/CLK
20.149 -0.032 tSu 1 R9C39[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 3.102, 37.960%; route: 4.730, 57.884%; tC2Q: 0.340, 4.156%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path12

Path Summary:

Slack 11.797
Data Arrival Time 8.352
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/CLK
0.520 0.340 tC2Q RF 9 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q
2.097 1.577 tNET FF 1 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
2.862 0.765 tINS FF 2 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
3.474 0.612 tNET FF 1 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
4.261 0.786 tINS FR 8 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
4.578 0.318 tNET RR 1 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
5.343 0.765 tINS RF 8 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
6.435 1.092 tNET FF 1 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/I2
7.221 0.786 tINS FR 3 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/F
8.352 1.131 tNET RR 1 R9C39[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C39[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1/CLK
20.149 -0.032 tSu 1 R9C39[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 3.102, 37.960%; route: 4.730, 57.884%; tC2Q: 0.340, 4.156%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path13

Path Summary:

Slack 11.797
Data Arrival Time 8.352
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/CLK
0.520 0.340 tC2Q RF 9 R20C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/cmd_en_s0/Q
2.097 1.577 tNET FF 1 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/I1
2.862 0.765 tINS FF 2 R14C36[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s3/F
3.474 0.612 tNET FF 1 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/I2
4.261 0.786 tINS FR 8 R14C37[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/n297_s2/F
4.578 0.318 tNET RR 1 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/I2
5.343 0.765 tINS RF 8 R14C38[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_data_ctrl_s0/F
6.435 1.092 tNET FF 1 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/I2
7.221 0.786 tINS FR 3 R9C39[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_4_s6/F
8.352 1.131 tNET RR 1 R9C39[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C39[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1/CLK
20.149 -0.032 tSu 1 R9C39[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/wr_ptr_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 3.102, 37.960%; route: 4.730, 57.884%; tC2Q: 0.340, 4.156%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path14

Path Summary:

Slack 11.801
Data Arrival Time 8.348
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_16_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.460 1.475 tNET FF 1 R8C29[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1914_s0/I2
7.220 0.760 tINS FR 1 R8C29[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1914_s0/F
8.348 1.128 tNET RR 1 R8C29[2][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_16_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R8C29[2][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_16_s1/CLK
20.149 -0.032 tSu 1 R8C29[2][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_16_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.103%; route: 4.879, 59.739%; tC2Q: 0.340, 4.159%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path15

Path Summary:

Slack 11.801
Data Arrival Time 8.348
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_30_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.460 1.475 tNET FF 1 R7C29[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1900_s0/I2
7.220 0.760 tINS FR 1 R7C29[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1900_s0/F
8.348 1.128 tNET RR 1 R7C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_30_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_30_s1/CLK
20.149 -0.032 tSu 1 R7C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_30_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.103%; route: 4.879, 59.739%; tC2Q: 0.340, 4.159%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path16

Path Summary:

Slack 11.816
Data Arrival Time 8.333
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.445 1.460 tNET FF 1 R9C31[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1927_s0/I2
7.205 0.760 tINS FR 1 R9C31[1][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1927_s0/F
8.333 1.128 tNET RR 1 R9C31[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_3_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C31[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_3_s1/CLK
20.149 -0.032 tSu 1 R9C31[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_3_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.167%; route: 4.864, 59.667%; tC2Q: 0.340, 4.166%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path17

Path Summary:

Slack 11.818
Data Arrival Time 8.330
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_9_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/CLK
0.520 0.340 tC2Q RF 2 R9C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_2_s1/Q
1.115 0.595 tNET FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/I0
1.930 0.814 tINS FF 1 R9C31[0][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s3/F
2.526 0.596 tNET FF 1 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/I3
3.135 0.609 tINS FF 3 R8C30[3][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s1/F
4.220 1.085 tNET FF 1 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/I2
4.985 0.765 tINS FF 36 R14C29[2][B] u_PSRAM_TOP/u_psram_top1/u_psram_init/n2451_s4/F
6.467 1.482 tNET FF 1 R7C30[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1921_s0/I2
7.227 0.760 tINS FR 1 R7C30[3][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1921_s0/F
8.330 1.103 tNET RR 1 R7C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_9_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_9_s1/CLK
20.149 -0.032 tSu 1 R7C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].id_reg_9_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.948, 36.180%; route: 4.861, 59.653%; tC2Q: 0.340, 4.167%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path18

Path Summary:

Slack 11.839
Data Arrival Time 8.310
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
3.689 3.169 tNET FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/I0
4.454 0.765 tINS FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/F
5.421 0.967 tNET FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/I3
6.236 0.814 tINS FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/F
7.313 1.077 tNET FF 1 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/I2
7.776 0.463 tINS FR 6 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/F
8.310 0.534 tNET RR 1 R9C23[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_1_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C23[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_1_s1/CLK
20.149 -0.032 tSu 1 R9C23[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.042, 25.123%; route: 5.747, 70.699%; tC2Q: 0.340, 4.178%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path19

Path Summary:

Slack 11.839
Data Arrival Time 8.310
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
3.689 3.169 tNET FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/I0
4.454 0.765 tINS FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/F
5.421 0.967 tNET FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/I3
6.236 0.814 tINS FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/F
7.313 1.077 tNET FF 1 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/I2
7.776 0.463 tINS FR 6 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/F
8.310 0.534 tNET RR 1 R9C23[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C23[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK
20.149 -0.032 tSu 1 R9C23[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.042, 25.123%; route: 5.747, 70.699%; tC2Q: 0.340, 4.178%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path20

Path Summary:

Slack 11.839
Data Arrival Time 8.310
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
3.689 3.169 tNET FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/I0
4.454 0.765 tINS FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/F
5.421 0.967 tNET FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/I3
6.236 0.814 tINS FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/F
7.313 1.077 tNET FF 1 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/I2
7.776 0.463 tINS FR 6 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/F
8.310 0.534 tNET RR 1 R9C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_4_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_4_s1/CLK
20.149 -0.032 tSu 1 R9C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.042, 25.123%; route: 5.747, 70.699%; tC2Q: 0.340, 4.178%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path21

Path Summary:

Slack 11.839
Data Arrival Time 8.310
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
3.689 3.169 tNET FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/I0
4.454 0.765 tINS FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/F
5.421 0.967 tNET FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/I3
6.236 0.814 tINS FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/F
7.313 1.077 tNET FF 1 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/I2
7.776 0.463 tINS FR 6 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/F
8.310 0.534 tNET RR 1 R9C23[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C23[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s1/CLK
20.149 -0.032 tSu 1 R9C23[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.042, 25.123%; route: 5.747, 70.699%; tC2Q: 0.340, 4.178%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path22

Path Summary:

Slack 11.847
Data Arrival Time 8.302
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_13_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/I0
5.930 0.765 tINS FF 36 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/F
6.580 0.650 tNET FF 1 R7C25[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1453_s0/I2
7.174 0.594 tINS FR 1 R7C25[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1453_s0/F
8.302 1.128 tNET RR 1 R7C25[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_13_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R7C25[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_13_s1/CLK
20.149 -0.032 tSu 1 R7C25[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_13_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.588, 31.863%; route: 5.194, 63.955%; tC2Q: 0.340, 4.182%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path23

Path Summary:

Slack 11.850
Data Arrival Time 8.299
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.520 0.340 tC2Q RF 169 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/Q
3.689 3.169 tNET FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/I0
4.454 0.765 tINS FF 1 R14C16[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s16/F
5.421 0.967 tNET FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/I3
6.236 0.814 tINS FF 1 R14C20[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s6/F
7.313 1.077 tNET FF 1 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/I2
7.776 0.463 tINS FR 6 R9C22[2][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_5_s3/F
8.299 0.523 tNET RR 1 R9C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R9C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_0_s1/CLK
20.149 -0.032 tSu 1 R9C24[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.042, 25.156%; route: 5.736, 70.660%; tC2Q: 0.340, 4.184%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path24

Path Summary:

Slack 11.893
Data Arrival Time 8.255
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/CLK
0.520 0.340 tC2Q RF 6 R20C22[1][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].check_cnt_0_s1/Q
1.380 0.859 tNET FF 1 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/I0
1.844 0.464 tINS FF 2 R16C23[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s2/F
2.100 0.256 tNET FF 1 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/I3
2.865 0.765 tINS FF 39 R16C23[3][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1402_s0/F
5.166 2.301 tNET FF 1 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/I0
5.930 0.765 tINS FF 36 R8C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2419_s4/F
6.578 0.648 tNET FF 1 R6C25[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1466_s0/I2
7.365 0.786 tINS FR 1 R6C25[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1466_s0/F
8.255 0.891 tNET RR 1 R6C25[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_0_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R6C25[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_0_s1/CLK
20.149 -0.032 tSu 1 R6C25[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[0].id_reg_0_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.779, 34.423%; route: 4.955, 61.370%; tC2Q: 0.340, 4.206%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Path25

Path Summary:

Slack 11.929
Data Arrival Time 8.220
Data Required Time 20.149
From u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1
To u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].id_reg_19_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.181 0.181 tNET RR 1 R9C23[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK
0.520 0.340 tC2Q RR 4 R9C23[1][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].check_cnt_2_s1/Q
0.836 0.315 tNET RR 1 R9C23[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1866_s1/I0
1.650 0.814 tINS RF 33 R9C23[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1866_s1/F
2.648 0.998 tNET FF 1 R11C26[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1866_s0/I1
3.413 0.765 tINS FF 8 R11C26[3][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1866_s0/F
4.380 0.967 tNET FF 1 R14C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2451_s4/I1
5.145 0.765 tINS FF 36 R14C24[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n2451_s4/F
6.498 1.354 tNET FF 1 R11C27[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1911_s0/I2
7.092 0.594 tINS FR 1 R11C27[0][B] u_PSRAM_TOP/u_psram_top0/u_psram_init/n1911_s0/F
8.220 1.128 tNET RR 1 R11C27[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].id_reg_19_s1/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
20.000 20.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
20.181 0.181 tNET RR 1 R11C27[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].id_reg_19_s1/CLK
20.149 -0.032 tSu 1 R11C27[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/read_calibration[1].id_reg_19_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 20.000
Logic Level 5
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 2.938, 36.547%; route: 4.762, 59.229%; tC2Q: 0.340, 4.225%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.412
Data Arrival Time 0.560
Data Required Time 0.148
From u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R18C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/CLK
0.384 0.247 tC2Q RR 2 R18C26[0][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/c_state.INIT_CALIB_DONE_s0/Q
0.560 0.176 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CE

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0/CLK
0.148 0.011 tHld 1 R18C26[2][A] u_PSRAM_TOP/u_psram_top0/u_psram_init/init_calib_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/check_data_4_s3
To u_test1/check_data_4_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R20C12[1][A] u_test1/check_data_4_s3/CLK
0.384 0.247 tC2Q RR 5 R20C12[1][A] u_test1/check_data_4_s3/Q
0.386 0.002 tNET RR 1 R20C12[1][A] u_test1/n1051_s4/I2
0.661 0.276 tINS RF 1 R20C12[1][A] u_test1/n1051_s4/F
0.661 0.000 tNET FF 1 R20C12[1][A] u_test1/check_data_4_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R20C12[1][A] u_test1/check_data_4_s3/CLK
0.137 0.000 tHld 1 R20C12[1][A] u_test1/check_data_4_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/wr_data_add_3_s1
To u_test1/wr_data_add_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R22C14[1][A] u_test1/wr_data_add_3_s1/CLK
0.384 0.247 tC2Q RR 3 R22C14[1][A] u_test1/wr_data_add_3_s1/Q
0.386 0.002 tNET RR 1 R22C14[1][A] u_test1/n685_s1/I2
0.661 0.276 tINS RF 1 R22C14[1][A] u_test1/n685_s1/F
0.661 0.000 tNET FF 1 R22C14[1][A] u_test1/wr_data_add_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R22C14[1][A] u_test1/wr_data_add_3_s1/CLK
0.137 0.000 tHld 1 R22C14[1][A] u_test1/wr_data_add_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/wr_data_add_11_s1
To u_test1/wr_data_add_11_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R18C13[0][A] u_test1/wr_data_add_11_s1/CLK
0.384 0.247 tC2Q RR 3 R18C13[0][A] u_test1/wr_data_add_11_s1/Q
0.386 0.002 tNET RR 1 R18C13[0][A] u_test1/n677_s1/I2
0.661 0.276 tINS RF 1 R18C13[0][A] u_test1/n677_s1/F
0.661 0.000 tNET FF 1 R18C13[0][A] u_test1/wr_data_add_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R18C13[0][A] u_test1/wr_data_add_11_s1/CLK
0.137 0.000 tHld 1 R18C13[0][A] u_test1/wr_data_add_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/RD_CYC_CNT_14_s1
To u_test1/RD_CYC_CNT_14_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R15C8[1][A] u_test1/RD_CYC_CNT_14_s1/CLK
0.384 0.247 tC2Q RR 4 R15C8[1][A] u_test1/RD_CYC_CNT_14_s1/Q
0.386 0.002 tNET RR 1 R15C8[1][A] u_test1/n358_s1/I3
0.661 0.276 tINS RF 1 R15C8[1][A] u_test1/n358_s1/F
0.661 0.000 tNET FF 1 R15C8[1][A] u_test1/RD_CYC_CNT_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R15C8[1][A] u_test1/RD_CYC_CNT_14_s1/CLK
0.137 0.000 tHld 1 R15C8[1][A] u_test1/RD_CYC_CNT_14_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path6

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/WR_CYC_CNT_3_s1
To u_test1/WR_CYC_CNT_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C11[0][A] u_test1/WR_CYC_CNT_3_s1/CLK
0.384 0.247 tC2Q RR 2 R16C11[0][A] u_test1/WR_CYC_CNT_3_s1/Q
0.386 0.002 tNET RR 1 R16C11[0][A] u_test1/n233_s1/I3
0.661 0.276 tINS RF 1 R16C11[0][A] u_test1/n233_s1/F
0.661 0.000 tNET FF 1 R16C11[0][A] u_test1/WR_CYC_CNT_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C11[0][A] u_test1/WR_CYC_CNT_3_s1/CLK
0.137 0.000 tHld 1 R16C11[0][A] u_test1/WR_CYC_CNT_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path7

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test1/WR_CYC_CNT_11_s1
To u_test1/WR_CYC_CNT_11_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R15C11[1][A] u_test1/WR_CYC_CNT_11_s1/CLK
0.384 0.247 tC2Q RR 3 R15C11[1][A] u_test1/WR_CYC_CNT_11_s1/Q
0.386 0.002 tNET RR 1 R15C11[1][A] u_test1/n225_s1/I3
0.661 0.276 tINS RF 1 R15C11[1][A] u_test1/n225_s1/F
0.661 0.000 tNET FF 1 R15C11[1][A] u_test1/WR_CYC_CNT_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R15C11[1][A] u_test1/WR_CYC_CNT_11_s1/CLK
0.137 0.000 tHld 1 R15C11[1][A] u_test1/WR_CYC_CNT_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path8

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/RD_CYC_CNT_0_s3
To u_test0/RD_CYC_CNT_0_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R8C9[0][A] u_test0/RD_CYC_CNT_0_s3/CLK
0.384 0.247 tC2Q RR 5 R8C9[0][A] u_test0/RD_CYC_CNT_0_s3/Q
0.386 0.002 tNET RR 1 R8C9[0][A] u_test0/n372_s3/I3
0.661 0.276 tINS RF 1 R8C9[0][A] u_test0/n372_s3/F
0.661 0.000 tNET FF 1 R8C9[0][A] u_test0/RD_CYC_CNT_0_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R8C9[0][A] u_test0/RD_CYC_CNT_0_s3/CLK
0.137 0.000 tHld 1 R8C9[0][A] u_test0/RD_CYC_CNT_0_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path9

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/wr_data_add_11_s1
To u_test0/wr_data_add_11_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R6C11[1][A] u_test0/wr_data_add_11_s1/CLK
0.384 0.247 tC2Q RR 3 R6C11[1][A] u_test0/wr_data_add_11_s1/Q
0.386 0.002 tNET RR 1 R6C11[1][A] u_test0/n677_s1/I2
0.661 0.276 tINS RF 1 R6C11[1][A] u_test0/n677_s1/F
0.661 0.000 tNET FF 1 R6C11[1][A] u_test0/wr_data_add_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R6C11[1][A] u_test0/wr_data_add_11_s1/CLK
0.137 0.000 tHld 1 R6C11[1][A] u_test0/wr_data_add_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path10

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/wr_data_add_12_s1
To u_test0/wr_data_add_12_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R6C14[1][A] u_test0/wr_data_add_12_s1/CLK
0.384 0.247 tC2Q RR 3 R6C14[1][A] u_test0/wr_data_add_12_s1/Q
0.386 0.002 tNET RR 1 R6C14[1][A] u_test0/n676_s1/I2
0.661 0.276 tINS RF 1 R6C14[1][A] u_test0/n676_s1/F
0.661 0.000 tNET FF 1 R6C14[1][A] u_test0/wr_data_add_12_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R6C14[1][A] u_test0/wr_data_add_12_s1/CLK
0.137 0.000 tHld 1 R6C14[1][A] u_test0/wr_data_add_12_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path11

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/addr_add_w_20_s1
To u_test0/addr_add_w_20_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R8C11[0][A] u_test0/addr_add_w_20_s1/CLK
0.384 0.247 tC2Q RR 2 R8C11[0][A] u_test0/addr_add_w_20_s1/Q
0.386 0.002 tNET RR 1 R8C11[0][A] u_test0/n731_s1/I2
0.661 0.276 tINS RF 1 R8C11[0][A] u_test0/n731_s1/F
0.661 0.000 tNET FF 1 R8C11[0][A] u_test0/addr_add_w_20_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R8C11[0][A] u_test0/addr_add_w_20_s1/CLK
0.137 0.000 tHld 1 R8C11[0][A] u_test0/addr_add_w_20_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path12

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/RD_CYC_CNT_11_s1
To u_test0/RD_CYC_CNT_11_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C6[0][A] u_test0/RD_CYC_CNT_11_s1/CLK
0.384 0.247 tC2Q RR 4 R14C6[0][A] u_test0/RD_CYC_CNT_11_s1/Q
0.386 0.002 tNET RR 1 R14C6[0][A] u_test0/n361_s4/I1
0.661 0.276 tINS RF 1 R14C6[0][A] u_test0/n361_s4/F
0.661 0.000 tNET FF 1 R14C6[0][A] u_test0/RD_CYC_CNT_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C6[0][A] u_test0/RD_CYC_CNT_11_s1/CLK
0.137 0.000 tHld 1 R14C6[0][A] u_test0/RD_CYC_CNT_11_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path13

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/WR_CYC_CNT_3_s1
To u_test0/WR_CYC_CNT_3_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R9C7[1][A] u_test0/WR_CYC_CNT_3_s1/CLK
0.384 0.247 tC2Q RR 2 R9C7[1][A] u_test0/WR_CYC_CNT_3_s1/Q
0.386 0.002 tNET RR 1 R9C7[1][A] u_test0/n233_s1/I3
0.661 0.276 tINS RF 1 R9C7[1][A] u_test0/n233_s1/F
0.661 0.000 tNET FF 1 R9C7[1][A] u_test0/WR_CYC_CNT_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R9C7[1][A] u_test0/WR_CYC_CNT_3_s1/CLK
0.137 0.000 tHld 1 R9C7[1][A] u_test0/WR_CYC_CNT_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path14

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/WR_CYC_CNT_5_s1
To u_test0/WR_CYC_CNT_5_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C7[0][A] u_test0/WR_CYC_CNT_5_s1/CLK
0.384 0.247 tC2Q RR 3 R14C7[0][A] u_test0/WR_CYC_CNT_5_s1/Q
0.386 0.002 tNET RR 1 R14C7[0][A] u_test0/n231_s1/I3
0.661 0.276 tINS RF 1 R14C7[0][A] u_test0/n231_s1/F
0.661 0.000 tNET FF 1 R14C7[0][A] u_test0/WR_CYC_CNT_5_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C7[0][A] u_test0/WR_CYC_CNT_5_s1/CLK
0.137 0.000 tHld 1 R14C7[0][A] u_test0/WR_CYC_CNT_5_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path15

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/WR_CYC_CNT_6_s1
To u_test0/WR_CYC_CNT_6_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C7[1][A] u_test0/WR_CYC_CNT_6_s1/CLK
0.384 0.247 tC2Q RR 2 R14C7[1][A] u_test0/WR_CYC_CNT_6_s1/Q
0.386 0.002 tNET RR 1 R14C7[1][A] u_test0/n230_s1/I3
0.661 0.276 tINS RF 1 R14C7[1][A] u_test0/n230_s1/F
0.661 0.000 tNET FF 1 R14C7[1][A] u_test0/WR_CYC_CNT_6_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R14C7[1][A] u_test0/WR_CYC_CNT_6_s1/CLK
0.137 0.000 tHld 1 R14C7[1][A] u_test0/WR_CYC_CNT_6_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path16

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/WR_CYC_CNT_16_s1
To u_test0/WR_CYC_CNT_16_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R11C7[1][A] u_test0/WR_CYC_CNT_16_s1/CLK
0.384 0.247 tC2Q RR 2 R11C7[1][A] u_test0/WR_CYC_CNT_16_s1/Q
0.386 0.002 tNET RR 1 R11C7[1][A] u_test0/n220_s1/I3
0.661 0.276 tINS RF 1 R11C7[1][A] u_test0/n220_s1/F
0.661 0.000 tNET FF 1 R11C7[1][A] u_test0/WR_CYC_CNT_16_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R11C7[1][A] u_test0/WR_CYC_CNT_16_s1/CLK
0.137 0.000 tHld 1 R11C7[1][A] u_test0/WR_CYC_CNT_16_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path17

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/start_cnt_0_s1
To u_test0/start_cnt_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R7C6[0][A] u_test0/start_cnt_0_s1/CLK
0.384 0.247 tC2Q RR 6 R7C6[0][A] u_test0/start_cnt_0_s1/Q
0.386 0.002 tNET RR 1 R7C6[0][A] u_test0/n94_s2/I0
0.661 0.276 tINS RF 1 R7C6[0][A] u_test0/n94_s2/F
0.661 0.000 tNET FF 1 R7C6[0][A] u_test0/start_cnt_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R7C6[0][A] u_test0/start_cnt_0_s1/CLK
0.137 0.000 tHld 1 R7C6[0][A] u_test0/start_cnt_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path18

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/start_cnt_7_s1
To u_test0/start_cnt_7_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R7C6[1][A] u_test0/start_cnt_7_s1/CLK
0.384 0.247 tC2Q RR 2 R7C6[1][A] u_test0/start_cnt_7_s1/Q
0.386 0.002 tNET RR 1 R7C6[1][A] u_test0/n95_s2/I3
0.661 0.276 tINS RF 1 R7C6[1][A] u_test0/n95_s2/F
0.661 0.000 tNET FF 1 R7C6[1][A] u_test0/start_cnt_7_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R7C6[1][A] u_test0/start_cnt_7_s1/CLK
0.137 0.000 tHld 1 R7C6[1][A] u_test0/start_cnt_7_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path19

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/addr_add_r_10_s0
To u_test0/addr_add_r_10_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R12C14[0][A] u_test0/addr_add_r_10_s0/CLK
0.384 0.247 tC2Q RR 5 R12C14[0][A] u_test0/addr_add_r_10_s0/Q
0.386 0.002 tNET RR 1 R12C14[0][A] u_test0/n554_s1/I0
0.661 0.276 tINS RF 1 R12C14[0][A] u_test0/n554_s1/F
0.661 0.000 tNET FF 1 R12C14[0][A] u_test0/addr_add_r_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R12C14[0][A] u_test0/addr_add_r_10_s0/CLK
0.137 0.000 tHld 1 R12C14[0][A] u_test0/addr_add_r_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path20

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_test0/addr_add_r_12_s0
To u_test0/addr_add_r_12_s0
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R12C14[1][A] u_test0/addr_add_r_12_s0/CLK
0.384 0.247 tC2Q RR 5 R12C14[1][A] u_test0/addr_add_r_12_s0/Q
0.386 0.002 tNET RR 1 R12C14[1][A] u_test0/n552_s1/I2
0.661 0.276 tINS RF 1 R12C14[1][A] u_test0/n552_s1/F
0.661 0.000 tNET FF 1 R12C14[1][A] u_test0/addr_add_r_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R12C14[1][A] u_test0/addr_add_r_12_s0/CLK
0.137 0.000 tHld 1 R12C14[1][A] u_test0/addr_add_r_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path21

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3
To u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/CLK
0.384 0.247 tC2Q RR 2 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/Q
0.386 0.002 tNET RR 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1162_s4/I2
0.661 0.276 tINS RF 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1162_s4/F
0.661 0.000 tNET FF 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3/CLK
0.137 0.000 tHld 1 R20C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/timer_cnt1_3_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path22

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/CLK
0.384 0.247 tC2Q RR 3 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/Q
0.386 0.002 tNET RR 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1485_s3/I0
0.661 0.276 tINS RF 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1485_s3/F
0.661 0.000 tNET FF 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1/CLK
0.137 0.000 tHld 1 R16C29[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].times_reg_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path23

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK
0.384 0.247 tC2Q RR 4 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/Q
0.386 0.002 tNET RR 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1844_s1/I3
0.661 0.276 tINS RF 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1844_s1/F
0.661 0.000 tNET FF 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1/CLK
0.137 0.000 tHld 1 R11C29[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[1].check_cnt_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path24

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/CLK
0.384 0.247 tC2Q RR 5 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/Q
0.386 0.002 tNET RR 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1381_s1/I2
0.661 0.276 tINS RF 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1381_s1/F
0.661 0.000 tNET FF 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1/CLK
0.137 0.000 tHld 1 R16C32[1][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Path25

Path Summary:

Slack 0.524
Data Arrival Time 0.661
Data Required Time 0.137
From u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1
To u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1
Launch Clk clk_x1:[R]
Latch Clk clk_x1:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/CLK
0.384 0.247 tC2Q RR 3 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/Q
0.386 0.002 tNET RR 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1378_s1/I1
0.661 0.276 tINS RF 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/n1378_s1/F
0.661 0.000 tNET FF 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk_x1
0.000 0.000 tCL RR 1391 LEFTSIDE[0] u_PSRAM_TOP/clkdiv/CLKOUT
0.137 0.137 tNET RR 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1/CLK
0.137 0.000 tHld 1 R16C31[0][A] u_PSRAM_TOP/u_psram_top1/u_psram_init/read_calibration[0].check_cnt_4_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path2

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path3

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path4

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path5

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path6

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path7

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path8

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path9

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
100.040 -0.033 tSu 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path10

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
100.040 -0.033 tSu 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path11

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
100.040 -0.033 tSu 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path12

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
100.040 -0.033 tSu 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path13

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
100.040 -0.033 tSu 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path14

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
100.040 -0.033 tSu 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path15

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
100.040 -0.033 tSu 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Path16

Path Summary:

Slack 29.671
Data Arrival Time 70.369
Data Required Time 100.040
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.847 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
67.186 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
67.923 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
68.532 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
70.369 1.837 tNET FF 2 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
100.000 100.000 active clock edge time
100.000 0.000 clk_x2p
100.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
100.103 0.103 tNET RR 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
100.073 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
100.040 -0.033 tSu 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.078
Setup Relationship 33.334
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.103, 100.000%

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path2

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path3

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path4

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path5

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path6

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path7

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path8

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path9

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
15.121 0.011 tHld 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path10

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
15.121 0.011 tHld 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path11

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
15.121 0.011 tHld 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path12

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
15.121 0.011 tHld 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path13

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
15.121 0.011 tHld 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path14

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
15.121 0.011 tHld 1 IOL24[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path15

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
15.121 0.011 tHld 1 IOL7[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Path16

Path Summary:

Slack 20.418
Data Arrival Time 35.540
Data Required Time 15.121
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.470 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
33.717 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
33.897 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
34.433 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
35.540 1.107 tNET RR 2 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
15.000 15.000 active clock edge time
15.000 0.000 clk_x2p
15.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
15.080 0.080 tNET FF 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
15.110 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
15.121 0.011 tHld 1 IOL8[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.056
Hold Relationship -18.333
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.080, 100.000%

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_63_s0/CLK

MPW2

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_47_s0/CLK

MPW3

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_39_s0/CLK

MPW4

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_35_s0/CLK

MPW5

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_33_s0/CLK

MPW6

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/rd_data_d_32_s0/CLK

MPW7

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_30_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_30_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[0].u_psram_lane/shift_burst128_r_30_s0/CLK

MPW8

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/shift_burst128_r_27_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/shift_burst128_r_27_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/shift_burst128_r_27_s0/CLK

MPW9

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_PSRAM_TOP/u_psram_top1/rd_data_d_62_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_PSRAM_TOP/u_psram_top1/rd_data_d_62_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_PSRAM_TOP/u_psram_top1/rd_data_d_62_s0/CLK

MPW10

MPW Summary:

Slack: 9.016
Actual Width: 9.942
Required Width: 0.926
Type: Low Pulse Width
Clock: clk_x1
Objects: u_test0/addr_add_r_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
10.000 0.000 active clock edge time
10.000 0.000 clk_x1
10.000 0.000 tCL FF u_PSRAM_TOP/clkdiv/CLKOUT
10.195 0.195 tNET FF u_test0/addr_add_r_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
20.000 0.000 active clock edge time
20.000 0.000 clk_x1
20.000 0.000 tCL RR u_PSRAM_TOP/clkdiv/CLKOUT
20.137 0.137 tNET RR u_test0/addr_add_r_8_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
1391 clk_x1 7.388 0.195
1025 ddr_rsti 28.008 2.203
169 init_calib0_d 10.424 3.169
169 init_calib1_d 7.388 2.976
65 rd_data_valid_d1_0[1] 17.342 1.483
65 rd_data_valid_d1[0] 16.357 2.310
65 rd_data_valid_d1[0] 17.173 1.377
65 rd_data_valid_d1_0[1] 17.197 1.376
64 wr_dq_29_8 13.370 1.107
64 wr_dq_29_8 12.044 1.582

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R8C24 63.89%
R10C21 56.94%
R10C23 56.94%
R20C10 55.56%
R10C22 55.56%
R20C12 54.17%
R10C24 54.17%
R12C30 51.39%
R11C20 51.39%
R11C30 50.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

Timing Path Constraint[1]: set_multicycle_path -from [get_clocks {clk_x1}] -to [get_clocks {clk_x2}] -setup -end 2

No timing paths to report!

Timing Path Constraint[2]: set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -setup -end 4

Path1

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path2

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path3

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path4

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path5

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

Timing Path Constraint[1]: set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -hold -end 4

Path1

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path2

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path3

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path4

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path5

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

Timing Path Constraint[1]: set_multicycle_path -from [get_clocks {clk_x1}] -to [get_clocks {clk_x2}] -setup -end 2

No timing paths to report!

Timing Path Constraint[2]: set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -setup -end 4

Path1

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path2

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path3

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path4

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
65.044 -0.033 tSu 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Path5

Path Summary:

Slack 28.008
Data Arrival Time 37.036
Data Required Time 65.044
From u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[F]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
33.333 33.333 active clock edge time
33.333 0.000 clk_d
33.333 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
33.514 0.181 tNET RR 1 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/CLK
33.853 0.340 tC2Q RF 10 R6C32[0][B] u_PSRAM_TOP/u_psram_sync/cs_memsync_3_s0/Q
34.590 0.737 tNET FF 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I0
35.199 0.609 tINS FF 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
37.036 1.837 tNET FF 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
65.000 65.000 active clock edge time
65.000 0.000 clk_x2p
65.000 0.000 tCL FF 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
65.108 0.108 tNET FF 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
65.078 -0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
65.044 -0.033 tSu 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.073
Setup Relationship 31.667
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.181, 100.000%
Arrival Data Path Delay cell: 0.609, 17.293%; route: 2.574, 73.065%; tC2Q: 0.340, 9.642%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.108, 100.000%

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

Timing Path Constraint[1]: set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -hold -end 4

Path1

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR23[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path2

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR22[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path3

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOR8[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path4

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen
50.117 0.011 tHld 1 IOR7[A] u_PSRAM_TOP/u_psram_top1/u_psram_wd/data_lane_gen[0].u_psram_lane/genclkpos.u_ck_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Path5

Path Summary:

Slack 18.755
Data Arrival Time 68.873
Data Required Time 50.117
From u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0
To u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
Launch Clk clk_d:[R]
Latch Clk clk_x2p:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
66.666 66.666 active clock edge time
66.666 0.000 clk_d
66.666 0.000 tCL RR 31 PLL_R your_instance_name/rpll_inst/CLKOUTD
66.803 0.137 tNET RR 1 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/CLK
67.050 0.247 tC2Q RR 2 R6C28[0][A] u_PSRAM_TOP/u_psram_sync/ddr_rst_d1_s0/Q
67.230 0.180 tNET RR 1 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/I1
67.766 0.536 tINS RR 1025 R6C28[3][A] u_PSRAM_TOP/u_psram_sync/ddr_rsti_s0/F
68.873 1.107 tNET RR 2 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
50.000 50.000 active clock edge time
50.000 0.000 clk_x2p
50.000 0.000 tCL RR 8 - u_PSRAM_TOP/u_dhcen_clk_x2p/CLKOUT
50.076 0.076 tNET RR 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen/FCLK
50.106 0.030 tUnc u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen
50.117 0.011 tHld 1 IOL23[A] u_PSRAM_TOP/u_psram_top0/u_psram_wd/data_lane_gen[1].u_psram_lane/genclkpos.u_ckn_gen

Path Statistics:

Clock Skew -0.061
Hold Relationship -16.666
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.137, 100.000%
Arrival Data Path Delay cell: 0.536, 25.919%; route: 1.286, 62.148%; tC2Q: 0.247, 11.933%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.076, 100.000%

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk_d -period 33.333 -waveform {0 16.666} [get_nets {clk_d}]
TC_CLOCK Actived create_clock -name clk_x2p -period 10 -waveform {0 5} [get_nets {u_PSRAM_TOP/clk_x2p}]
TC_CLOCK Actived create_clock -name clk -period 20 -waveform {0 10} [get_ports {clk}]
TC_CLOCK Actived create_clock -name clk_x1 -period 20 -waveform {0 10} [get_nets {clk_x1}]
TC_CLOCK Actived create_clock -name clk_x2 -period 10 -waveform {0 5} [get_nets {memory_clk}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_x1}] -to [get_clocks {clk_x2 clk clk_d clk_x2p}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk}] -to [get_clocks {clk_x2 clk_x1 clk_d clk_x2p}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_x2}] -to [get_clocks {clk_x1 clk clk_d clk_x2p}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_d}] -to [get_clocks {clk clk_x2 clk_x1 clk_x2p}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk_x2p}] -to [get_clocks {clk clk_x2 clk_x1}]
TC_MULTICYCLE Actived set_multicycle_path -from [get_clocks {clk_x1}] -to [get_clocks {clk_x2}] -setup -end 2
TC_MULTICYCLE Actived set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -setup -end 4
TC_MULTICYCLE Actived set_multicycle_path -from [get_clocks {clk_d}] -to [get_clocks {clk_x2p}] -hold -end 4
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clk_x1 clk_x2}]